JPS6239918A - Phase locked loop oscillation circuit - Google Patents

Abstract

PURPOSE:To reduce remarkably the time required for re-locking by setting properly an initial phase of a frequency divider in response to the phase of a reference signal input. CONSTITUTION:An output 14 of a detector 11 is set by the 1st rising pulse of a reference signal input 1. An aperture gate generator 12 generates a single short gate pulse 15 while receiving the rising of the output 14. In applying the gate pulse 15 and the reference signal input 1 to an AND circuit 13, a reset pulse 16 is obtained as the output. An output 6 of a digital frequency divider 5 is subjected to self-running while applying 1/n frequency division to the output of a VCO4, and when the reference signal input 1 is fed at first, the count is set initially by a reset pulse 16, resulting in that the phase of the output 6 to the reference signal input 1 is set forcibly to have a minimized phase difference.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that accelerates the pull-in time in a frame phase synchronized oscillator circuit used in a one-time division multiplexer or the like.

[Conventional technology]

FIG. 5 is a block diagram showing a conventional phase-locked oscillator circuit, and FIGS. 6 to 11 are detailed in technical data relating to MC4044 manufactured by Motorola, Inc., USA.

FIG. 2 is a circuit configuration diagram of each part in a conventional phase-locked oscillation circuit, and a diagram for explaining its operation. In FIG. 5, 1 is the reference signal input of the phase synchronized oscillation circuit, 2 is the phase detector, 3 is the integrator, 4 is the voltage controlled oscillator (VCO), 5 is the digital frequency divider, and 6 is the digital frequency divider 5. This output 6 is applied to the other input (comparison input) of the phase detector 2. FIG. 6 shows a specific configuration example of the phase detector 2, where 17 is a functional block which is a circuit that performs the operations shown in FIGS. 8 and 9, R1 is a load resistance of the functional block 17, Resistor R and capacitor C1 constitute a low-pass filter. Figure 7 shows a specific example of the configuration of the integrator 3. In Figure 1, each resistor R, , R, and capacitor C1 are constants that determine the integration time constant, and 11 is an operational amplifier with a very large DC gain. It is. 10 shows the phase comparison characteristic of the phase detector 2, and FIG. 11 shows the phase comparison characteristic of the phase detector 2 and the integrator 3.

Next, the operation of the above-described conventional phase synchronization excavation circuit will be explained. The output of the VCO 4 is frequency-divided by n by a digital frequency divider 5 and applied to the comparison input (input V in FIG. 6) of the 1-phase detector 2. on the other hand.

At almost the same period as this, the reference signal 1 is output to the phase detector 2.
is applied to the other input (input R in FIG. 6). The one-phase detector 2 operates as follows. In Fig. 6, considering various phase relationships of each human power R and V,
As shown in FIGS. 8 and 9. That is, if the input R is ahead of the input V in phase as shown in FIG. A positive pulse is obtained from the falling edge of V to the falling edge of the input V pulse.

Conversely, if the input V is ahead of the input R in phase, a negative pulse will be obtained as the output U from the fall of the input V to the fall of the human power R, as shown in Figure 9. . This is resistance R.

and a low pass filter consisting of capacitor C1.

A DC voltage 7 corresponding to the phase difference between the input R and the input ■ is obtained. As can be seen from this explanation, the width of the positive or negative pulse obtained at the output U is proportional to the phase difference between the inputs R and V, so the phase comparison characteristic of the single-phase detector 2 is shown in FIG. 10. get something

By passing the output of the phase detector 2 obtained in this way through an integrator 3 called a loop filter, the VCO 4
Appropriate negative feedback is applied to the circuit shown in FIG. 5, and phase synchronization is applied so that the phase difference between input R and input V becomes almost zero in the entire circuit shown in FIG. FIG. 11 shows the phase detector 2.
Integrator 3. The output frequency of the VCO4 is controlled in the range of f+ and f- according to the phase difference between the input V and the input R, and the output frequency of the VCO4 is generally The frequency cannot change infinitely, and the DC gain of the integrator 3 is very large, so at the output frequencies f+ and f- of the VCO 4, which correspond to a phase difference ψ or ψ- which is considerably smaller than 1 phase difference 2π. , V.C.
This shows that the change in the output frequency of O4 is saturated.

Next, in this phase-locked loop,
The operation when the input R is temporarily cut off will be explained. As estimated from FIG. 8, when the input R is disconnected in the phase relationship shown in FIG.

The output U becomes the GND potential. Similarly, when the input R is cut off in the phase relationship shown in FIG. 9, the output U becomes constant at a negative potential. Even in the former case, due to the imperfections of the actual elements, the output of the integrator 3 has a very large DC gain, so
Offset to one side.

The output frequency of the VCO 4 will be swung toward a frequency of 1, for example, f-. In the latter case, as a matter of course, the output frequency of the VCO 4 will be shifted toward the frequency f-.

When the input R recovers in such a state, the initial phase difference between the input R and the input V is generally not controlled, so the first
There is almost no possibility that the input/output characteristics shown in FIG. 1 fall into the linear part 5, and the pull-in operation is generally started from a state in which the output frequency of VC04 is saturated. In this pull-in operation, the phase difference between the input R and the input V changes at a speed corresponding to the frequency difference between the frequency of the input R pulse and the input V pulse created by dividing the output frequency of the VCO4. When the phase difference falls within ψ or ψ-, a lock-in operation is performed due to the so-called pull-in operation characteristic of the phase-locked loop.

Here, assuming that ψy or ψ- is almost O, the maximum time required for the retracting operation is as shown in the next column.

(Example) VCO4 center frequency f(, = 10
MHz Maximum frequency of VCO4 f+= 10.001
MflzVCO4 minimum frequency f = 9.99
9Mflz Pulse frequency of human power R = 500Hz Number of divisions of digital frequency divider 5 n = 20000 In this case, the pull-in operation time TL is given by the following equation.

Or, therefore, in the above example, TL=20 (seconds).

[Problem that the invention seeks to solve]

Since the conventional phase-locked oscillator circuit as described above is configured as described above, if the reference signal 1 is restored again after the reference signal 1 disappears due to a line disconnection, etc. There was a problem in that the retracting operation took a long time.

The present invention was made to solve this problem, and an object of the present invention is to provide a phase synchronized oscillation circuit that can significantly shorten the time required for re-pulling operation.

[Means for solving problems]

The phase synchronized oscillation circuit according to the present invention optimally sets the initial phase of the frequency divider according to the phase of the reference signal input when starting the application of the reference signal input.

The purpose is to minimize the initial phase difference between the reference signal input phase and the frequency divider output, thereby shortening the pull-in operation time.

[Effect]

In the phase-locked oscillator circuit of the present invention, the initial phase difference between the phase of the reference signal and the output of the frequency divider is minimized by controlling the detector that detects when the reference signal input is connected. Initialize the 1 frequency divider.

〔Example〕

FIG. 1 is a block diagram showing a phase-locked oscillator circuit according to an embodiment of the present invention, and reference numerals 1 to 6 are the same as those in the conventional example shown in FIG. 5 above. In the figure, 11 is a reference signal human power detector 1 to which reference signal human power 1 is applied;
13 is an aperture gate generator, 13 is an AND circuit, 14.
15 is the output of each detector 11 and aperture gate generator 12, and 16 is a refined reset pulse for initializing the digital frequency divider 5.

FIGS. 2 to 4 are diagrams showing the operation timing of each part in the phase-locked oscillation circuit of FIG. 1. FIG. 2 shows the operation timings of the output 14 of the reference signal human power 1# detector 11, the output 15 of the aperture gate generator 12, and the reset pulse 16. It is assumed that a in FIG. 2 is the first pulse of the reference signal human power 1 applied, and subsequent pulses b and below are input periodically.

The detector 11 is composed of a monostable multivibrator etc. that is repeatedly triggered by the rising edge of the reference signal 1, and the output 14 of the detector 11 is generated at the beginning of the reference signal 1 as shown in FIG. It turns on at the rising edge of the pulse. In response to the rising edge of the detector 110 output 14, the aperture gate generator 12 generates a short single gate pulse 15.
occurs. By applying this gate pulse 15 and the reference signal 1 to the AND circuit 13, a reset pulse 16 as shown in FIG. 2 is obtained as its output.

On the other hand, FIG. 3 shows the operation of the digital frequency divider 5. The digital frequency divider 5 can be considered as -9=, taking as an example a counter that counts up at the output frequency of the VCO 4, and the counter counts up to O (n-1) and returns to O again. It's repeating. The output 6 of the digital frequency divider 5, i.e. the input V
is created when the counter value changes to 1, for example, to 0.

FIG. 4 shows an explanation of the operation according to the present invention. Fourth
The reference signal 1 and reset pulse 16 shown in the figure are the second
It is the same as shown in the figure. The output 6 of the digital frequency divider 5 divides the output of the VCO 4 by n and runs by itself, but when the reference signal 1 is first applied, the counter value is initialized by the reset pulse 16. As a result, the phase of the output 6 with respect to the reference signal 1 is forcibly set to the distance T1 shown in FIG.

The value of this distance 111Tx is.

It goes without saying that it is desirable to make it correspond to a value smaller than 1ψ+1 or 1ψ" explained in FIG. 11 above. It is conceptually shown that below each distance Tt = Ts, the phase difference between the reference signal 1 and the output 6, that is, the input R and the input V becomes smaller due to the pull-in by the phase-locked loop.

In addition, in the above embodiment, the reset pulse 1 for initial setting
Although only one number 6 is considered, it goes without saying that applying two or more may be considered as a modification considering the stability of the circuit.

〔Effect of the invention〕

As explained above, the present invention is configured to set the initial pull-in phase so that the pull-in operation is performed quickly in the one-phase synchronized shooting circuit, and to ensure that frame synchronization, etc. is recovered extremely quickly after one line is disconnected. It has the excellent effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing a phase-locked oscillation circuit which is an embodiment of the present invention. FIGS. 2 to 4 are diagrams showing the operation timing of each part in the phase-locked oscillation circuit of FIG. 1. The figure is a block configuration diagram showing a conventional phase-locked oscillation circuit, and FIGS. 6 to 11 are circuit configuration diagrams of various parts in the conventional phase-locked oscillation circuit, and diagrams for explaining its operation. In the figure, l... reference signal input, 2... phase detector, 3... integrator, 4... voltage controlled oscillator (VCO).
). 5... Digital frequency divider, 6... Output of digital frequency divider 5, 11... Detector, 12... A/NIL-
CHA gate generator, 13... is an AND circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a phase synchronized oscillation circuit that divides the output frequency of a voltage controlled oscillator by n (integer) and synchronizes the phase of the divided output signal with another synchronous reference signal input applied from the outside, the reference signal input is disconnected. A detector is provided that detects that the reference signal input is in the connected state when the state changes from the state to the connected state, and the detector uses the reference signal input to control the frequency divider. The initial phase of is set such that the initial phase difference between the phase of the reference signal input and the output of the frequency divider is minimal, so that the output of the frequency divider is phase-synchronized with the reference signal input. A phase synchronized oscillator circuit characterized by shortening the required synchronization pull-in time.