JPS63187354U - - Google Patents
Info
- Publication number
- JPS63187354U JPS63187354U JP7815087U JP7815087U JPS63187354U JP S63187354 U JPS63187354 U JP S63187354U JP 7815087 U JP7815087 U JP 7815087U JP 7815087 U JP7815087 U JP 7815087U JP S63187354 U JPS63187354 U JP S63187354U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- chip package
- package
- pins
- terminal pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の実施例を示す図、第２図は本
考案の実施例の製造工程を示す図、第３図及び第
４図は本考案の他の実施例を示す図、第５図は従
来のマルチチツプパツケージの端子構造を示す図
である。
第１図、第２図、第３図、第４図において、１
０はチツプ、１１はパツケージ、１２は端子ピン
、１３は絶縁基板、１４は端子ブロツク、１５は
スルーホール、１６はパツド、１７は半田、１８
はくびれ部、１９は半田バンプ接合部である。
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the manufacturing process of the embodiment of the present invention, FIGS. 3 and 4 are diagrams showing other embodiments of the present invention, and FIG. The figure shows the terminal structure of a conventional multi-chip package. In Figures 1, 2, 3, and 4, 1
0 is a chip, 11 is a package, 12 is a terminal pin, 13 is an insulating board, 14 is a terminal block, 15 is a through hole, 16 is a pad, 17 is solder, 18
19 is a solder bump joint.
Claims (1)
ジの端子構造において、 端子ピン１２群を複数の区画に分け、各区画毎
に絶縁体の基板１３に前記端子ピン１２を植設し
て端子ブロツク１４となし、該端子ブロツク１４
を前記パツケージ１１の所定位置にそれぞれ接合
したことを特徴としたマルチチツプパツケージの
端子構造。[Claims for Utility Model Registration] In the terminal structure of a multi-chip package having a large number of terminal pins, a group of terminal pins 12 is divided into a plurality of sections, and the terminal pins 12 are implanted in an insulating substrate 13 for each section. and a terminal block 14, the terminal block 14
A terminal structure for a multi-chip package, characterized in that the chips are respectively bonded to predetermined positions of the package 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7815087U JPS63187354U (en) | 1987-05-26 | 1987-05-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7815087U JPS63187354U (en) | 1987-05-26 | 1987-05-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63187354U true JPS63187354U (en) | 1988-11-30 |
Family
ID=30926827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7815087U Pending JPS63187354U (en) | 1987-05-26 | 1987-05-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63187354U (en) |
-
1987
- 1987-05-26 JP JP7815087U patent/JPS63187354U/ja active Pending
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