JPH0265340U - - Google Patents
Info
- Publication number
- JPH0265340U JPH0265340U JP14503388U JP14503388U JPH0265340U JP H0265340 U JPH0265340 U JP H0265340U JP 14503388 U JP14503388 U JP 14503388U JP 14503388 U JP14503388 U JP 14503388U JP H0265340 U JPH0265340 U JP H0265340U
- Authority
- JP
- Japan
- Prior art keywords
- header
- semiconductor chip
- electrode pads
- power supply
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
第１図および第２図は本考案に依る半導体装置
を説明する上面図および断面図、第３図および第
４図は従来の半導体装置を説明する上面図および
断面図である。
1 and 2 are a top view and a sectional view illustrating a semiconductor device according to the present invention, and FIGS. 3 and 4 are a top view and a sectional view illustrating a conventional semiconductor device.
Claims (1)
前記半導体チツプを載置するヘツダーと前記ヘツ
ダーに隣接し且つ前記電極パツドとボンデイング
ワイヤにより接続された複数のリードとを有する
半導体装置において、前記ヘツダーを２分割し、
前記ヘツダー上に設けた絶縁層を介して前記半導
体チツプを載置し、前記半導体チツプ上の異なる
電源端子となる前記電極パツドと前記夫々のヘツ
ダーとをボンデイングワイヤで接続して電源配線
と兼用することを特徴とした半導体装置。 (2) 前記半導体チツプとしてダイナミツクラン
ダムアクセスメモリを用い、前記半導体チツプ上
の両側に異なる種類の同一の電源端子の前記電極
パツドを設け、前記同一の電源端子の電極パツド
をボンデイングワイヤにより夫々の近くの２分割
した前記ヘツダーに接続することを特徴とした請
求項１記載の半導体装置。[Claims for Utility Model Registration] (1) A semiconductor chip having a plurality of electrode pads, a header on which the semiconductor chip is placed, and a plurality of leads adjacent to the header and connected to the electrode pads by bonding wires. In the semiconductor device comprising: dividing the header into two,
The semiconductor chip is placed on the header through an insulating layer provided on the header, and the electrode pads serving as different power supply terminals on the semiconductor chip are connected to each of the headers using bonding wires to serve also as power supply wiring. A semiconductor device characterized by: (2) A dynamic random access memory is used as the semiconductor chip, the electrode pads of different types of the same power supply terminal are provided on both sides of the semiconductor chip, and the electrode pads of the same power supply terminal are connected to each other by bonding wires. 2. The semiconductor device according to claim 1, wherein said semiconductor device is connected to said header divided into two parts nearby.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14503388U JPH0265340U (en) | 1988-11-07 | 1988-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14503388U JPH0265340U (en) | 1988-11-07 | 1988-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0265340U true JPH0265340U (en) | 1990-05-16 |
Family
ID=31413267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14503388U Pending JPH0265340U (en) | 1988-11-07 | 1988-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0265340U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62283635A (en) * | 1986-05-31 | 1987-12-09 | Toshiba Corp | Semiconductor device |
-
1988
- 1988-11-07 JP JP14503388U patent/JPH0265340U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62283635A (en) * | 1986-05-31 | 1987-12-09 | Toshiba Corp | Semiconductor device |
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