JPS63185253U

JPS63185253U -

Info

Publication number: JPS63185253U
Application number: JP7589587U
Authority: JP
Priority date: 1987-05-20
Filing date: 1987-05-20
Publication date: 1988-11-29

Description

[Brief explanation of the drawing]

第１図は本考案の半導体装置の概略平面図、第
２図は従来の半導体装置の概略平面図、第３図は
第１図のＡ―Ａ′線の断面図である。１は半導体チツプ、２，３，４，５，６，７は
パツド、８，９，１０，１１は第１乃至第４のＪ
・ＦＥＴ、２１は半導体基板、２２は埋込み領域
、２３は分離領域、２４はゲート領域、２５はド
レインコンタクト、２６はソースコンタクトであ
る。 FIG. 1 is a schematic plan view of a semiconductor device of the present invention, FIG. 2 is a schematic plan view of a conventional semiconductor device, and FIG. 3 is a cross-sectional view taken along line AA' in FIG. 1 is a semiconductor chip, 2, 3, 4, 5, 6, and 7 are pads, and 8, 9, 10, and 11 are the first to fourth J.
-FET, 21 is a semiconductor substrate, 22 is a buried region, 23 is an isolation region, 24 is a gate region, 25 is a drain contact, and 26 is a source contact.

Claims

[Scope of utility model registration request]

In a semiconductor device in which two field effect transistors are formed on one chip, first to fourth field effect transistors configured as the two field effect transistors are sequentially formed, and the first and third field effect transistors are formed in sequence. A semiconductor characterized in that the drain, gate, and source of the effect transistor are configured in one field effect transistor, and the drain, gate, and source of the second and fourth field effect transistors are configured in the other field effect transistor. Device.