JPS63184154A - Shared ram accessing system - Google Patents

Abstract

PURPOSE:To respond to the change of a storage position, by writing a data which specifies an area prohibited to write the data from a second processor on another RAM by a first processor after applying a power source, and deciding whether an address is a prohibited area or not at the time of accessing to the second processor. CONSTITUTION:When a shared RAM 14 is accessed by a first and a second processor units 11 and 12, an address decoder 15 is provided on the unit 11 side, and an address decoder RAM 16 on the unit 12 side, respectively. And in the unit 12, the data representing possible/impossible to be written is supplied on each address of the RAM 14, and after the power source being applied, the unit 11 writes the data on the RAM 16. Furthermore, when the unit 12 accesses to the RAM 14 in such state, the data possible/impossible to be written is read from the corresponding address of the RAM 16, and if the area is the prohibited area, no write of the data on the RAM 14 is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a shared RAM access method that can be commonly accessed by two processors.

<Prior Art> There is a system in which first and second processor units exchange data with each other via a commonly accessible shared RAM to perform predetermined processing.

FIG. 2 is a schematic block diagram of such a system, where 1 is a first
2 is a second processor unit, and 3 is a common unit. The common unit 3 includes a shared RAM 3a that can be accessed in common from the first and second processor units 1.2, a path arbiter 3b, and the like. In such a system, the processor unit that sends data writes the data and commands to be sent to the serial RAM 3a via the bus arbiter 3b,
The processor unit that receives the data is the Ci-Art RA.
It reads the data addressed to itself written in M3a and performs predetermined processing based on the data.

A specific example of such a system is a numerical control system, in which the first processor unit 1 corresponds to an NC device, 1', processor unit 2 is a PC device (blogeramable controller)
corresponds to

<Problems to be Solved by the Invention> By the way, among the data written by one of the processor units to the shared RAM 3a, certain data may not be destroyed. For example, in a numerical control system, certain data written in the shared RAM 3a by the NC device 1 should not be destroyed, and the system will malfunction if it is destroyed.

However, in numerical control systems, the program that controls the second processor unit, the PC device, is created by the user who is the machine manufacturer, so there is a problem with reliability, and it is difficult to destroy the program due to a program error. There may be cases where other data is written into an area where data is stored.

For this reason, an area in the shared RAM (area from address A1 to An in FIG. 3) that stores data that should not be destroyed is determined in advance, and the second processor unit, PC@O, stores the data in the shared RAM3.
A conceivable configuration is to check whether the data write address exists in the data write prohibited areas A1 to An when writing to A, and to write data only if the data write address does not exist.

However, in such a method, a data writing prohibited area is fixedly determined. For this reason, a problem arises in that it is impossible to deal with the case where the program for controlling the NC device is revised and the storage area in the shared RAM of data that should not be destroyed is changed as a result of the revision.

In light of the above, an object of the present invention is to provide a shared RAM access method that can reliably protect data that should not be destroyed, and that can cope with changes in the storage location of the data in the shared RAM due to program revisions, etc. It is.

Means to solve problems〉 FIG. 1 is a block diagram of an embodiment of the present invention.

11 is a first processor unit, 12 is a second processor unit, 13 is a bus arbiter, 14 is a shared RAM, and 16 is a RAM for an address decoder on the second processor side.

Effect> After the power is turned on, the first processor 11 writes into the address decoder RAM 16 data that specifies the area of the shared RAM 14 where data writing is prohibited by the second processor 12.

Note that the data specifying this write-inhibited area is data indicating whether data can be written to each address of the shared RAM 14.

In this state, the second processor 12 uses the shared RAM
When accessing 1a for data writing, the writable/unwritable data ("1"/NO") is read from the address of the address decoder RAM 16 corresponding to the data write address of the shared RAM, and based on the applicable/unwritable data. It is determined whether the area is a data write prohibited area, and if the area is a data write prohibited area, no data is written to the shared RAM, and if the area is not a write prohibited area, data writing is permitted.

<Example> FIG. 1 is a block diagram of an embodiment of the present invention.

11 is a first processor unit, 12 is a second processor unit, 13 is a bus arbiter that manages bus control,
14 is a shared RAM that can be commonly accessed by the first and second processor units.

15 is an address decoder on the first processor side, 16 is a RAM for the address decoder on the second processor side, 17 is a multiplexer, 18 is a read/write control unit (R/W control unit), 19.20 is a pass buffer, and 21 is a pass buffer. latch circuit, 2
2.24 is Antogame), 23 is Orgate. Further, the bus line connected to the terminal of alphabet A is an address bus, the bus line connected to the terminal of alphabet D is a data bus, and the bus line connected to the terminal of alphabet C is a control bus. In addition, the storage RAM
14 and the C8 terminal in the address decoder RAM 16 are chip select terminals, and each R
Access to AM becomes possible.

The control program stored in the built-in memory of the first processor unit 11 is stored in the address decoder RAM 16 every time the system is powered on.
It is configured to write data for specifying the M14 area (write-protected area). Note that the data specifying this write-protected area is stored in the shared RAM 14.
This is data ("1"/'0') indicating whether data can be written for each address.

When storing write-protected area data immediately after power is turned on, the multiplexer 17 transfers the address and control signals from the first processor 22 to the address decoder RA.
Input the write-protected area data to M16 and write it to RAM16.
After the address is stored in the address decoder RAM 16, the address from the second processor unit 12 and the control chair number (read signal) from the R/W control section 18 are input to the address decoder RAM 16.

When the second processor unit 12 reads data from the shared RAM 14, the R/W control unit 18 outputs a high level chip select signal C8R, and sets the chip select signal C82, which is the output of the OR gate 23, to a high level. This makes it possible to access the shared RAM 14 under the control of the bus arbiter 13, and when the second processor unit 12 writes data to the shared RAM 14 (read signal R is used as a control signal).
D and a high-level chip select signal C3B are output to enable data reading from the address decoder RAM 16.

The address decoder 15 decodes the address output from the first processor unit 11, and if the address is an address of the shared RAM 14, outputs a high-level chip select signal C81, and under the control of the bus arbiter 13, the address decodes the shared RAM 14. be accessible.

If there is an access request from one processor unit while neither the first nor second processor unit is accessing the shared RAM 14, the bus arbiter 13 transmits the access request to the shared RAM 14.
If one of the first and second processor units accesses the shared RAM 14 and there is an access request from the other processor unit, the shared RAM 14 is accessed by the other processor unit.
AM14 is not allowed to access and is placed on standby.

The overall operation of FIG. 1 will be explained below.

(When the power of the Al writable/unwritable data storage system is turned on, the first processor unit 11 accesses the address decoder RAM 16 under the control of the control program, and the second processor 12 accesses it when writing data. In other words, the first processor unit 11 writes data indicating whether data can be written (a predetermined bit is "1") for each address of the shared RAM 14 based on the control program. ″/″0
゛°) and R for the address decoder corresponding to the address.
Outputs the address in AM16 and write (No. 8) to each path line.

The address decoder 15 decodes the address appearing on the address bus, and the address decoder 15 decodes the address appearing on the address bus.
Since this address indicates the storage area of M16, a high level chip select signal C3A is output.

On the other hand, since the latch circuit 21 is initialized so that its output (switching signal ASW) is at a high level when the power is turned on, the multiplexer 17 receives each data from the bus line connected to the first processor unit 11. Chip select signal C3A is sent to address decoder RAM16
Enter.

As a result, a high-level chip select signal css' is input to the chip select terminal C8, the address decoder RAM 16 becomes accessible, and a predetermined bit position appearing on the data bus is placed in the storage area indicated by the address on the address bus. 1″ or 0″ (writable/
data) is stored.

Thereafter, similarly, writable/unwritable data is stored in each address of the address decoder RAM 16 corresponding to all addresses in the shared RAM 14.

Once the storage process of writable/unwritable data is completed, the first
The processor unit 11 outputs the address of the latch circuit 21, a write signal, and data for inverting the state of the latch circuit to each bus. Address decoder 15 outputs a high level signal to line 41 to indicate that the address of latch circuit 15 appears on the address bus. This result and gate 22
The output becomes high level, the state of the latch circuit 21 is inverted, and the switching signal ASW becomes low level "0". From now on, the remultiplexer 17 receives the address signal from the second processor unit 12 and the R/W control. The read signal RD and chip select signal C3B from the section 18 are input to the address decoder RAM 16.

(B) Read from the second processor unit When the second processor unit 12 reads data from the shared RAM 14, the second processor unit outputs the address of the shared RAM 14 to the address bus and a read signal to the control bus. do.

R/W? ! The IJ control section 18 outputs a high level chip select signal C3R when a read signal appears on the control bus. As a result of B, the chip select signal C32 which is the output of the OR gate 23 is at a high level, and the bus arbit 13! It is identified that there is an access request from the second processor unit. Furthermore, the R/W control section 18
always inputs the read signal RD to the multiplexer 17 as a control signal.

If the first processor unit 11 is not accessing the shared RAM 14, the bus architecture 13 sets the chip access signal C5S to high level in response to an access request from the second processor unit 12, and also outputs the address signal from the second processor unit 12. and a read signal are input to the storage RAM 14. As a result, data is read from the storage area of the shared RAM 14 specified by the address, and is taken into the second processor unit 12 via the bus buffer 20.

Note that when a data read access request is generated from the second processor unit 12 (chip select signal C32=
When the first processor unit 11 is accessing the storage RAM 14 (when it is "1"), the access request from the second processor unit 12 is awaited.

(C) Write processing of the second processor unit When the second processor unit 12 writes data to the shared RAM 14, the second processor unit 12 writes the address of the shared RAM 14 to the address bus and writes the data to the data bus. , outputs a write signal to the control bus.

The R/W control unit 18 outputs a high level chip select No. 43 C3B to indicate that a write signal appears on the control bus. Note that when the write signal is generated, the chip select signal C3R is at a low level. Further, the R/W control section 18 constantly inputs the read signal RD to the multiplexer 17 as a control signal.

The multiplexer 17 operates except when writing enabled/disabled data (when switching signal C3A="OI+")
, an address signal from the second processor unit 12,
R/W [Since the read signal RD from the controller 18 and the chip select signal C3B are input to the address decoder RAM 16, when the chip select signal C3B becomes high level, the address decoder RA specified by the address signal
Writable/unwritable data is output from the storage area of M16 via the DO terminal. High level if writable (
1''), if it is not possible, low level (0'') data is stored, so if writing is possible, the chip select signal C8W, which is the Do terminal output, becomes high level and the output of the AND gate 24 becomes high level. Nari, or gate 2
A high level chip select signal C32 is input to the bus arbiter 13 via the bus arbiter 13.

If the first processor unit 11 is not accessing the shared RAM 14, the bus arbiter 13 sets the chip access signal C8S to high level in response to an access request from the second processor unit 12, and also outputs the address from the second processor unit 12. The signal and write signal are input to the shared RAM 14. As a result, data from the second processor unit 12 is written via the path buffer 20 to the storage area of the shared RAM 14 designated by the address signal.

Note that when a data write access request is generated from the second processor unit 12 (chip select signal C32=
If the first processor unit 11 is accessing the shared RAM 14 ("1"), the access request from the second processor unit 12 is awaited.

On the other hand, if writing is not possible, the chip select signal C8W output from the DO terminal becomes low level, the output of the AND gate 24 becomes low level, and the chip select signal C82 output from the OR gate 23 also becomes low level.

As a result, no access request from the second processor unit 12 is input to the bus arbiter 13, and therefore the shared RAM 14 does not store data from the second processor unit 12. In other words, even if the address of the write-inhibited area is incorrectly commanded from the second processor unit 12 at the time of data writing, data writing is not performed.

<Effects of the Invention> According to the present invention, after the power is turned on, the first processor writes data to the RAM that specifies the area of the shared RAM where data writing is prohibited by the second processor, and the second processor When accessing the shared RAM to write data, it is determined whether the data write address is in the data write-inhibited area, and if it is in the data write-inhibited area, the data is not written. By using this as a storage area for data that should not be destroyed by two processor units, data can be reliably protected.

Moreover, even if the storage location of data that is corrupted or problematic in the shared RAM is changed due to a revision of the control program, etc., the revised control program will set the storage location as a write-protected area after the system power is turned on.
Since it is configured to write to M, it is possible to prevent data from being destroyed even if there is a revision, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams of conventional gripping points. 11...First processor unit, 12...Second processor unit, 13...Bus arbiter, 14...Shared RAM. 15. Address decoder on the first processor side, 16.
・RAM for address decoder. 17...Multiplexer,

Claims (2)

[Claims] (1) In a shared RAM access method that can be commonly accessed by the first and second processors, after power is turned on, the first processor identifies an area of the shared RAM where data writing is prohibited by the second processor. When the second processor accesses the shared RAM to write data, it determines whether the data write address is in the data write prohibited area, and if it is the data write prohibited area, writes the data. A shared RAM access method characterized by: (2) The data specifying the write-prohibited area stored in the RAM indicates whether data can be written to each address of the shared RAM. RAM access method.