JPS63182838A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63182838A JPS63182838A JP1542787A JP1542787A JPS63182838A JP S63182838 A JPS63182838 A JP S63182838A JP 1542787 A JP1542787 A JP 1542787A JP 1542787 A JP1542787 A JP 1542787A JP S63182838 A JPS63182838 A JP S63182838A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- manufacturing
- layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 238000010030 laminating Methods 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- -1 polycide Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 abstract description 12
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000002844 melting Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、多層配線を有する半導体装置において、多
層配線間の接続方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for connecting multilayer interconnections in a semiconductor device having multilayer interconnections.
この発明は、２層以上の多層配線を有する半導体装置に
おいて、これらの配線間の接続方法に関するもので、下
層の配線を形成した後に、層間絶縁膜と上層の配線を順
次積層する０次に、下層配線と上層配線との接続（コン
タクト）部分の上層配線と層間絶縁膜を順次エツチング
除去し、コンタクト部分の下層配線を露出させる。さら
に、導電体膜を積層し、コンタクト部分において下層配
線と上層配線を接続する。The present invention relates to a method for connecting interconnects in a semiconductor device having two or more layers of multi-layer interconnects, in which after forming a lower layer interconnect, an interlayer insulating film and an upper layer interconnect are sequentially laminated. The upper layer wiring and the interlayer insulating film at the connection (contact) portion between the lower layer wiring and the upper layer wiring are sequentially removed by etching to expose the lower layer wiring at the contact portion. Further, a conductive film is laminated, and the lower layer wiring and the upper layer wiring are connected at the contact portion.
（従来の技術〕
たとえば、Ａｌ２層配線を有する半導体装置第５図にお
いて、第１層目のＡｌ配線１１を形成した後層間絶縁膜
１４を積層し、所望の部分に接続（コンタクト）孔１２
を形成し、第１層目のＡｌ配線の１部を露出させる。(Prior Art) For example, in the semiconductor device shown in FIG. 5 having two Al wiring layers, after forming the first layer Al wiring 11, an interlayer insulating film 14 is laminated, and connection (contact) holes 12 are formed in desired portions.
A portion of the first layer Al wiring is exposed.
次に、第２層目のＡｌ配線１５をスパッター法に゛より
積層し、所望の第２層配線１５をパターニングする。こ
の時、第２層目のＡｌ配線１５を形成するスパッター法
は、被覆性（ステップ・カバレンジ）が良くないために
、第５図のａのコンタクト上部のエツジ部分や第５図の
ｂのコンタクト下部の部分にくびれや断切れが生じる事
があった。特に近年、ＩＣの微細化が進み、コンタクト
孔の大きさが２．０ ミクロン以下になるとコンタクト
孔へのＡｌの積層はさらに悪くなり、被覆率も低下する
。Next, a second layer of Al wiring 15 is laminated by a sputtering method, and a desired second layer wiring 15 is patterned. At this time, since the sputtering method for forming the second layer Al wiring 15 has poor coverage (step coverage), Constrictions or cuts may occur in the lower part. Particularly in recent years, as ICs have become smaller and the size of contact holes has become smaller than 2.0 microns, the lamination of Al in the contact holes becomes even worse and the coverage rate decreases.
Ａｆｆｉ２１配線を有する半導体装置において、第１１
Ｊ目と第２層目の接続孔では、第２層目のＡｎの被覆率
が悪い為、断切れや極度のくびれにより配線間のコンタ
クト不良が発生するという問題があった。又、コンタク
ト部では深い溝ができるため、その上に形成される絶縁
膜にも溝が投影され、さらにその上に形成されも配線層
の断切れを発生するという問題があった。In a semiconductor device having Affi21 wiring, the 11th
In the connection hole of the J-th layer and the second layer, since the coverage of the second layer of An is poor, there is a problem that a contact failure between wirings occurs due to breakage or extreme constriction. Further, since a deep groove is formed in the contact portion, the groove is also projected onto the insulating film formed thereon, and even if formed thereon, there is a problem in that the wiring layer is cut off.
上記問題点を解決するためにこの発明は、第２層目のＡ
ｌ配線を形成した後に、コンタクト孔を形成し、第１層
目のＡｌ配線と第２層目のＡｌ配線の接続を行う為に、
被覆性の良好な例えば化学気相成長法を用いて導電体膜
を形成する。In order to solve the above problems, the present invention provides a second layer of A
After forming the l wiring, contact holes are formed and in order to connect the first layer Al wiring and the second layer Al wiring,
The conductor film is formed using, for example, a chemical vapor deposition method that provides good coverage.
第１１Ａ＆配線と第２１１ｉ、Ａｌ配線との接続は被覆
性の良好な導電体膜で形成するので、コンタクト孔での
くびれや断線もなくなる。又、導電体膜を厚く積層する
事によりコンタクト孔を完全に充填できるので、第３層
目のＡｌ配線のくびれや断線もな（す事ができる。Since the connection between the 11th A& wiring and the 211i, Al wiring is formed with a conductive film with good coverage, there is no constriction or disconnection at the contact hole. Furthermore, by stacking the conductor film thickly, the contact hole can be completely filled, so that constrictions and disconnections in the third layer Al wiring can be avoided.
以下にこの発明の実施例を図面に基づいて詳細に説明す
る。第１図は本発明の半導体装置の製造方法の工程順を
示す断面図である。第１図（ａ）において、半導体素子
の上に第１の配！！３を積層し所望の形状にパターニン
グする。この第１の配線３は導電体膜であり、例えば、
Ａｌ．Ａｌ−３ｉ。Embodiments of the present invention will be described in detail below based on the drawings. FIG. 1 is a cross-sectional view showing the order of steps in the method for manufacturing a semiconductor device according to the present invention. In FIG. 1(a), a first arrangement is placed on a semiconductor element! ! 3 are stacked and patterned into a desired shape. This first wiring 3 is a conductive film, for example,
Al. Al-3i.
ＡＪ−３ｉ−Ｔｉ、Ａｊｌ−３ｉ −Ｃｕ等のＡｌを主
成分とするＡｌ系配線や、多結晶シリコン膜あるいはポ
リサイド膜（ＰｏｌｙＳｉとシリサイドの２層膜あるい
はＰｏ１ｙＳｉと金属との２層膜）あるいは、Ｗｓｉｘ
、Ｍｏ５ｉｘ４ｉｓｉｘ等のシリサイド膜、あるいはＷ
やＭｏ、Ｔｉ等の高融点金属等である０次に第１開山）
に示す様に配線相互間を絶縁する層間絶縁膜４を積層す
る。この眉間ｍ縁１ｌｉ４は、例えばシリコン酸化膜、
シリコン窒化膜、シリコンオキシナイトライド膜、アル
ミナ膜、ポリイミド等の有機絶縁膜、 Ｓ ＯＧ （Ｓ
ｐｉｎ Ｏｎ Ｇｌａｓｓ）等の無機塗布膜等であ
る０次に第１図（Ｃ）に示す様に、第２の配＆１１５を
積層する。この第２の配ｗＡ５は導電体膜であり、例え
ば、Ａｊｌ、 Ａｊｌ−３１，Ａｌｔ−３Ｌ −Ｔｉ、
ＡＪ−３Ｌ−Ｃｕ等のＡｔを主成分とするＡｌ系配線や
、多結晶シリコン膜、あるいは−ｓｉｘ。Al-based wiring mainly composed of Al such as AJ-3i-Ti and Ajl-3i-Cu, polycrystalline silicon film or polycide film (two-layer film of PolySi and silicide or two-layer film of Po1ySi and metal), or , Wsix
, silicide film such as Mo5ix4isix, or W
0-order first opening, which is high-melting point metals such as Mo, Ti, etc.)
As shown in the figure, an interlayer insulating film 4 is laminated to insulate the interconnects from each other. This glabella m edge 1li4 is made of, for example, a silicon oxide film,
Silicon nitride film, silicon oxynitride film, alumina film, organic insulating film such as polyimide, SOG (S
As shown in FIG. 1(C), a second layer 115, which is an inorganic coating film such as pin on glass (pin on glass), is laminated. This second wiring wA5 is a conductive film, for example, Ajl, Ajl-31, Alt-3L-Ti,
Al-based wiring mainly composed of At such as AJ-3L-Cu, polycrystalline silicon film, or -six.
Ｍｏ５ｉｘ、Ｔｉ５ｉｘ等のシリサイド膜、あるいはポ
リサイド膜、あるいはＷやＭｏ、Ｔｉ等の高融点金属等
である０次に第１図（ｄｌに示す様に、例えばレジスト
ロを塗布パターニングして、第１の配線３と第２の配線
５との接続孔６の窓明けを行い、第２の配線と層間絶縁
膜４とを順次エツチング除去し、第１の配線３の１部を
露出させる。As shown in FIG. A connection hole 6 between the wiring 3 and the second wiring 5 is opened, and the second wiring and the interlayer insulating film 4 are sequentially etched away to expose a portion of the first wiring 3.
この時のパターニング方法にはレジストを用いたフォト
リン法を応用したが、勿論他の方法でも良い０例えば、
直接エツチング法でも可能である。The patterning method used at this time was a photorin method using a resist, but other methods may of course be used.For example,
A direct etching method is also possible.
次にレジスト６を除去する。勿論この後に第１の配線３
の１部を露出させてもよい０次に第１図（ｅｌに示す様
に、導電体膜８を積層する。この時、当然、第２の配線
５の上ばかりではなく、接続孔７にも導電体膜８は入り
込み第１の配線３の露出した部分の上にも積層し、接続
孔７において、第１の配線３と第２の配線５とが導電体
膜８を通して接続する。この導電体膜は、例えば、Ａｌ
、Ａｌ−３ｉ、Ａｌ−３ｉ−Ｔｔ、ＡＡ−３ｉ−Ｃｕ等
のＡｌｌを主成分とするＡｌ系の材料や、多結晶シリコ
ン膜、アモルファスシリコン膜、あるいはポリサイド膜
、あるいはＷやＭｏ、Ｔｉ等の高融点金属や、Ｐｂ、Ｓ
ｎ、ハンダ等の低融点金属や、Ｗｓｉｘ、Ｍｏ５ｉｘ、
Ｔｉ５ｉｘ等のシリサイド膜等がある。半導体素子が微
細化すると、接続孔のサイズも小さくなる。接続孔が垂
直に近いステップの時には、２ミクロン以下の小さな接
続孔に導電体膜８を入れ込む為に、段差被覆性の良好な
、例えば化学気相成長法にて導電体膜を積層する事も良
い方法である。又、通常はスパック−法で導電体膜を積
層するが、より被覆性の良好なバイアススパンター法を
用いても良い、ところで、第２図に示す様に、接続孔を
あける時に接続孔７′にテーパー（傾斜）をつける事に
より、接続孔における導電体膜８′の埋め込みも良好に
なり、接続孔での段切れも解消される。さて、次にフォ
トリングラフィ等の方法を用いて、第１図（８１の導電
体膜８及び第、２の配線５の所望の部分を選択的にエツ
チング除去し、配線のパターニングを行う、第２の配線
５の上に導電体膜８を残したくない時や配線全体を薄く
したい時は、例えば、反応性イオンエツチング（ＲＩＢ
）等の異方性エツチングを用いて導電体ＰＩＪ、８をエ
ツチングし、第３図に示す様に接続孔７″の側壁に導電
体１！１８’を残す方法でも、第１の配線３′と第２の
配線５″との接続が可能である。Next, the resist 6 is removed. Of course, after this, the first wiring 3
As shown in FIG. The conductive film 8 also penetrates and is laminated on the exposed portion of the first wiring 3, and the first wiring 3 and the second wiring 5 are connected through the conductive film 8 in the connection hole 7. The conductor film is made of, for example, Al
, Al-based materials mainly composed of Al such as Al-3i, Al-3i-Tt, and AA-3i-Cu, polycrystalline silicon films, amorphous silicon films, polycide films, or W, Mo, Ti, etc. high melting point metals, Pb, S
n, low melting point metals such as solder, Wsix, Mo5ix,
There are silicide films such as Ti5ix. As semiconductor elements become smaller, the size of contact holes also becomes smaller. When the step of the contact hole is close to vertical, in order to insert the conductive film 8 into the small contact hole of 2 microns or less, a conductive film with good step coverage, for example, is laminated by chemical vapor deposition. is also a good method. In addition, the conductive film is usually laminated by the spackle method, but the bias spunter method, which provides better coverage, may also be used.By the way, as shown in FIG. By providing a taper (slant) to ', the conductor film 8' can be well embedded in the connection hole, and step breakage in the connection hole can be eliminated. Next, using a method such as photolithography, the desired portions of the conductive film 8 and the second wiring 5 shown in FIG. When you do not want to leave the conductor film 8 on the wiring 5 of No. 2 or when you want to make the entire wiring thin, for example, reactive ion etching (RIB) is used.
) etc. to etch the conductor PIJ, 8 and leave the conductor 1!18' on the side wall of the connection hole 7'' as shown in FIG. connection with the second wiring 5'' is possible.
又、被覆性の良い方法で導電体膜８を積層する事により
、第１図ｔｅｌに示す様に、接続孔７を完全に埋め込む
事ができ、配線層の表面を平坦にできる。Furthermore, by laminating the conductive film 8 in a manner that provides good coverage, the contact hole 7 can be completely filled, as shown in FIG. 1, and the surface of the wiring layer can be made flat.
仮に完全に埋め込む事ができなくとも、導電体膜８の上
に平坦化用の例えばレジストやポリイミドを塗布し、エ
ッチバックを行う事により、配線層を平坦にできる。第
４図に示す様に、エッチバック方法を使用する事により
、接続孔を完全に埋め、配線層も平坦化できる。Even if it cannot be completely buried, the wiring layer can be made flat by applying a flattening resist or polyimide, for example, on the conductor film 8 and performing etch back. As shown in FIG. 4, by using the etch-back method, the connection hole can be completely filled and the wiring layer can be flattened.
この様に平坦化する事により、本発明を用いて配線を何
層でも積層可能である。By flattening in this manner, it is possible to stack any number of wiring layers using the present invention.
この発明は以上説明した様に、上層配線を積層した後に
接続孔をあけ、第１の配線と第２の配線との接続を行う
為に導電体膜を積層する事により、接続孔での段切れの
ない、良好なコンタクトを得る事ができる。又、配線の
平坦化も容易に行う事が可能なため、多層配線プロセス
にも適用できる。As explained above, in this invention, a connection hole is formed after laminating the upper layer wiring, and a conductive film is laminated to connect the first wiring and the second wiring, thereby forming a step in the connection hole. You can get good, unbroken contact. Furthermore, since wiring can be easily flattened, it can also be applied to multilayer wiring processes.
第１図（ａｌ〜＋ｉ１１は本発明の半導体装置の製造方
法の工程順を示す断面図、第２図、第３図、第４図は本
発明の実施例を示す断面図、第５図は従来の半導体装置
の製造方法を示す断面図である。
以上FIG. 1 (al to +i11 is a cross-sectional view showing the process order of the semiconductor device manufacturing method of the present invention, FIG. 2, FIG. 3, and FIG. 4 are cross-sectional views showing an embodiment of the present invention. FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
Claims (8)
法において、第１の配線を形成する工程と前記第１の配
線層の上に第１の層間絶縁膜を形成する工程と、前記第
１の層間絶縁膜の上に第２の配線を形成する工程と、前
記第１の配線と前記第２の配線とを接続する領域におけ
る前記第２の配線と前記第１の層間絶縁膜とを順次エッ
チング除去し第１の配線を露出する工程と、第１の配線
が露出した接続孔の部分に第１の導電層を積層する工程
とを含む事を特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device having a multilayer interconnection of two or more layers, including the steps of forming a first interconnection layer, forming a first interlayer insulating film on the first interconnection layer, and forming a first interconnection layer on the first interconnection layer. a step of forming a second wiring on a first interlayer insulating film; and a step of forming a second wiring on a first interlayer insulating film, and forming a second wiring and a first interlayer insulating film in a region connecting the first wiring and the second wiring. A method for manufacturing a semiconductor device, comprising the steps of sequentially etching and removing the first wiring to expose the first wiring, and laminating a first conductive layer in the connection hole where the first wiring is exposed.
Ａｌ系の材料である事を特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。(2) Claim 1, characterized in that the first wiring and the second wiring are made of an Al-based material containing Al as a main component.
A method for manufacturing a semiconductor device according to section 1.
り、第２の配線は多結晶シリコン又はポリサイドである
事を特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the first wiring is made of polycrystalline silicon or polycide, and the second wiring is made of polycrystalline silicon or polycide.
り、第２の配線はＡｌを主成分としたＡｌ系の材料であ
る事を特徴とする特許請求の範囲第１項記載の半導体装
置の製造方法。(4) The semiconductor device according to claim 1, wherein the first wiring is made of polycrystalline silicon or polycide, and the second wiring is made of an Al-based material containing Al as a main component. Production method.
はシリサイド又は金属である事を特徴とする特許請求の
範囲第１項記載の半導体装置の製造方法。(5) The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is made of polycrystalline silicon, polycide, silicide, or metal.
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(6) The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is formed using a chemical vapor deposition method.
いて、第１の導電層を厚く積層し、接続孔を完全に穴埋
めする事を特徴とする特許請求の範囲第１項記載の半導
体装置の製造方法。(7) Claim 1, characterized in that in the connection hole connecting the first wiring and the second wiring, the first conductive layer is laminated thickly to completely fill the connection hole. A method for manufacturing a semiconductor device.
し、次にエッチバック法を用いて配線を平坦にする事を
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(8) The semiconductor device according to claim 1, characterized in that the first conductive layer is laminated thickly to completely fill the contact hole, and then the wiring is made flat by using an etch-back method. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1542787A JPS63182838A (en) | 1987-01-26 | 1987-01-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1542787A JPS63182838A (en) | 1987-01-26 | 1987-01-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63182838A true JPS63182838A (en) | 1988-07-28 |
Family
ID=11888479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1542787A Pending JPS63182838A (en) | 1987-01-26 | 1987-01-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63182838A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH045824A (en) * | 1990-04-23 | 1992-01-09 | Toshiba Corp | Semiconductor device and its manufacture |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419382A (en) * | 1977-07-14 | 1979-02-14 | Nec Corp | Semiconductor device |
| JPS5658247A (en) * | 1979-10-17 | 1981-05-21 | Fujitsu Ltd | Production of semiconductor device |
| JPS57145340A (en) * | 1981-03-05 | 1982-09-08 | Toshiba Corp | Manufacture of semiconductor device |
| JPS60200541A (en) * | 1984-03-26 | 1985-10-11 | Agency Of Ind Science & Technol | Semiconductor device |
-
1987
- 1987-01-26 JP JP1542787A patent/JPS63182838A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5419382A (en) * | 1977-07-14 | 1979-02-14 | Nec Corp | Semiconductor device |
| JPS5658247A (en) * | 1979-10-17 | 1981-05-21 | Fujitsu Ltd | Production of semiconductor device |
| JPS57145340A (en) * | 1981-03-05 | 1982-09-08 | Toshiba Corp | Manufacture of semiconductor device |
| JPS60200541A (en) * | 1984-03-26 | 1985-10-11 | Agency Of Ind Science & Technol | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH045824A (en) * | 1990-04-23 | 1992-01-09 | Toshiba Corp | Semiconductor device and its manufacture |
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