JPS6318223B2 - - Google Patents

Info

Publication number
JPS6318223B2
JPS6318223B2 JP58116712A JP11671283A JPS6318223B2 JP S6318223 B2 JPS6318223 B2 JP S6318223B2 JP 58116712 A JP58116712 A JP 58116712A JP 11671283 A JP11671283 A JP 11671283A JP S6318223 B2 JPS6318223 B2 JP S6318223B2
Authority
JP
Japan
Prior art keywords
data
error
circuit
clock signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58116712A
Other languages
English (en)
Japanese (ja)
Other versions
JPS607542A (ja
Inventor
Hisashi Inoshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58116712A priority Critical patent/JPS607542A/ja
Publication of JPS607542A publication Critical patent/JPS607542A/ja
Publication of JPS6318223B2 publication Critical patent/JPS6318223B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
JP58116712A 1983-06-27 1983-06-27 エラ−処理回路 Granted JPS607542A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58116712A JPS607542A (ja) 1983-06-27 1983-06-27 エラ−処理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58116712A JPS607542A (ja) 1983-06-27 1983-06-27 エラ−処理回路

Publications (2)

Publication Number Publication Date
JPS607542A JPS607542A (ja) 1985-01-16
JPS6318223B2 true JPS6318223B2 (enrdf_load_stackoverflow) 1988-04-18

Family

ID=14693942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58116712A Granted JPS607542A (ja) 1983-06-27 1983-06-27 エラ−処理回路

Country Status (1)

Country Link
JP (1) JPS607542A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS607542A (ja) 1985-01-16

Similar Documents

Publication Publication Date Title
KR100819720B1 (ko) 온 칩 백그라운드 디버그 시스템 및 그 방법을 갖는데이터 처리 시스템
JP2595314B2 (ja) 誤書き込み防止機能を備えたｉｃカ―ド
US5357613A (en) Time-domain boundary buffer method and apparatus
US11372461B2 (en) Circuitry for transferring data across reset domains
JPS6318223B2 (enrdf_load_stackoverflow)
US6301188B1 (en) Method and apparatus for registering free flow information
JPH096725A (ja) 非同期データ転送受信装置
JPH04268647A (ja) 二度読み防止機能付レジスタ
KR910000152Y1 (ko) 자기테이프의 오버런/언더런 데이터에러 검출회로
JPS61109154A (ja) 固定デ−タ・レジスタのエラ−検出方式
JP2864779B2 (ja) パルス入力回路
JPS6324503Y2 (enrdf_load_stackoverflow)
JP2979918B2 (ja) 割り込み検出回路
JPH08292828A (ja) インターフェース用雑音防止回路
JP2948714B2 (ja) 受信オーバーラン制御回路
JPS6042973B2 (ja) 入出力情報チエツク方式
JPS5851360A (ja) エラ−・チエック方式
JPS60118964A (ja) インタ−フェイス回路
JPS5836440B2 (ja) 記憶装置制御方式
JPH0495785A (ja) 半導体集積回路装置
JP2005174090A (ja) データ転送回路
JPS6237416B2 (enrdf_load_stackoverflow)
JPS601644B2 (ja) タイミングパルス発生回路
JPH0566632B2 (enrdf_load_stackoverflow)
JPH01149643A (ja) パケットバッファ装置