JPS63177582A - Manufacture of hybrid integrated circuit device - Google Patents

Manufacture of hybrid integrated circuit device

Info

Publication number
JPS63177582A
JPS63177582A JP1078587A JP1078587A JPS63177582A JP S63177582 A JPS63177582 A JP S63177582A JP 1078587 A JP1078587 A JP 1078587A JP 1078587 A JP1078587 A JP 1078587A JP S63177582 A JPS63177582 A JP S63177582A
Authority
JP
Japan
Prior art keywords
layer
electrode conductor
leads
glass
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1078587A
Other languages
Japanese (ja)
Inventor
森尻 友彦
政信 鈴木
健一 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP1078587A priority Critical patent/JPS63177582A/en
Publication of JPS63177582A publication Critical patent/JPS63177582A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はIC等の回路部品のリードを正確に半田接続す
ることができる混成集積回路装置の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a hybrid integrated circuit device in which leads of circuit components such as ICs can be accurately soldered connected.

[従来の技術] 混成S積回路装置の基板上にフラットバット型半導体チ
ップを取付ける場合に半導体チップの多数のリードに対
応する厚膜電極導体層上にクリーム半田層を設け、ここ
にリードを仮接着し、しかる後、クリーム半田層を溶融
し、固化させてリードを固着することは既に行われてい
る。また、リード間即ち電極導体層間が半田によって短
絡することを防止するために、半田付は領域以外にオー
バーコートガラスを設けることも知られている。
[Prior art] When attaching a flat butt type semiconductor chip to a substrate of a hybrid S integrated circuit device, a cream solder layer is provided on a thick film electrode conductor layer corresponding to a large number of leads of the semiconductor chip, and the leads are temporarily attached here. It has already been done to adhere the leads and then melt and solidify the cream solder layer to fix the leads. It is also known to provide an overcoat glass in areas other than the soldering area in order to prevent short circuits between leads, that is, between electrode conductor layers due to solder.

[発明が解決しようとする問題点コ ところで、オーバーコートガラスは、比較的低温(50
0°C〜550℃)で焼成される非晶質ガラスから成る
ので、オーバーコートガラスペーストの焼成時にオーバ
ーコートガラスで被覆する部分としない部分との境界に
おいてオーバーコートガラスのダレが生じ、オーバコー
トガラスを所望領域に正確に設けることが困難であった
。オーバコートガラスの縁にダレが生じると、半田付は
領域上にもオーバコートガラスが付着し、所望の半田付
は領域を確保することが不可能になり、クリーム半田を
所望の電極導体層上に印刷することができず、電極導体
層間の半田ブリッジの発生や、不完全なリード接続状態
が発生する。この種の問題は、リード間隔が0.4m+
aのように極めて狭いフラットパック型半導体チップを
取付ける場合に顕著に生じる。
[Problems to be solved by the invention] By the way, the overcoat glass can be heated at a relatively low temperature (50
Since it is made of amorphous glass that is fired at a temperature of 0°C to 550°C, when the overcoat glass paste is fired, the overcoat glass sag occurs at the boundary between the parts covered with overcoat glass and the parts not covered with overcoat glass, causing overcoat glass to sag. It was difficult to place the glass precisely in the desired area. If sag occurs on the edge of the overcoat glass, the overcoat glass will also adhere to the soldering area, making it impossible to secure the desired soldering area, and leaving the cream solder on the desired electrode conductor layer. This results in solder bridging between electrode conductor layers and incomplete lead connections. This kind of problem occurs when the lead spacing is 0.4m+
This problem occurs noticeably when attaching an extremely narrow flat-pack type semiconductor chip as shown in a.

そこで、本発明の目的は、回路部品のリードを確実且つ
容易に接続することができる混成集積回路の製造方法を
提供することにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a hybrid integrated circuit that allows the leads of circuit components to be connected reliably and easily.

[問題点を解決するための手段コ 上記問題点を解決し、上記目的を達成するための本発明
は、相互に隣接する複数のリードを備えた回路部品を半
田接続するための複数の電極導体層を絶縁基板上に形成
する工程と、前記複数の電極導体層の相互間に、結晶質
ガラスを主成分とする絶縁体層を形成する工程と、前記
複数の電極導体層に半田によって前記回路部品のリード
を接続する工程と、を備えている混成集積回路の製造方
法に係わるものである。
[Means for Solving the Problems] In order to solve the above problems and achieve the above objects, the present invention provides a plurality of electrode conductors for soldering connection of circuit components having a plurality of mutually adjacent leads. forming a layer on an insulating substrate, forming an insulating layer mainly composed of crystalline glass between the plurality of electrode conductor layers, and applying the circuit to the plurality of electrode conductor layers by soldering. The present invention relates to a method of manufacturing a hybrid integrated circuit, which includes a step of connecting leads of components.

[作用] 上記本発明によれば、電極導体層の相互間に結晶質ガラ
スを主成分とする絶縁体層を設けるので、絶縁体層の縁
のダレが少なくなり、所望の半田付は領域を確保するこ
とができる。従って、半田が絶縁体層上に付着するよう
な問題が生じ難くなり、半田によるリード間ブリッジ即
ち短絡が生じ難くなる。
[Function] According to the present invention, since the insulating layer mainly composed of crystalline glass is provided between the electrode conductor layers, sagging at the edges of the insulating layer is reduced, and desired soldering can be performed over the area. can be secured. Therefore, problems such as solder adhering to the insulating layer are less likely to occur, and lead-to-lead bridges or short circuits due to solder are less likely to occur.

[実施例] 次に、第1図及び第2図を参照して本発明の実施例に係
わる混成集積回路装置の製造方法を説明する。
[Embodiment] Next, a method for manufacturing a hybrid integrated circuit device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

まず、第1図(A)に示す如く、セラミック基板1の上
に銀パラジウム導体ペーストを印刷し、乾燥し、焼成(
850°C11o分)することによって、破線で示すI
CIIのリード12の接続用の多数の電極導体層2即ち
半田付はランド、抵抗用電極導体層3、配線導体層4等
を形成する。
First, as shown in FIG. 1(A), a silver-palladium conductor paste is printed on a ceramic substrate 1, dried, and fired (
850°C for 11o minutes) to obtain I shown by the dashed line.
A large number of electrode conductor layers 2 for connecting CII leads 12, ie, soldering, form lands, resistor electrode conductor layers 3, wiring conductor layers 4, and the like.

次に、第1図(B)に示す如く、はうけい酸鉛ガラスを
主成分とする結晶化ガラスペースト(クロスオーバー用
ガラスペースト)を、クロス配線部分及び電極導体JW
2の相互間にスクリーン印刷し、150℃、10分乾燥
し、850℃、10分焼成してクロスオーバーガラス層
5と半田レジスト層として機能する絶縁体7116とを
斜線を付して示すように形成する。クロスオーバガラス
層5及び絶縁体層6は、共に結晶質ガラス90%と非晶
質ガラス10%とから成る結晶質ガラスを主成分とする
軟化温度の高いガラス層である。従って、高温(850
℃)で焼成してもこの周縁におけるダレは極めて少ない
、換言すれば、ガラスペーストの印刷パターンとこの焼
成後のパターンとの差が少ない。
Next, as shown in FIG. 1(B), a crystallized glass paste (crossover glass paste) containing lead silicate glass as a main component is applied to the cross wiring portion and the electrode conductor JW.
2, dried at 150° C. for 10 minutes, and baked at 850° C. for 10 minutes to form a cross-over glass layer 5 and an insulator 7116 functioning as a solder resist layer as shown with diagonal lines. Form. Both the crossover glass layer 5 and the insulator layer 6 are glass layers having a high softening temperature and mainly composed of crystalline glass consisting of 90% crystalline glass and 10% amorphous glass. Therefore, high temperature (850
℃), there is very little sagging at the periphery. In other words, there is little difference between the printed pattern of the glass paste and the pattern after firing.

次に、第1図(C)に示す如くクロス配線導体層7をク
ロスオーバガラス層5の上に形成する。
Next, as shown in FIG. 1C, a cross wiring conductor layer 7 is formed on the crossover glass layer 5.

この導体層7は、銀パラジウム導体ペーストを印刷し、
150℃、10分乾燥し、850℃、10分焼成するこ
とによって形成する。
This conductor layer 7 is made by printing silver palladium conductor paste,
It is formed by drying at 150°C for 10 minutes and baking at 850°C for 10 minutes.

次に、第1図(D)に示す如く、抵抗体ペーストを印刷
し、150℃、10分乾燥し、850 ’C110分焼
成することによって厚膜抵抗体8を電極導体層3の相互
間に形成する。
Next, as shown in FIG. 1(D), a thick film resistor 8 is formed between the electrode conductor layers 3 by printing a resistor paste, drying it at 150°C for 10 minutes, and baking it at 850'C for 110 minutes. Form.

次に、第1図(E)に示す如<IC接続用の電極導体層
2及びその相互間、及び図示されててない他の電極部分
を除いて非晶質のオーバコートガラス層9即ち保護膜を
形成する。このオーバコートガラス層9は、オーバコー
トガラスペーストを印刷し、150℃、10分間乾燥し
、530℃、3分焼成することによって形成する。
Next, as shown in FIG. 1(E), an amorphous overcoat glass layer 9 is formed, except for the electrode conductor layer 2 for IC connection, between them, and other electrode parts not shown. Forms a film. This overcoat glass layer 9 is formed by printing an overcoat glass paste, drying it at 150°C for 10 minutes, and baking it at 530°C for 3 minutes.

次に、厚膜抵抗体8のトリミングを行った後に、第1図
(E)に示す如く電極導体層2上に半田合金粉末とフラ
ックスとから成るクリーム半田(半田ペースト)を印刷
することによってクリーム半田層10を形成する。
Next, after trimming the thick film resistor 8, cream solder (solder paste) consisting of solder alloy powder and flux is printed on the electrode conductor layer 2 as shown in FIG. 1(E). A solder layer 10 is formed.

次に、第2図に示す如< ICI 1のリード12をク
リーム半田/[10の上に載せる。クリーム半田層10
は粘着性を有するので、リード12が仮接着される。
Next, as shown in FIG. 2, the leads 12 of ICI 1 are placed on top of the cream solder/[10]. Cream solder layer 10
has adhesive properties, so the leads 12 are temporarily attached.

次に、クリーム半田層10を溶融し、固化させることに
よってリード12を電極導体M2に固着させる。
Next, the cream solder layer 10 is melted and solidified to fix the lead 12 to the electrode conductor M2.

この実施例では、電極導体層2の相互間の絶縁体層6が
結晶質ガラスを主成分としているために、この周縁のブ
レが極めて少なく、精度の高いパターンが得ら゛れる。
In this embodiment, since the insulating layer 6 between the electrode conductor layers 2 is mainly composed of crystalline glass, there is extremely little wobbling at the periphery, and a highly accurate pattern can be obtained.

このため、0.4鴎のような極めて狭い間隔にも絶縁体
N6を正確に形成することができる。絶縁体層6が電極
導体層2上にダして、ここを汚すことが少なくなるので
、クリーム半田10が絶縁体層6上に印刷されるような
ことが少なくなり、半田ブリッジの発生が少なくなる。
Therefore, the insulator N6 can be accurately formed even at extremely narrow intervals such as 0.4 mm. Since the insulator layer 6 is less likely to drip onto the electrode conductor layer 2 and contaminate it, the cream solder 10 is less likely to be printed on the insulator layer 6, and the occurrence of solder bridges is reduced. Become.

また、リード12の不完全接続の発生も少なくなり、信
頼性が向上する。また、この実施例では、クロスオーバ
ーガラス層5と同時に、絶縁体J16を形成するので、
工程の増加が実質的に生じない。
Moreover, the occurrence of incomplete connections of the leads 12 is reduced, and reliability is improved. Furthermore, in this example, since the insulator J16 is formed at the same time as the crossover glass layer 5,
Substantially no increase in process steps occurs.

[変形例コ 本発明は上述の実施例に限定されるものでなく、変形可
能なものである0例えば、電極導体層2.3及び配線導
体層4を銅ペーストを使用して形成してもよい。
[Modifications] The present invention is not limited to the above-described embodiments, and may be modified. For example, the electrode conductor layer 2.3 and the wiring conductor layer 4 may be formed using copper paste. good.

[発明の効果] 上述から明らかな如く、本発明によれば、リードの接続
を確実に行うことができる。
[Effects of the Invention] As is clear from the above, according to the present invention, the leads can be connected reliably.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)(B)(C)<D)(E)は、本発明に従
う混成集積回路装置を製造工程順に示す平面図、 第2図は第1図(E)の■−■線に相当する部分をリー
ドを接続した状態で示す断面図である。 1 セラミック基板 2 電極導体層 ラ クロスオーバーガラス層 6 絶縁体層 9 オーバーコートガラス層 10 クリーム半田 1  IC 12リード ■4コ 手続補正書(自発) 昭和62年9月11日 】、事件の表示 昭和62年 特 許   麗 第10785  号2、
発明の名称  混成集積回路装置の製造方法3 補正を
する者 事件との関係   出願人 4、代理人 5、補正命令の日付  自  発 6 補正により増加する発明の数 7 補正の対象 図面(第1図囚@0)。 8、補正の内容 図面第1図(4)@Ωを添付図面に補
正する。 第1図
Figures 1 (A), (B), (C) < D, and (E) are plan views showing the hybrid integrated circuit device according to the present invention in the order of manufacturing steps, and Figure 2 is the line ■-■ in Figure 1 (E). FIG. 3 is a cross-sectional view showing a portion corresponding to , with leads connected thereto. 1 Ceramic substrate 2 Electrode conductor layer Crossover glass layer 6 Insulator layer 9 Overcoat glass layer 10 Cream solder 1 IC 12 leads 1962 Patent Rei No. 10785 2,
Title of the invention Method for manufacturing a hybrid integrated circuit device 3 Relationship with the case of the person making the amendment Applicant 4, attorney 5, date of amendment order Initiator 6 Number of inventions increased by the amendment 7 Drawings to be amended (Fig. 1) prisoner @0). 8. Details of the amendment: Figure 1 (4) @Ω will be corrected to the attached drawing. Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)相互に隣接する複数のリードを備えた回路部品を
半田接続するための複数の電極導体層を絶縁基板上に形
成する工程と、 前記複数の電極導体層の相互間に、結晶質ガラスを主成
分とする絶縁体層を形成する工程と、前記複数の電極導
体層に半田によつて前記回路部品のリードを接続する工
程と を備えていることを特徴とする混成集積回路装置の製造
方法。
(1) A step of forming a plurality of electrode conductor layers on an insulating substrate for soldering circuit components having a plurality of adjacent leads, and a step of forming a crystalline glass between the plurality of electrode conductor layers. manufacturing a hybrid integrated circuit device comprising the steps of: forming an insulator layer containing as a main component; and connecting leads of the circuit component to the plurality of electrode conductor layers by solder. Method.
(2)前記半田によって前記回路部品のリードを接続す
る工程が、前記電極導体層上にクリーム半田層を設け、
このクリーム半田層を使用して前記リードを前記電極導
体層に結合させることを含むことを特徴とする特許請求
の範囲第1項記載の混成集積回路装置の製造方法。
(2) the step of connecting the leads of the circuit component with the solder includes providing a cream solder layer on the electrode conductor layer;
2. The method of manufacturing a hybrid integrated circuit device according to claim 1, further comprising bonding the lead to the electrode conductor layer using the cream solder layer.
JP1078587A 1987-01-19 1987-01-19 Manufacture of hybrid integrated circuit device Pending JPS63177582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1078587A JPS63177582A (en) 1987-01-19 1987-01-19 Manufacture of hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1078587A JPS63177582A (en) 1987-01-19 1987-01-19 Manufacture of hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS63177582A true JPS63177582A (en) 1988-07-21

Family

ID=11759989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1078587A Pending JPS63177582A (en) 1987-01-19 1987-01-19 Manufacture of hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63177582A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH032673U (en) * 1989-05-31 1991-01-11

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142858B2 (en) * 1978-11-29 1986-09-24 Nippon Electric Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142858B2 (en) * 1978-11-29 1986-09-24 Nippon Electric Co

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH032673U (en) * 1989-05-31 1991-01-11

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