JPS63177439A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device in which one layer of a semiconductor surface is flattened, crystal defects are reduced, and one layer is reduced in size by burying a polycrystalline silicon surrounded by an insulating layer in a groove formed on a semiconductor substrate. CONSTITUTION:A fine groove having a sidewall deeper than a very fine width thereof and substantially perpendicular to a semiconductor substrate 4 surface is formed in the substrate 4, and thin insulating films 5 are formed on the sidewall and the bottom of the groove. A polycrystalline silicon 6 having a flat surface in the height substantially equal to the opening of the groove and electrically connected to a power source is buried in a region surrounded by the films 5 in the groove. For example, a groove is formed on a silicon substrate 4, and a thin silicon oxide film 5 is formed. Then, a polycrystalline silicon 6 is covered, the polycrystalline silicon on the substrate surface is removed, with a silicon nitride film 1 as a mask a separating region field between elements is ion implanted, and the silicon nitride film is removed. The silicon 6 is connected to a positive or negative power source.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO3 type semiconductor device. Conventional MO8 type semiconductor devices have generally been constructed by forming isolation regions between elements by selective oxidation of a substrate. However, when a semiconductor device is constructed by selective oxidation of a substrate, there are drawbacks such as limitations on miniaturization of the semiconductor device, steps on the surface of the semiconductor device, and crystal defects in the semiconductor device. In order to eliminate the drawbacks of the prior art, the present invention is characterized in that a polycrystalline semiconductor region surrounded by an insulating layer is embedded in the element isolation region. An object of the present invention is to provide an MO3 semiconductor device in which the semiconductor surface is further reduced in flatness and crystal defects, and the device is further miniaturized.

This will be explained in detail below using examples.

FIG. 1 shows a cross-sectional view of the conventional technique, taking as an example an element isolation region, which is the simplest structure of an MO3 type semiconductor device. It is the same thing that was formed. Region 3 is an element isolation field ion implantation region. In this case, the oxide film penetrates under the silicon nitride film and the element isolation field ion implantation region spreads laterally, which impedes miniaturization of semiconductor devices. Further, by thermally oxidizing the substrate thickly, crystal defects and steps on the semiconductor surface occur.

Parts 2 to 6 show a cross-sectional view (Fig. 6) of an isolation field when polycrystalline silicon surrounded by a silicon oxide film is buried in an isolation region as an example of the present invention. This is a manufacturing process diagram (FIGS. 2 to 6). In FIG. 2, grooves are formed by partially anisotropically etching or ion etching the n-type silicon substrate 4. The figure shows a thin silicon oxide film 5 due to thermal oxidation.
is formed in the groove of the silicon substrate. Since this oxide film does not require a large thickness, crystal defects can be minimized. In FIG. 4, polycrystalline silicon is deposited by the CVD method to completely fill the narrow grooves in the silicon substrate with polycrystalline silicon. By ion etching, it is possible to form narrow and deep grooves with a width of about 1 μm.
Grooves as narrow as μm can be filled with polycrystalline silicon using the CVD method. In Figure 5, the polycrystalline silicon on the surface of the silicon substrate is removed by etching, leaving only the polycrystalline silicon embedded in the silicon substrate. Next, using the silicon nitride film with the groove pattern of the silicon substrate as a mask, field ion implantation is performed in the element isolation region, and high concentration n-type ions are implanted into the buried polycrystalline silicon.Fifth The figure shows the element isolation region obtained by activating field ions and removing the silicon nitride film. 1 is a cross-sectional view of an element isolation field of an MO3 type semiconductor,
This polycrystalline silicon region is connected to a positive or negative power source to control the potential around the element isolation region.

According to the present invention, the lateral spread of element isolation field ions is limited by the surrounding thin silicon oxide film.

Furthermore, since patterning accuracy is determined by ion etching accuracy, MO3 type semiconductor devices can be further miniaturized. Furthermore, by embedding polycrystalline silicon surrounded by a thin silicon oxide film in the element isolation region, a semiconductor device is provided in which steps and crystal defects on the substrate surface are minimized.

[Brief explanation of the drawing]

FIG. 1: A sectional view of a conventional element isolation field. FIGS. 2 to 6 are cross-sectional views of an isolation field between elements of an MO3 type semiconductor device according to the present invention, and a process sequence thereof. 1... Silicon nitride film 2... Thermal oxidation silicon film 3... Element isolation ion implantation 4... Silicon substrate 5... Thin thermal oxide film 6... Polycrystalline silicon 7... Ion implantation Above Figure 1 Figure 2 Figure 3 Haze Figure 4 ↓ ↓ ↓ ↓ ↓ ↓ ↓ To 7 Answer 6 Director General of the Patent Office Kunio Ogawa Patent layer (B) 2゜ invention submitted on December 18, 1986 Name of semiconductor device 3, Relationship to the amended person case Applicant Tsuneya Nakamura, Representative Director, Seiko Epson Corporation, 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo 5, Specification subject to amendment (full text) (Amendment) Description 1. Name of the invention Semiconductor device 2. Claims = thinning) 3. Detailed description of the invention The present invention relates to a semiconductor device. Conventional MO3 type semiconductor devices have generally been constructed by forming isolation regions between elements by selective oxidation of a substrate. For example, FIG. 1 shows a cross-sectional view of the prior art, taking an element isolation region, which is the simplest structure of a semiconductor device, as an example. was formed. Region 3 is an element isolation field ion implantation region. In this case, the oxide film penetrates under the silicon nitride film 1;
The horizontal expansion of the element isolation field ion implantation region 3 hinders miniaturization of semiconductor devices. Further, by thermally oxidizing the substrate thickly, crystal defects and steps on the semiconductor surface occur. As described above, when a semiconductor device is constructed by selective oxidation of a substrate, there are drawbacks such as limitations on miniaturization of the semiconductor device, steps on the surface of the semiconductor device, and crystal defects in the semiconductor device. In order to eliminate the drawbacks of the prior art, the present invention is characterized in that a polycrystalline semiconductor region surrounded by an insulating layer is embedded in the element isolation region. An object of the present invention is to provide a semiconductor device in which the semiconductor surface is further planarized, crystal defects are reduced, and the size is further reduced. This will be explained in detail below using examples. FIGS. 2 to 6 show a cross-sectional view of an isolation field (FIG. 6) in which polycrystalline silicon surrounded by a silicon oxide film is embedded in an isolation region as an example of the present invention, and its manufacture. It shows process order diagrams (Figs. 2 to 6). In FIG. 2, an n-type silicon substrate 4 is partially anisotropically etched or ion etched to form sidewalls on the substrate surface with a very narrow width, for example, about 1 μm, and a depth greater than the width. A groove is formed that is almost perpendicular to the surface. In FIG. 3, a thin silicon oxide film 5 is formed in a groove of a silicon substrate 4 by thermal oxidation. Since this oxide film does not require a large thickness, crystal defects can be minimized. In Figure 4, thin grooves in the silicon substrate are filled with polycrystalline silicon by depositing polycrystalline silicon using the CVD method.
It is possible to form a scarlet and deep groove whose side wall is almost perpendicular to the silicon substrate 4 and has a width of about 1 μm.
A fairly narrow groove can be completely filled with polycrystalline silicon produced by CVD, and its height can be approximately equal to the opening of the groove in the substrate, and its surface can be made flat. Fifth
In the figure, the polycrystalline silicon on the surface of the silicon substrate is removed by etching, leaving only the polycrystalline silicon embedded in the silicon substrate. Next, using the silicon nitride film having the groove pattern of the silicon substrate as a mask, field ion implantation is performed in the element isolation region, and high concentration n-type ions are implanted into the buried polycrystalline silicon. Figure 6 shows the element isolation region obtained by activating field ions and removing the silicon nitride film. A cross-sectional view of the device isolation field of the embedded semiconductor, the polycrystalline silicon region is
It is electrically connected to a positive or negative power source to control the potential around the element isolation region. According to the present invention, the transverse wave of the element isolation field ions is limited by the surrounding thin silicon oxide film. Furthermore, since patterning accuracy is determined by ion etching accuracy, semiconductor devices can be further miniaturized. Furthermore, by embedding polycrystalline silicon surrounded by a thin silicon oxide film in the element isolation region, a semiconductor device is provided in which steps and crystal defects on the substrate surface are minimized. As described above, the present invention has a very thin groove, for example, a width of about 1 μm and a depth greater than the width, and whose sidewalls are almost perpendicular to the substrate surface, through which a thin insulating film is formed. Since the polycrystalline silicon is embedded so that the surface is flat and approximately at the same height as the opening of the groove formed in the substrate, further miniaturization and higher reliability of semiconductor devices can be achieved. It has the following. 4. Brief description of the drawings FIG. 1: A sectional view of a conventional isolation field. FIGS. 2 to 6 are cross-sectional views of semiconductor devices according to embodiments of the present invention and their process steps. 1...Silicon nitride film 2...Thermal oxidation silicon film 3...Element isolation ion implantation 4...Silicon substrate 5...Thin thermal oxide film 6...Polycrystalline silicon 7...Ion implantation that's all

Claims (2)

[Claims] (1) A semiconductor device characterized in that a polycrystalline semiconductor region surrounded by an insulating layer is embedded in a single crystal semiconductor substrate. (2) The semiconductor device according to claim 1, wherein a polycrystalline semiconductor region surrounded by an insulating layer is embedded in an element isolation region of a single crystal semiconductor substrate.