JPS63174309A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63174309A
JPS63174309A JP507287A JP507287A JPS63174309A JP S63174309 A JPS63174309 A JP S63174309A JP 507287 A JP507287 A JP 507287A JP 507287 A JP507287 A JP 507287A JP S63174309 A JPS63174309 A JP S63174309A
Authority
JP
Japan
Prior art keywords
film
single crystal
semiconductor
region
element forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP507287A
Other languages
Japanese (ja)
Other versions
JPH0740550B2 (en
Inventor
Minoru Takahashi
稔 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP507287A priority Critical patent/JPH0740550B2/en
Publication of JPS63174309A publication Critical patent/JPS63174309A/en
Publication of JPH0740550B2 publication Critical patent/JPH0740550B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the generation of a bird's beak by forming a recessed groove in an element forming region on the surface of an insulating film deposited on a substrate and by forming the single crystal semiconductor element forming region deposited on the insulating film thicker than the other region. CONSTITUTION:After an SiO2 film 12 on which a groove 13 is formed is formed on a single crystal Si substrate 11 and a polycrystalline Si film 14 is formed on the SiO2 film 12, the film 14 is melted by irradiating an electron beam and recrystallized and a single crystal Si film 14' is formed. In this case, the Si film near an element forming region flows over the groove 13 and the thickness of the film 14' in the element forming region is made thicker. Then, an Si3N4 film 17 is formed in the element forming region and a field oxide film 18 is formed by oxidizing the film 14' using the film 17 as a mask. In this case, a bird's beak is not extended to the element forming region since the thickness of the single crystal Si film except the element forming region where the film 18 is to be formed is thinner. Then, the film 17 is removed and a gate oxide film 19, a gate electrode 20, a source region 21, a drain region 22, an Al wiring 24, etc., are formed.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置の製造方法に係わり、特に絶縁膜
上に単結晶半導体膜を形成して素子を3次元的に積層す
る半導体装置の製造方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a device three-dimensionally by forming a single crystal semiconductor film on an insulating film. The present invention relates to a method for manufacturing stacked semiconductor devices.

(従来の技術) 近年、半導体装置の高集積化・高密度化のために素子は
益々微細化されているが、素子の微細化には限度があり
、素子を2次元的に配置するのではその集積度の向上も
限界近くになっている。
(Prior art) In recent years, elements have become increasingly finer due to the higher integration and density of semiconductor devices, but there is a limit to the miniaturization of elements, and it is difficult to arrange elements two-dimensionally. Improvements in the degree of integration are nearing their limits.

そこで最近、基板のみならず絶縁膜上にも素子を形成す
ることにより、素子を3次元的に積層する、所謂3次元
ICが提案されている。
Therefore, recently, a so-called three-dimensional IC has been proposed in which elements are stacked three-dimensionally by forming elements not only on a substrate but also on an insulating film.

3次元ICを製造するには、シリコン基板上に堆積した
絶縁膜上に単結晶半導体膜を形成する必要がある。この
ため、シリコン基板上に堆積した絶縁膜上に多結晶若し
くは非晶質の半導体膜を堆積し、レーザビームや電子ビ
ームの照射(ビームアニール)により半導体膜を単結晶
化している。
To manufacture a three-dimensional IC, it is necessary to form a single crystal semiconductor film on an insulating film deposited on a silicon substrate. For this reason, a polycrystalline or amorphous semiconductor film is deposited on an insulating film deposited on a silicon substrate, and the semiconductor film is made into a single crystal by irradiation with a laser beam or an electron beam (beam annealing).

そして、この単結晶膜に素子を形成することにより、基
板に形成した下層素子と単結晶膜に形成した上層素子と
を絶縁膜を介して積層した2層構造が実現されることに
なる。また、上層素子上に、更に絶縁膜を介して単結晶
膜を形成し、この単結晶膜に素子を形成することにより
、3層構造が実現されることになる。
By forming an element on this single crystal film, a two-layer structure is realized in which a lower layer element formed on the substrate and an upper layer element formed on the single crystal film are laminated with an insulating film interposed therebetween. Furthermore, a three-layer structure is realized by forming a single crystal film on the upper layer element via an insulating film and forming the element on this single crystal film.

しかしながら、この種の方法にあっては次のような問題
があった。即ち、単結晶膜に素子を形成−1って(る。
However, this type of method has the following problems. That is, an element is formed on a single crystal film (1).

特に、熱酸化により素子分離を行う場゛合、単結晶膜厚
の増大に伴い熱酸化時間を増加しなければならず、バー
ズビークと呼ばれる素子領域内への酸化侵入により、短
チヤネル素子形成が困難であった。また、素子分離を容
易にする目的で単結晶半導体膜を薄くすると、半導体膜
の薄膜化に伴い半導体素子の電気的耐圧が減少すること
になり、良好な素子特性を得ることが困難となる。
In particular, when device isolation is performed by thermal oxidation, the thermal oxidation time must be increased as the single crystal film thickness increases, and oxidation invasion into the device region called bird's beak makes it difficult to form short channel devices. Met. Furthermore, if a single crystal semiconductor film is made thinner for the purpose of facilitating element isolation, the electrical breakdown voltage of the semiconductor element decreases as the semiconductor film becomes thinner, making it difficult to obtain good element characteristics.

なお、上記バーズビークの発生を第2図を参照して説明
しておく。シリコン基板31上の絶縁膜32上に単結晶
シリコン膜34を形成したのち、素子形成領域上のみに
シリコン窒化膜37を形成し、この状態で素子分離のた
めの熱処理を施す。
Incidentally, the occurrence of the bird's beak will be explained with reference to FIG. 2. After forming a single-crystal silicon film 34 on an insulating film 32 on a silicon substrate 31, a silicon nitride film 37 is formed only on the element formation region, and in this state a heat treatment for element isolation is performed.

このとき、シリコン窒化膜37のない部分ではシリコン
膜が酸化されシリコン酸化膜38となる。
At this time, the silicon film is oxidized to become a silicon oxide film 38 in the areas where the silicon nitride film 37 is not present.

さらに、シリコン窒化膜37の端部から該窒化膜37の
下部に酸化剤が侵入し、シリコン窒化膜37の下部にお
いても酸化が進み、ここにバーズビーク39が生じるの
である。
Furthermore, the oxidizing agent penetrates into the lower part of the silicon nitride film 37 from the edge of the silicon nitride film 37, and oxidation progresses in the lower part of the silicon nitride film 37, resulting in the formation of bird's beaks 39 there.

(発明が解決しようとする問題点) このように従来方法では、絶縁膜上の単結晶半導体膜に
半導体素子を形成する際、半導体膜が厚くなるに従い素
子分離の熱酸化時間を増加しなければならず、結果とし
てバーズビークが増加し、短チヤネル素子を形成するこ
とが困難になると云う問題点があった。また、バーズビ
ークを低減させるために単結晶膜を薄くした場合、電界
効果型:乎導体素子においては、ソース・ドレイン間ノ
耐圧が減少し、素子特性が劣化すると云う問題がある。
(Problems to be Solved by the Invention) In this way, in the conventional method, when forming a semiconductor element on a single crystal semiconductor film on an insulating film, it is necessary to increase the thermal oxidation time for element isolation as the semiconductor film becomes thicker. However, as a result, the number of bird's beaks increases, making it difficult to form a short channel element. Further, when the single crystal film is made thinner in order to reduce bird's beak, there is a problem in that in a field effect type conductor element, the withstand voltage between the source and drain decreases, and the element characteristics deteriorate.

本発明は上記事情を考慮してなされたもので、その目的
とするところは、素子領域の単結晶膜厚を厚くしてソー
ス・ドレイン間の耐圧を十分大きくすることができ、且
つ素子分離工程に起因するバーズビークを小さくするこ
とができ、3次元ICの製造に好適する半導体装置の製
造方法を提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to increase the thickness of the single crystal film in the element region to sufficiently increase the withstand voltage between the source and drain, and to improve the device isolation process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce bird's beak caused by , and is suitable for manufacturing a three-dimensional IC.

[発明の構成] (問題点を解決するための手段) 本発明の骨子は、素子形成領域では単結晶半導体膜の膜
厚を厚く形成し、素子分離領域では単結晶半導体膜の膜
厚を薄く形成することにある。
[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to form a single crystal semiconductor film thickly in the element formation region and to reduce the thickness of the single crystal semiconductor film in the element isolation region. It is about forming.

即ち本発明は、半導体基板上に堆積した絶縁膜上に半導
体素子を形成する半導体装置の製造方法において、前記
絶縁膜の表面に該絶縁膜上の素子領域となるべき領域に
対応して凹型の溝を形成したのち、前記絶縁膜上に多結
晶若しくは非晶質の半導体膜を堆積し、次いでビームア
ニール法により上記半導体膜を単結晶化し、しかるのち
上記単結晶化した半導体膜に所望の素子を形成するよう
にした方法である。
That is, the present invention provides a method for manufacturing a semiconductor device in which a semiconductor element is formed on an insulating film deposited on a semiconductor substrate, in which a concave shape is formed on the surface of the insulating film corresponding to a region on the insulating film that is to become an element region. After forming the groove, a polycrystalline or amorphous semiconductor film is deposited on the insulating film, and then the semiconductor film is made into a single crystal by a beam annealing method, and then a desired element is formed in the single crystal semiconductor film. This is a method that allows the formation of

(作用) ビームアニール時の半導体膜は液状に溶融しているため
、凹型溝の外部の半導体膜は溝の内部に流れ込み、溝外
部よりも溝内部の方が半導体膜の膜厚が増加する。従っ
て、ビームアニール前に絶縁膜全面に堆積した半導体膜
は、ビームアニール後では素子領域となるべき領域のみ
厚くなる。
(Function) Since the semiconductor film is melted in a liquid state during beam annealing, the semiconductor film outside the concave groove flows into the inside of the groove, and the thickness of the semiconductor film inside the groove is increased more than outside the groove. Therefore, the semiconductor film deposited on the entire surface of the insulating film before beam annealing becomes thicker only in the region that is to become the element region after beam annealing.

このことから、電界効果型半導体素子を形成する溝部の
半導体膜厚をソース・ドレイン間の耐圧低下を防止する
に十分な厚さにすることが可能となる。一方、素子分離
工程で酸化すべき溝外領域の半導体膜厚は薄くなるので
、熱酸化時間の短縮に伴いバーズビーク増加が防止され
、短チャネルの電界効果型半導体素子の形成が可能とな
る。
From this, it is possible to make the semiconductor film thickness of the trench portion in which the field effect semiconductor element is formed to be thick enough to prevent a decrease in breakdown voltage between the source and drain. On the other hand, since the thickness of the semiconductor film in the region outside the trench to be oxidized in the element isolation step becomes thinner, the increase in bird's beak is prevented as the thermal oxidation time is shortened, and a short channel field effect semiconductor element can be formed.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図は本発明の一実施例に係わる半導体装置の製造工
程を示す断面図である。まず、第1図(a)に示す如く
、所望の素子が形成された単結晶Si基板11上にスパ
ッタ法或いはCVD法にi予分離領域となるべき部分に
図示しないレジスト1彎、 −パターンを形成し、このレジストパターンをマスクに
5i02膜12をRIE等によりエツチングして、5i
02膜12の表面に5000 [入]の深さの溝13を
形成する。次いで、第1図(b)に示す如く、全面に厚
さaooo [人]の多結晶Si膜(半導体膜)14を
堆積する。
FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), a resist pattern (not shown) is formed on a single crystal Si substrate 11 on which a desired element is formed by sputtering or CVD in a portion that is to become an i pre-separation region. Using this resist pattern as a mask, the 5i02 film 12 is etched by RIE or the like.
A groove 13 with a depth of 5000 mm is formed on the surface of the 02 film 12. Next, as shown in FIG. 1(b), a polycrystalline Si film (semiconductor film) 14 is deposited over the entire surface to a thickness of aooo [man].

次いで、第1図(c)に示す如く、電子ビーム15を照
射して一方向に走査するこ−とにより、多結晶Si膜1
4を溶融再結晶化して単結晶Si膜14′を形成する。
Next, as shown in FIG. 1(c), the polycrystalline Si film 1 is irradiated with an electron beam 15 and scanned in one direction.
4 is melted and recrystallized to form a single crystal Si film 14'.

このとき、素子形成領域近傍のSi膜は、溝部13上に
流れ込み、素子形成領域の単結晶Si膜14′の膜厚が
5000 [入]となった。また、素子形成領域近傍の
単結晶Si膜14′の膜厚は1500 [人]と薄膜化
した。なお、電子ビーム15の加速電圧は12 [ke
V] 、  ビーム電流は2 [mA] とした。
At this time, the Si film near the element formation region flowed onto the groove 13, and the thickness of the single crystal Si film 14' in the element formation region became 5000 mm thick. Furthermore, the thickness of the single crystal Si film 14' near the element formation region was reduced to 1500 [layers]. Note that the acceleration voltage of the electron beam 15 is 12 [ke
V], and the beam current was 2 [mA].

次いで、第1図(d)に示す如く、単結晶SL膜1り′
上に5i3Na膜17を2000 [人]の厚さに堆積
し、図示しないレジストパターンをマスクに素子形成領
域のみにSi3N4膜17を残存i4′を酸化し、第1
図(e)に示す如くフィー+6.、Vレジスト1彎を形
成する。このとき、フィールド酸化膜18を形成すべき
素子形成領域以外の単結晶Si膜の膜厚が十分薄いので
、素子形成領域にバーズビークが伸びることは殆どなか
った。
Next, as shown in FIG. 1(d), a single crystal SL film 1'
A 5i3Na film 17 is deposited on top to a thickness of 2000 μm, and a Si3N4 film 17 is deposited only on the element formation region using a resist pattern (not shown) as a mask, and the remaining i4' is oxidized.
As shown in figure (e), fee +6. , a V resist 1 curve is formed. At this time, since the thickness of the single crystal Si film other than the element formation region where the field oxide film 18 is to be formed was sufficiently thin, the bird's beak hardly extended into the element formation region.

次いで、第1図(f)に示す如く、5t31’Ja膜1
7を180[・℃]の燐酸液により除去した後、酸素雰
囲気による熱酸化法によりゲート酸化膜19を400[
人]の厚さに形成する。その後、通常のNチャネルMO
Sトランジスタ製造工程と同様に、第1図(g)に示す
如くゲート電極20゜ソース・ドレイン領域21.22
を形成し、さらに5i02膜23及びA、ff配線24
を形成する。
Next, as shown in FIG. 1(f), the 5t31'Ja film 1
After removing the gate oxide film 19 with a phosphoric acid solution at 180[°C], the gate oxide film 19 is heated to a temperature of 400[°C] by thermal oxidation in an oxygen atmosphere.
form to the thickness of a person]. Then a normal N-channel MO
Similarly to the S transistor manufacturing process, as shown in FIG.
, and further 5i02 film 23 and A, ff wiring 24
form.

これにより、素子を3次元的に積層した3次元ICが実
現されることになる。
As a result, a three-dimensional IC in which elements are three-dimensionally stacked is realized.

かくして本実施例方法によれば、ビームアニール前の多
結晶Si膜14が3000 [人]と薄いにも拘らず、
ビームアニール後の単結晶Si膜14′のMOSトラン
ジスタ形成領域が5000 [人]と厚くなっている。
Thus, according to the method of this embodiment, even though the polycrystalline Si film 14 before beam annealing is as thin as 3,000 [people],
The MOS transistor forming region of the single crystal Si film 14' after beam annealing is as thick as 5000 [people].

このため、ソース・ドレイン間耐圧不良が発生すること
はなく、良好な素子特性を得ることができる。また、ビ
ームアニール後の゛ヱクを著しく低減することが可能と
なる。従って、良好な素子特性を有する短チヤネル素子
を形成することができ、3次元IC等の製造に極めて有
効である。
Therefore, source-drain breakdown voltage failure does not occur, and good device characteristics can be obtained. Furthermore, it becomes possible to significantly reduce the damage after beam annealing. Therefore, it is possible to form a short channel device with good device characteristics, which is extremely effective in manufacturing three-dimensional ICs and the like.

なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記絶縁膜上の半導体膜をアニールす
る手段として、電子ビームの代りにレーザビームを用い
たレーザアニールを行うようにしてもよい。また、半導
体膜は多結晶Siに限るものではなく、非晶質Stであ
ってもよく、さらに他の半導体材料を用いることも可能
である。
Note that the present invention is not limited to the method of the embodiment described above. For example, as a means for annealing the semiconductor film on the insulating film, laser annealing using a laser beam instead of an electron beam may be performed. Further, the semiconductor film is not limited to polycrystalline Si, but may be amorphous St, and other semiconductor materials may also be used.

また、単結晶半導体膜に形成する半導体素子はMOS)
ランジスタに限るものではなく、各種の半導体素子に適
用可能である。さらに、絶縁膜の膜厚、エツチング方法
及び単結晶半導体膜の酸化方法等は、仕様に応じて適宜
変更可能である。その他、本発明の要旨を逸脱しない範
囲で、種々変形して実施することができる。
In addition, the semiconductor element formed on the single crystal semiconductor film is MOS)
The present invention is not limited to transistors, and can be applied to various semiconductor devices. Further, the thickness of the insulating film, the etching method, the oxidation method of the single crystal semiconductor film, etc. can be changed as appropriate depending on the specifications. In addition, various modifications can be made without departing from the gist of the present invention.

【発明の効果] 以上詳述したように本発明によれば、素子領域の単結晶
膜厚を厚くし、ソース・ドレイン間のICの製造に極め
て有効となる。
[Effects of the Invention] As described in detail above, according to the present invention, the single crystal film thickness in the element region can be increased, which is extremely effective in manufacturing an IC between a source and a drain.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例方法に係わる半導体装置の製
造工程を示す断面図、第2図は従来の問題点を説明する
ための断面図である。 11・・・Si基板、12・・・5i02膜(絶縁膜)
、13・・・凹型溝、14・・・多結晶Si膜(半導体
膜)、14′・・・単結晶Si膜、15・・・電子ビー
ム、17・・・5i3Ni膜、18・・・フィールド酸
化膜、19・・・ゲート酸化膜、20・・・ゲート電極
、21.22・・・ソース・ドレイン領域。 出願人 工業技術院長 飯塚 幸三 第1図
FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining the problems of the conventional method. 11...Si substrate, 12...5i02 film (insulating film)
, 13... Concave groove, 14... Polycrystalline Si film (semiconductor film), 14'... Single crystal Si film, 15... Electron beam, 17... 5i3Ni film, 18... Field Oxide film, 19... Gate oxide film, 20... Gate electrode, 21.22... Source/drain region. Applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に堆積した絶縁膜上に半導体素子を
形成する半導体装置の製造方法において、前記絶縁膜の
表面に該絶縁膜上の素子領域となるべき領域に対応して
凹型の溝を形成する工程と、前記絶縁膜上に多結晶若し
くは非晶質の半導体膜を堆積する工程と、ビームアニー
ル法により上記半導体膜を単結晶化する工程と、上記単
結晶化した半導体膜に所望の素子を形成する工程とを含
むことを特徴とする半導体装置の製造方法。
(1) In a method of manufacturing a semiconductor device in which a semiconductor element is formed on an insulating film deposited on a semiconductor substrate, a concave groove is formed in the surface of the insulating film corresponding to a region on the insulating film that is to become an element region. a step of depositing a polycrystalline or amorphous semiconductor film on the insulating film; a step of making the semiconductor film into a single crystal by a beam annealing method; 1. A method for manufacturing a semiconductor device, comprising the step of forming an element.
(2)前記単結晶化した半導体膜は、単結晶化以前に比
し凹型溝内部の膜厚が溝外部の膜厚よりも厚くなること
を特徴とする特許請求の範囲第1項記載の半導体装置の
製造方法。(3)前記ビームアニール法として、電子ビ
ーム或いはレーザビームを用い、このビームを前記半導
体膜上で走査することを特徴とする特許請求の範囲第1
項記載の半導体装置の製造方法。
(2) The semiconductor film according to claim 1, wherein the single crystallized semiconductor film has a film thickness inside the concave groove that is thicker than the film outside the groove compared to before the single crystallization. Method of manufacturing the device. (3) The first aspect of the present invention is characterized in that the beam annealing method uses an electron beam or a laser beam and scans the beam on the semiconductor film.
A method for manufacturing a semiconductor device according to section 1.
JP507287A 1987-01-14 1987-01-14 Method for manufacturing semiconductor device Expired - Lifetime JPH0740550B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP507287A JPH0740550B2 (en) 1987-01-14 1987-01-14 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP507287A JPH0740550B2 (en) 1987-01-14 1987-01-14 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63174309A true JPS63174309A (en) 1988-07-18
JPH0740550B2 JPH0740550B2 (en) 1995-05-01

Family

ID=11601184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP507287A Expired - Lifetime JPH0740550B2 (en) 1987-01-14 1987-01-14 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0740550B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016655A (en) * 2006-07-06 2008-01-24 Sumitomo Heavy Ind Ltd Method for manufacturing crystallized semiconductor film

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101648867B1 (en) * 2009-06-02 2016-08-17 삼성전자주식회사 Manufacturing Method of Si Film using Si Solution Process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016655A (en) * 2006-07-06 2008-01-24 Sumitomo Heavy Ind Ltd Method for manufacturing crystallized semiconductor film

Also Published As

Publication number Publication date
JPH0740550B2 (en) 1995-05-01

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