JPS63173420A - Analog/digital converter - Google Patents

Analog/digital converter

Info

Publication number
JPS63173420A
JPS63173420A JP554987A JP554987A JPS63173420A JP S63173420 A JPS63173420 A JP S63173420A JP 554987 A JP554987 A JP 554987A JP 554987 A JP554987 A JP 554987A JP S63173420 A JPS63173420 A JP S63173420A
Authority
JP
Japan
Prior art keywords
converter
voltage
circuit
conversion
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP554987A
Other languages
Japanese (ja)
Inventor
Takehisa Matsuura
松浦 武久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP554987A priority Critical patent/JPS63173420A/en
Publication of JPS63173420A publication Critical patent/JPS63173420A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve the accuracy of A/D conversion by holding a D/A converter output voltage in obtaining an A/D converter by a sample-and-hold circuit, amplifying the difference between the value and a signal to be measured and applying A/D conversion again so as to add a value of new A/D conversion to a conventional A/D conversion value. CONSTITUTION:A sample-and-hold circuit 8 outputs an A/D conversion value Da obtained by a conventional circuit constitution and samples and holds the output voltage of a D/A converter 5 by the control of the timing circuit 6. The holding voltage is inputted to a differential amplifier 9 together with an output voltage of the buffer circuit 1 and only the difference of the both is amplified. The amplification factor in this case is selected to amplify the error voltage within one bit resolution to a value of A/D conversion again. When a switch circuit 10 selects the differential amplifier 9, the measuring range is decided by the amplification factor set by the differential amplifier 9 and its value is given in the same process as the A/D conversion by a conventional circuit operation to obtain the conversion data. Since the conversion data is given to the least significant bit of the conventional circuit operation, then the measuring accuracy as the A/D converter is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は波計側信号とし【アナログ信号を取扱う計測
分野に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to the field of measurement that handles analog signals as signals on the wave meter side.

〔従来の技術〕[Conventional technology]

第2図は従来の逐次比較型A/D変換装置であり。 FIG. 2 shows a conventional successive approximation type A/D converter.

図において、(1)は波計副信号をインピーダンス変換
するためのバッファ回路、(21は上記バッファ回路(
1)の信号とD/A変換器+51の信号vt電圧比較る
電圧比軟型コンパレータ(31は電圧比軟型コンパレー
タ121の信号を蓄積する逐次比軟レジスタ、(41は
基準電圧発生回路、(51は上記基準電圧発生回路(4
)の電圧を入力し逐次比較レジスタ(31のデータに対
応したアナログ電圧を発生させるo/A変換器(6)は
上記動作のタイミングを制御するタイミング回路、(7
)は上記逐次比較レジスタ(3)の出力であるA/D変
換値を蓄積するためのレジスタ、Daは上記レジスタ(
71の出力値である。
In the figure, (1) is a buffer circuit for impedance conversion of the wave meter sub-signal, (21 is the buffer circuit (
1) A voltage ratio soft comparator that compares the signal vt voltage of the D/A converter +51 (31 is a successive ratio soft register that stores the signal of the voltage ratio soft comparator 121, (41 is a reference voltage generation circuit, ( 51 is the reference voltage generation circuit (4
The O/A converter (6) which inputs the voltage of the successive approximation register (31) and generates an analog voltage corresponding to the data of the successive approximation register (31) is a timing circuit which controls the timing of the above operation;
) is a register for accumulating the A/D conversion value that is the output of the successive approximation register (3), and Da is the register (
This is the output value of 71.

〔発明が解決しようとする間順点〕[While the invention is trying to solve the problem]

上記櫓成によると人/D変換装置の計測精度はD/A変
換器そのものの分解能によってのみ回路の分解能が決定
されるため、計測精度を向上させるためKはより良い分
解能を有したD/A変換器が必要となり価格の増加を招
く問題点があった。
According to the above-mentioned Yasei, the measurement accuracy of a human/D converter is determined only by the resolution of the D/A converter itself, so in order to improve measurement accuracy, K is a D/A converter with better resolution. There was a problem in that a converter was required, leading to an increase in price.

この発明は上記のような間和点を解決するためになされ
たものでD/A変換装置を変更することなく人/D f
楔装置の分解能を向上させることを目的とする。
This invention was made in order to solve the above-mentioned problem of interpolation, and it is possible to convert the D/D f without changing the D/A converter.
The purpose is to improve the resolution of the wedge device.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るA/D変換装珈は従来のA/D変撓値を
得たときのD/A変換器出力電圧をサンプル・ホールド
回路にて保持し、その値と板針画信号の差分を増幅し再
度A/D変換することにより、従来のA/D変換変換対
し9wrたにA/D変換した値を付加し人/D変換装置
の人/D変換精度向上を図ったものである。
The A/D conversion device according to the present invention holds the D/A converter output voltage when obtaining the conventional A/D conversion value in a sample/hold circuit, and calculates the difference between that value and the plate needle image signal. By amplifying the signal and A/D converting it again, the A/D converted value is added to the conventional A/D conversion by 9wr, thereby improving the human/D conversion accuracy of the human/D conversion device. .

〔作用〕[Effect]

この発明における差動増幅器は、サンプル・ホールドに
よりホールドされたD/A変換器出力電圧と、バッファ
回路の出力電圧の差分をとりその誤差電圧増幅すること
により、今まで1ビツト内に入っていた誤差電圧を再度
A/D 変換可能な状態としこれをA/D変換すること
により倉たに得たA/D変換値を従来の人/D変換価に
付加し人/D変換精度を向上させる。
The differential amplifier in this invention takes the difference between the D/A converter output voltage held by sample and hold and the output voltage of the buffer circuit, and amplifies the error voltage, which is within 1 bit. The error voltage is made A/D convertible again, and the A/D conversion value obtained by A/D conversion is added to the conventional human/D conversion value to improve human/D conversion accuracy. .

〔実施例〕〔Example〕

第1図はこの発明の一実施例を示す構成図である。 FIG. 1 is a block diagram showing an embodiment of the present invention.

図においてftl〜(71は上記従来回路と全く同一の
ものである。
In the figure, ftl~(71 is exactly the same as the above-mentioned conventional circuit.

上記第1図においてサンプル・ホールド(8)は従来の
回路構成によって得られる人/D変換値Daを出力した
時のD/A変換器(51の出力電圧をタイミング回路(
6)の1filJ(ii4]によりサンプル・ホールド
する。上記サンプルホールド(8+にてホールドされた
電圧は、バッファ回路(11の出力電圧とともに差動増
幅器191へ入力される。上記差動増幅器(9)では。
In FIG. 1 above, the sample/hold (8) is the timing circuit (8) that outputs the output voltage of the D/A converter (51) when it outputs the human/D conversion value Da obtained by the conventional circuit configuration.
6) is sampled and held by 1filJ (ii4). The voltage held by the sample and hold (8+) is input to the differential amplifier 191 together with the output voltage of the buffer circuit (11). Well then.

上記サンプル・ホールド(8)とバッファ回路(り)差
分電圧だけを増幅する。この場合の増幅率は1ビツトの
分解能内に入っている誤差電圧を再度A/D変換できる
値にまで増幅する。
Only the difference voltage between the sample and hold circuit (8) and the buffer circuit (ri) is amplified. In this case, the amplification factor is such that the error voltage within the resolution of 1 bit is amplified to a value that allows A/D conversion again.

上記バッファ回路(1)の出力と上記差動増幅器(91
の出力をタイミング回路(6)により選択するスイッチ
回路6Oでは、従来の回路構成によるA/D 変換を実
施する場合バッファ回路(11を選択し9本発明による
動作時では上記差動増幅器+9+を選択する。
The output of the buffer circuit (1) and the differential amplifier (91)
The switch circuit 6O selects the output of the buffer circuit (11) using the timing circuit (6), when performing A/D conversion using the conventional circuit configuration, selects the buffer circuit (11), and when operating according to the present invention, selects the differential amplifier +9+. do.

上記差動増幅器(9)を選択した場合、差動増幅器(9
)で設定された増幅率により計測範囲が決定されその値
が従来の回路動作によるA/D変換と同じ課程で変換デ
ータを得る。この変換データは従来の回路動作の最下位
ビットに付加されるため1人/D変換装置としての計測
精度を向上させることができる。また差動増幅器(91
の増幅率はD/A変換器151の分解能の111まで可
変可能である。
If the above differential amplifier (9) is selected, the differential amplifier (9)
) The measurement range is determined by the amplification factor set in ), and the converted data is obtained in the same process as A/D conversion by conventional circuit operation. Since this conversion data is added to the least significant bit of the conventional circuit operation, it is possible to improve the measurement accuracy as a one-person/D conversion device. Also, a differential amplifier (91
The amplification factor can be varied up to 111, which is the resolution of the D/A converter 151.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、差動増幅器で増幅する
増幅率を自由に設定することにより従来のA/D変換装
置に対し、A/D変換精度を向上させることができる効
果がある。
As described above, according to the present invention, by freely setting the amplification factor of the differential amplifier, the A/D conversion accuracy can be improved compared to the conventional A/D conversion device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す回路の構成図、第2
図は従来の回路を示す構成図である。 図において(1)はバッファ回路、(21は電圧比較型
コンパレータ、(3)は逐次比較レジスタ、C41は基
準電圧発生回路、(5)はD/A変換器、(6)はタイ
ミング回路、C7)はレジスタ、(8)はサンプル・ホ
ールド。 +91は差動増幅器、α・はスイッチ回路である。 なお9図中同一符号は同一または相当部分を示すO
FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a configuration diagram showing a conventional circuit. In the figure, (1) is a buffer circuit, (21 is a voltage comparison type comparator, (3) is a successive approximation register, C41 is a reference voltage generation circuit, (5) is a D/A converter, (6) is a timing circuit, and C7 is a reference voltage generation circuit. ) is a register, and (8) is a sample/hold. +91 is a differential amplifier, and α· is a switch circuit. Note that the same symbols in Figure 9 indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 外部より与えられるアナログ信号をインピーダンス変換
するバッファ回路と、上記バッファ回路の出力をD/A
変換器出力電圧と電圧比較する電圧比較型コンパレータ
と、上記電圧比較型コンパレータの比較結果を入力する
とともにタイミング回路によつて動作速度を制御される
逐次比較レジスタと、上記逐次比較レジスタの出力をア
ナログ電圧に変換するD/A変換器と、上記D/A変換
器に基準電圧を供給する基準電圧発生回路と、基準電圧
供給時のA/D変換値を蓄積するレジスタとから構成さ
れるA/D変換装置において、上記A/D変換値を得た
ときのD/A変換器出力電圧をタイミング回路の制御に
よりホールドするサンプル・ホールドと上記サンプル・
ホールドの出力電圧とバッファ回路出力を差分だけ増幅
する差動増幅器と、上記バッファ回路出力と上記差動増
幅器出力をタイミング回路の制御により切り換えるスイ
ッチ回路において、上記バッファ回路からのアナログ電
圧をA/D変換した値と上記差動増幅器からのアナログ
電圧をA/D変換した値を併用することにより計測精度
の向上を図つたことを特徴とするA/D変換装置。
A buffer circuit that converts the impedance of an analog signal given from the outside, and a D/A converter for the output of the buffer circuit.
A voltage comparison type comparator that compares the voltage with the converter output voltage, a successive approximation register that inputs the comparison result of the voltage comparison type comparator and whose operating speed is controlled by a timing circuit, and an analog output of the successive approximation register. The A/D converter is composed of a D/A converter that converts into a voltage, a reference voltage generation circuit that supplies a reference voltage to the D/A converter, and a register that stores A/D converted values when the reference voltage is supplied. In the D converter, there is a sample/hold for holding the D/A converter output voltage when the above A/D converted value is obtained under the control of a timing circuit, and the above sample/hold.
A differential amplifier that amplifies the difference between the hold output voltage and the buffer circuit output, and a switch circuit that switches the buffer circuit output and the differential amplifier output under the control of a timing circuit, the analog voltage from the buffer circuit is converted into an A/D converter. An A/D conversion device characterized in that measurement accuracy is improved by using a converted value and a value obtained by A/D converting the analog voltage from the differential amplifier.
JP554987A 1987-01-13 1987-01-13 Analog/digital converter Pending JPS63173420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP554987A JPS63173420A (en) 1987-01-13 1987-01-13 Analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP554987A JPS63173420A (en) 1987-01-13 1987-01-13 Analog/digital converter

Publications (1)

Publication Number Publication Date
JPS63173420A true JPS63173420A (en) 1988-07-18

Family

ID=11614270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP554987A Pending JPS63173420A (en) 1987-01-13 1987-01-13 Analog/digital converter

Country Status (1)

Country Link
JP (1) JPS63173420A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0593643A (en) * 1991-10-02 1993-04-16 Rinnai Corp Liquid-level detecting apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0593643A (en) * 1991-10-02 1993-04-16 Rinnai Corp Liquid-level detecting apparatus

Similar Documents

Publication Publication Date Title
JPS63173420A (en) Analog/digital converter
US4924224A (en) High-accuracy A/D converter
JPS61199199A (en) Analog input unit
JPS58172560A (en) Linearity measurement of d/a converter
JPS6121524A (en) High speed data collecting system
JPS62204617A (en) High resolution analog-digital converter
US6172627B1 (en) Dynamic digital to synchro converter
JPH09181604A (en) Semiconductor integrated circuit device and its noise reduction method
US4584560A (en) Floating point digitizer
JPS6029028A (en) High speed analog-digital converting circuit
JP3498088B2 (en) Integrated circuit
JP3945389B2 (en) Time-voltage converter and method
JPH0712852A (en) Waveform measuring equipment having waveform generating function
JP3036263B2 (en) AGC circuit
JPS6331224A (en) Accuracy improving system for a/d conversion sample value
JPS6210659Y2 (en)
JP2006352743A (en) A/d conversion apparatus
JPH0983363A (en) A/d converting circuit
JPS605396Y2 (en) analog output circuit
JPS63530U (en)
SU661269A1 (en) Temperature measuring device
SU769308A1 (en) Method and device for measuring displacements
JPH0528832Y2 (en)
JPH0256115A (en) A/d converter
CN114978184A (en) Signal processing circuit and method for improving AD resolution