JP2006352743A - A/d conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D conversion apparatus whose resolution is improved. <P>SOLUTION: A differential amplifier 4 amplifies, with a predetermined gain G, a difference between an analog value resulting from converting an analog value that becomes the object of A/D conversion processing, into a digital value by an A/D converter 2 and then D/A-converting the digital value by a D/A converter 3 and an analog value sampled/held by a sample/hold circuit 1. The output of the differential amplifier 4 is converted into a digital value by an A/D converter 5 and then divided with the predetermined gain G in a divider 6. An adder 7 adds the output of the A/D converter 2 and the division result of the divider 6 and outputs an addition result as the A/D conversion processing result of an A/D conversion apparatus 100. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an A / D conversion device that converts analog data into digital data.

  2. Description of the Related Art Conventionally, an A / D converter that detects a current flowing through an electric motor with a current sensor and converts the detected current into a digital signal is known (see Patent Document 1).

JP 2003-255006 A

  However, in the conventional A / D conversion device, if the resolution is to be increased, it is necessary to improve the performance of the A / D converter to be used. However, the A / D converter having a high resolution is expensive. There is.

(1) An A / D conversion device according to the present invention includes a sample hold means for sample-holding an analog value to be subjected to A / D conversion processing, and a first A for converting the sampled analog value into a digital value. / D conversion means, a D / A conversion means for converting a digital value output from the first A / D conversion means to an analog value, an analog value output from the D / A conversion means, and a sample hold means Differential amplification means for amplifying the difference from the analog value sampled and held with a predetermined gain; second A / D conversion means for converting the analog value output from the differential amplification means into a digital value; Division means for dividing a digital value output from the A / D conversion means by a predetermined gain, a digital value output from the first A / D conversion means, and a digital value that is a result of division by the division means By adding the value, characterized in that the result of the addition an adding means for outputting a result of the A / D conversion process.
(2) An A / D conversion device according to the present invention includes a sample hold means for sample-holding an analog value to be subjected to A / D conversion processing, and a first A for converting the sampled analog value into a digital value. / D conversion means, D / A conversion means for converting a digital value output from the first A / D conversion means into an analog value, an analog value output from the D / A conversion means, and the sample hold means Differential amplification means for amplifying the difference from the analog value sampled and held by a gain of 2 ^m (m is a natural number), and a second A for converting the analog value output from the differential amplification means into a digital value The result obtained by arranging the digital value output from the / D conversion means and the first A / D conversion means in the integer part and the digital value output from the second A / D conversion means in the decimal part , / Characterized in that it comprises a data processing means for outputting as a result of D conversion process.

  According to the A / D conversion device of the present invention, it is possible to realize a resolution higher than the resolution of the A / D conversion means.

-First embodiment-
FIG. 1 is a diagram illustrating a block configuration of an A / D conversion apparatus 100 according to the first embodiment. The A / D conversion device according to the first embodiment includes a sample hold circuit 1, a first A / D converter 2, a D / A converter 3, a differential amplifier 4, and a second A / D converter. 5, a divider 6, an adder 7, and a control signal generator 8.

  The voltage value detected by the voltage sensor 10 is multiplied by 1 / K according to the maximum input voltage of the A / D converter 2 and is input to the sample hold circuit 1 of the A / D converter 100. For example, when the maximum value of the voltage measured by the voltage sensor 10 is 800 V and the maximum input voltage of the A / D converter 2 is 5 V, K = 800/5.

  The sample hold circuit 1 samples and holds the input voltage value based on the control signal input from the control signal generator 8. The A / D converter 2 is an 8-bit A / D converter, and the maximum input voltage is 5V. The A / D converter 2 converts the voltage value (analog value) sampled and held by the sample hold circuit 1 into a digital value. The D / A converter 3 is an 8-bit D / A converter, and converts the digital value output from the A / D converter 2 into an analog value.

  The differential amplifier 4 amplifies the difference between the voltage value (analog value) sampled and held by the sample hold circuit 1 and the analog value output from the D / A converter 3 with a gain G, and outputs the result. Here, G = 200. The second A / D converter 5 is an 8-bit A / D converter having the same performance as that of the first A / D converter 2, and the maximum input voltage is 5V. The A / D converter 5 converts the analog value output from the differential amplifier 4 into a digital value.

  The divider 6 divides the digital value output from the A / D converter 5 by the gain G. The adder 7 adds the output value of the A / D converter 2 and the output value of the divider 6. The addition result of the adder 7 is output as an output value of the A / D converter 100, multiplied by K by a microcomputer or the like, and becomes a voltage reading value.

  FIG. 2 is a timing chart of each control signal output from the control signal generator 8. The sample hold circuit 1 samples and holds the input voltage based on the signal input via the control signal line 81 at the timing t1. The A / D converter 2 converts the voltage value output from the sample hold circuit 1 into a digital value based on a signal input via the control signal line 82 at timing t2.

  The D / A converter 3 converts the digital value converted by the A / D converter 2 into an analog value based on a signal input via the control signal line 83 at timing t3. The A / D converter 5 converts the analog value output from the differential amplifier 4 into a digital value based on a signal input via the control signal line 84 at timing t4. Thereafter, each process is repeatedly performed at the timing described above.

The resolution of the A / D conversion apparatus 100 will be described with reference to FIGS. FIG. 3 is a diagram showing the relationship between the voltage Vin input to the A / D converter 2 and the output voltage Vout of the A / D converter 2. When the input voltage of the A / D converter 2 is Va and the output voltage after A / D conversion is Vb, the quantization error Vc due to the A / D conversion process is expressed by the following equation (1).
Vc = Va-Vb (1)
However, the quantization error Vc is 0 or more and is smaller than the resolution ΔV1 of the A / D converter 2.

  The differential amplifier 4 is a value obtained by amplifying the difference between the voltage Va input to the A / D converter 2 and the voltage Vb obtained by converting the output voltage (digital value) of the A / D converter 2 into an analog value with a gain G. That is, G · (Va−Vb) = G · Vc is output. Therefore, the input voltage of the A / D converter 5 is G · Vc.

FIG. 4 is a diagram showing the relationship between the voltage Vin input to the A / D converter 5 and the output voltage Vout of the A / D converter 5. As shown in FIG. 4, when the output voltage when the input voltage of the A / D converter 5 is G · Vc is Vd, the quantization error Ve due to the A / D conversion process is expressed by the following equation (2). The
Ve = G · Vc−Vd (2)
However, the quantization error Ve is 0 or more and a value smaller than the resolution ΔV2 (= ΔV1) of the A / D converter 5.

Solving equation (2) with respect to Vc leads to the following equation (3).
Vc = Vd / G + Ve / G (3)

The output voltage Vd of the A / D converter 5 is divided by the gain G in the divider 6. That is, the output voltage of the divider 6 is Vd / G. The adder 7 outputs a value (Vb + Vd / G) obtained by adding the output voltage Vb of the A / D converter 2 and the output voltage Vd / G of the divider 6. Here, from the expression (1), the input voltage Va of the A / D conversion apparatus 100 is expressed by the following expression (4). Therefore, the quantization error of the A / D conversion processing by the A / D conversion apparatus 100 is Is represented by the following equation (5).
Va = Vb + Vc (4)
Quantization error = Va− (Vb + Vd / G) = (Vb + Vc) − (Vb + Vd / G)
= Vc-Vd / G = (Vd / G + Ve / G) -Vd / G
= Ve / G (5)

As described above, since the relationship of 0 ≦ Ve <ΔV1 holds, the magnitude of the quantization error Ve / G in the A / D conversion process of the A / D conversion apparatus 100 is defined by the following equation (6). .
0 ≦ Ve / G <ΔV1 / G (6)

  That is, the maximum quantization error of the A / D conversion process by the A / D conversion apparatus 100 is ΔV1 / G, and the maximum value ΔV1 / G of the quantization error is the resolution of the A / D conversion apparatus 100. Here, since the maximum value of the quantization error when only one A / D converter is provided, that is, the resolution is ΔV1, according to the A / D conversion apparatus 100 of the first embodiment, the resolution Can be reduced to 1 / G.

Here, the resolution is calculated using specific numerical values. The resolution of the 8-bit A / D converter 2 with a maximum input voltage of 5V is 5/2 ⁸ (V).
5/2 ⁸ × K = 800/256 = 3.125 (V)
It becomes. This is the resolution (800 V conversion) of a conventional A / D converter having only one A / D converter.

On the other hand, since the resolution of the A / D conversion device 100 in the first embodiment is 1 / G of the resolution of the A / D converters 2 and 5,
3.125 / 200 = 15.6 (mV)
It becomes.

Here, in a conventional A / D converter having only one A / D converter, the resolution (converted to 800 V) when a 16-bit A / D converter is used is as follows:
^{5/2 16 × K = 800/2} 16 = 12.2 (mV)
It becomes. That is, according to the A / D converter in the first embodiment, the A / D converter using the 8-bit A / D converter is equivalent to the A / D converter using the expensive 16-bit converter. Resolution can be obtained.

The gain G is determined based on the resolution of the first A / D converter 2 and the maximum input voltage of the second A / D converter 5. As described above, since the resolution of the A / D converter 2 is 5/2 ⁸ (V), the voltage input to the A / D converter 5 is a value smaller than 5/2 ⁸ × G (V). It becomes. Gain G must be set so that the input voltage of the A / D converter 5 is smaller than 5V is the maximum input voltage, here, it is necessary to set the gain G 2 ⁸ the following values. As described above, according to the A / D conversion device 100 in the first embodiment, the resolution is set to 1 / G with respect to the resolution of the A / D conversion device using one A / D converter. since it is, the gain G is at 2 ⁸ the following values, it is preferable to set as high as possible value.

  According to the A / D conversion device in the first embodiment, A / D conversion processing is performed according to the following procedure. The sample and hold circuit 1 samples and holds an analog value to be subjected to A / D conversion processing, and the sampled and held analog value is converted to a digital value by the A / D converter 2. The A / D converted digital value is converted into an analog value by the D / A converter 3. The differential amplifier 4 amplifies the difference between the analog value sampled and held by the sample hold circuit 1 and the analog value D / A converted by the D / A converter 3 with a predetermined gain G. The output value of the differential amplifier 4 is converted into a digital value by the A / D converter 5 and then divided by a predetermined gain G in the divider 6. The adder 7 adds the output value of the A / D converter 2 and the output value of the divider 6 and outputs the result as an output value of the A / D converter 100. Thereby, even if it does not use a highly accurate A / D converter, the resolution equivalent to the case where a highly accurate A / D converter is used can be obtained. In the above-described embodiment, an 8-bit converter can be used to obtain the same resolution as when a 16-bit converter is used. That is, an A / D conversion device having a wide dynamic range and high resolution can be provided without using a high accuracy A / D converter.

-Second Embodiment-
FIG. 5 is a diagram illustrating a block configuration of the A / D conversion device 200 according to the second embodiment. The difference from the configuration of the A / D conversion device 100 in the first embodiment shown in FIG. 1 is that a data adder 20 is provided instead of the divider 6 and the adder 7, and the differential amplifier 4. Is the value of the gain G.

The processing performed by each of the sample hold circuit 1, the A / D converter 2, the D / A converter 3, the differential amplifier 4, and the A / D converter 5 is the case of the A / D converter 100 according to the first embodiment. It is the same. However, the value of the gain G of the differential amplifier 4 is 2 ^m when the A / D converter 5 is an m-bit converter. For example, if the A / D converter 5 is an 8-bit converter, the value of the gain G is set to ^{2 8.}

In the A / D conversion device according to the first embodiment, the output value of the A / D conversion device 100, that is, the output value of the adder 7, is the output value of the A / D converter 2, Vb, and the A / D converter 5 When the output value of Vd is Vd, it was Vb + Vd / G. If the value of the gain G is 2 ^m , the output of the A / D converter is Vb + Vd / 2 ^m .

In the A / D conversion device according to the second embodiment, the data adder 20 outputs the output of the A / D converter 5 at a position below the decimal point with respect to the output value (digital value) Vb of the A / D converter 2. The values (digital values) Vd are combined and output. The reason why the value obtained by combining the output value of the A / D converter 5 at the position below the decimal point with respect to the output value of the A / D converter 2 becomes the same value as (Vb + Vd / 2 ^m ) will be described below.

In the binary system, dividing the digital value Vd by 2 ^m is equivalent to moving the decimal point position to the left by m bits with respect to the digital value Vd. For example, it is assumed that the m-bit digital value Vd ₍₂₎ output from the A / D converter 5 is a value represented by the following equation (7).
Vd ₍₂₎ = a _m-1 a _m-2 ... A ₂ a ₁ a ₀ (7)
However, a _{m-1 to} a ₀ are values of 0 or 1, respectively.

When the digital value Vd ₍₂₎ expressed in binary notation is expressed in decimal notation, the following equation (8) is obtained.
Vd ₍₁₀₎ = a _m−1 × 2 ^m−1 + a _m−2 × 2 ^m−2 +... + A ₂ × 2 ² + a ₁ × 2 ¹ + a ₀ × 2 ⁰ (8)
Therefore, when Vd ₍₁₀₎ expressed in decimal notation is divided by 2 ^m , the following equation (9) is obtained.
Vd ₍₁₀₎ / 2 ^m
= A _m-1 × 2 ⁻¹ + a _m−2 × 2 ⁻² +... + A ₂ × 2 ^2-m + a ₁ × 2 ^1-m + a ₀ × 2 ^−m (9)
When the value represented by Equation (9) is expressed in binary, the numbers after the decimal point are a _m-1 a _m-2 ... A ₂ a ₁ a ₀ . That is, the digital value obtained by dividing the digital value Vd by 2 ^m is a value obtained by moving the decimal point position to the left by m bits with respect to the digital value Vd.

As described above, the value obtained by arranging the output value Vb of the A / D converter 2 in the integer part and the output value Vd of the A / D converter 5 in the decimal part is the same value as (Vb + Vd / 2 ^m ). That is, according to the A / D conversion device in the second embodiment, the divider can be omitted from the configuration of the A / D conversion device in the first embodiment shown in FIG. In FIG. 5, the addition method in the data adder 20 is shown assuming that the A / D converter 2 is an n-bit converter and the A / D converter 5 is an m-bit converter.

According to the A / D conversion device in the second embodiment, A / D conversion processing is performed according to the following procedure. The sample and hold circuit 1 samples and holds an analog value to be subjected to A / D conversion processing, and the sampled and held analog value is converted to a digital value by the A / D converter 2. The A / D converted digital value is converted into an analog value by the D / A converter 3. The differential amplifier 4 amplifies the difference between the analog value sampled and held by the sample hold circuit 1 and the analog value D / A converted by the D / A converter 3 with a gain of 2 ^m . The output value of the differential amplifier 4 is converted into a digital value by the A / D converter 5. In the data adder 20, the output value of the A / D converter 2 is converted into an integer part and the output value of the A / D converter 5 is converted into a decimal number. And output as a result of the A / D conversion process of the A / D conversion device 200. As a result, similar to the A / D converter in the first embodiment, even if the high-precision A / D converters 2 and 5 are not used, the same resolution as when the high-precision A / D converter is used. Can be obtained. In addition, since the division operation is not performed, the operation can be speeded up.

  The present invention is not limited to the embodiments described above. For example, as described with reference to FIG. 2, since the A / D converters 2 and 5 perform A / D conversion processing at different timings, only one A / D converter is provided, and the A / D converter 2 and It is also possible to perform the A / D conversion process performed by each of the 5 by a single A / D converter. In this case, a multiplexer for switching an analog value input to one A / D converter is provided, and the A / D conversion performed by the A / D converters 2 and 5 at the times t2 and t4 in FIG. 2, respectively. The multiplexer switching process may be controlled so that the process is performed. According to this method, since only one A / D converter is required, the cost of the entire apparatus can be reduced.

  As an example of the analog value to be subjected to the A / D conversion process, the voltage value has been described. However, the analog value to be subjected to the A / D conversion process is not limited to the voltage value.

  The correspondence between the constituent elements of the claims and the constituent elements of the first and second embodiments is as follows. That is, the sample hold circuit 1 is sample hold means, the A / D converter 2 is first A / D conversion means, the D / A converter 3 is D / A conversion means, and the differential amplifier 4 is differential amplification means. The A / D converter 5 constitutes second A / D conversion means, the divider 6 constitutes division means, the adder 7 constitutes addition means, and the data adder 20 constitutes data processing means. In addition, the above description is an example to the last, and when interpreting invention, it is not limited to the correspondence of the component of said embodiment and the component of this invention at all.

The figure which shows the block configuration of the A / D converter in 1st Embodiment. The figure which shows the timing chart of each control signal output from a control signal generator The figure which shows the relationship between the voltage input into a 1st A / D converter, and the output voltage of a 1st A / D converter The figure which shows the relationship between the voltage input into a 2nd A / D converter, and the output voltage of a 2nd A / D converter The figure which shows the block structure of the A / D converter in 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Sample hold circuit, 2 ... 1st A / D converter, 3 ... D / A converter, 4 ... Differential amplifier, 5 ... 2nd A / D converter, 6 ... Divider, 7 ... Adder, 8 ... Control signal generator, 20 ... Data adder, 100, 200 ... A / D converter

Claims (3)

Sample-and-hold means for sample-holding analog values to be subjected to A / D conversion processing;
First A / D conversion means for converting an analog value sampled and held by the sample and hold means into a digital value;
D / A conversion means for converting a digital value output from the first A / D conversion means into an analog value;
Differential amplification means for amplifying a difference between an analog value output from the D / A conversion means and an analog value sampled and held by the sample hold means with a predetermined gain;
Second A / D conversion means for converting an analog value output from the differential amplification means into a digital value;
Division means for dividing a digital value output from the second A / D conversion means by the predetermined gain;
Addition means for adding the digital value output from the first A / D conversion means and the digital value which is the division result of the division means, and outputting the addition result as a result of the A / D conversion processing; An A / D converter characterized by the above. Sample-and-hold means for sample-holding analog values to be subjected to A / D conversion processing;
First A / D conversion means for converting an analog value sampled and held by the sample and hold means into a digital value;
D / A conversion means for converting a digital value output from the first A / D conversion means into an analog value;
The difference between the analog value output from the D / A conversion means and the analog value sampled and held by the sample hold means is 2 ^m (m is the number of bits of the second A / D conversion means). Differential amplification means for amplifying with gain;
Second A / D conversion means for converting an analog value output from the differential amplification means into a digital value;
The result obtained by arranging the digital value output from the first A / D conversion means in the integer part and the digital value output from the second A / D conversion means in the decimal part is represented by A / D. An A / D conversion apparatus comprising: data processing means for outputting as a result of the conversion process. The A / D conversion device according to claim 1 or 2,
The first A / D conversion means and the second A / D conversion means are composed of one A / D conversion means,
Input value switching means for switching an analog value input to the A / D conversion means;
The input value so that the A / D conversion process performed by each of the first A / D conversion unit and the second A / D conversion unit is performed at different timings by the one A / D conversion unit. The A / D conversion apparatus further comprising switching timing control means for controlling input value switching processing by the switching means.

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