JPS63173373A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPS63173373A JPS63173373A JP668187A JP668187A JPS63173373A JP S63173373 A JPS63173373 A JP S63173373A JP 668187 A JP668187 A JP 668187A JP 668187 A JP668187 A JP 668187A JP S63173373 A JPS63173373 A JP S63173373A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- layer
- impurity layer
- resistance
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 abstract description 36
- 230000015556 catabolic process Effects 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000002344 surface layer Substances 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果１〜ランジスタに関し、特に高耐圧、
低オン抵抗の縦型の電界効果トランジスタに関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to field effects 1 to transistors, and in particular to high breakdown voltage,
This invention relates to a vertical field effect transistor with low on-resistance.
従来、縦型の電界効果トランジスタ（以下ＦＥＴと称ず
）を、高耐圧化するには、半導体層からなるドレインの
比抵抗を大きくしかつその半導体層を厚くする方法をと
り、しかもベースを深くまで形成すると共にフィールド
プレートやフィールドリング等を能動領域の周辺部に設
けて電界の集中を緩和していた。Conventionally, in order to increase the breakdown voltage of vertical field effect transistors (hereinafter referred to as FETs), the method of increasing the specific resistance of the drain consisting of a semiconductor layer and thickening the semiconductor layer was taken, as well as making the base deeper. At the same time, field plates, field rings, etc. were provided around the active region to alleviate the concentration of electric field.
第３図は従来のＦＥＴの一例の断面図である。FIG. 3 is a sectional view of an example of a conventional FET.
この従来例は、裏面にドレイン電極１２を有するｎ＋型
型部濃度シリコン基板１上のｎ−型低濃度の半導体層か
らなるドレイン２の表面にｐ型のベース６とベース６の
表面のｎ＋型型部濃度ソース７とソース７の間のベース
６及びドレイン２の表面上にゲーＩ・絶縁膜を介して設
けたゲーＩ〜８とからなる能動領域と、その周囲を囲む
ｐ型の拡散層５からなるフィールドリンクと、一番外側
のフィールドリング５に接続したフィールドプレー）１
０と、絶縁膜１０に開孔した窓を通してソース７及びベ
ース６と接続したソース電極１１とで構成されている。In this conventional example, a p-type base 6 is formed on the surface of a drain 2 made of an n-type low concentration semiconductor layer on an n+ type doped silicon substrate 1 having a drain electrode 12 on the back surface, and an n+ type base 6 is formed on the surface of the base 6. An active region consisting of a gate I and gates I to 8 provided through an insulating film on the surfaces of the base 6 and the drain 2 between the source 7 and the source 7, and a p-type diffusion layer surrounding the active region. Field link consisting of 5 and field play connected to the outermost field ring 5) 1
0, and a source electrode 11 connected to the source 7 and base 6 through a window formed in an insulating film 10.
上述した従来技術の電界効果１〜ランジスタでは、高耐
圧化のために半導体層からなるドレインの比抵抗を大き
くしなければならないので、より一層高耐圧化を図ろう
とするとドレイン抵抗が増してオン抵抗が大きくなると
共に電力損失が増大し電気的特性を損うという欠点があ
る。In the above-mentioned conventional field effect transistors, the specific resistance of the drain made of a semiconductor layer must be increased in order to achieve a high withstand voltage. Therefore, if an attempt is made to achieve an even higher withstand voltage, the drain resistance increases and the on-resistance increases. There is a drawback that as the value increases, power loss increases and electrical characteristics are impaired.
本発明の目的は、高耐圧でしかも低オン抵抗のＦＥＴを
提供することにある。An object of the present invention is to provide an FET with high breakdown voltage and low on-resistance.
本発明の電界効果Ｉ・ランジスタは、−導電型低濃度の
半導体層からなるドレイン表面に設けた所定のパターン
の前記ドレインより高濃度の一導電型の第１の不純物層
と、前記ドレイン表面の前記第１の不純物層の周囲に設
けた前記ドレインより低濃度の一導電型の第２の不純物
層と、前記第１の不純物層表面に設けた反対導電型のベ
ースと、該ベース表面に設けた一導電型高濃度のソース
と、前記ベース表面の前記ソース及び前記不純物層に挟
まれた部分の上にゲート絶縁膜を介して設けたゲートと
を少くとも有して成る。The field effect I transistor of the present invention includes a first impurity layer of one conductivity type with a higher concentration than the drain in a predetermined pattern provided on the drain surface made of a low concentration semiconductor layer of the negative conductivity type, and a first impurity layer of one conductivity type with a higher concentration than the drain, and a second impurity layer of one conductivity type with a lower concentration than the drain provided around the first impurity layer; a base of an opposite conductivity type provided on the surface of the first impurity layer; and a second impurity layer provided on the surface of the base. and a gate provided on a portion of the base surface sandwiched between the source and the impurity layer with a gate insulating film interposed therebetween.
次に、本発明の一実施例について図面を参照して説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
この実施例は、裏面にドレイン電極１２を有するｎ＋型
型温濃度シリコン基板１上のｎ−型低濃度の比抵抗が１
８ΩΩで厚さ４５μｍの半導体層からなるドレイン２表
面に比抵抗が６Ω艶程度のｎ型の不純物層４及びその周
辺の比抵抗３８Ω（至）で厚さ３μｍのｎ−一型低濃度
の不純物層３を設け、不純物層４表面にドレイン２に至
るｐ型のベース６、その表面のｎ＋型型温濃度ソース７
並びにソース７の間のベース６及び不純物層４の上にゲ
ート絶縁膜を介して設けたゲート８からなる能動領域を
設け、不純物層３表面にドレイン２に至るｐ型の拡散層
５からなるフィールドリングを設け、更に、一番外側の
フィールドリング５に接゛続したフィールドプレー１・
１０並びにソース７及びベース６と接続したソース電極
１１を設け、不純物層３及び４の境界が拡散層５からな
るフィールドリングと能動領域の間に設けた構造になっ
ている。ここで、不純物層４は、例えば、エネルギー１
２０ｋｅＶ、ドーズ量２ Ｘ １０１２ｃｍ２テｔ ウ
素をイオン注入し、１２００℃、６０分で押込み拡散を
行い、形成している。In this embodiment, the specific resistance of the n- type low concentration on the n+ type temperature doped silicon substrate 1 having the drain electrode 12 on the back surface is 1.
An n-type impurity layer 4 with a resistivity of about 6Ω on the surface of the drain 2 made of a semiconductor layer with a resistivity of 8ΩΩ and a thickness of 45μm, and a low concentration n-type impurity with a resistivity of 38Ω (maximum) and a thickness of 3μm around it. A layer 3 is provided, and a p-type base 6 extending to the drain 2 is formed on the surface of the impurity layer 4, and an n+-type temperature concentration source 7 on the surface thereof.
Furthermore, an active region consisting of a gate 8 provided through a gate insulating film is provided on the base 6 and the impurity layer 4 between the source 7, and a field consisting of a p-type diffusion layer 5 extending to the drain 2 on the surface of the impurity layer 3. A field play 1.
10 and a source electrode 11 connected to the source 7 and the base 6 are provided, and the boundary between the impurity layers 3 and 4 is provided between the field ring made of the diffusion layer 5 and the active region. Here, the impurity layer 4 has an energy of 1, for example.
It is formed by implanting ion implantation of 20 keV and dose of 2 x 1012 cm2 tet of uran, and performing intrusion diffusion at 1200°C for 60 minutes.
第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
この実施例は、不純物層３及び４が、一番内側のｐ型の
拡散層５からなるフィールドリンクによって仕切られて
いる。In this embodiment, impurity layers 3 and 4 are separated by a field link consisting of an innermost p-type diffusion layer 5.
上述の構造のＦＥＴを試作した結果、５．５ｒｕｎ口の
半導体チップで耐圧５５０■、オン抵抗０．４２Ωのも
のが得られた。従来方法で試作したものは、耐圧５３０
Ｖでオン抵抗０．６Ωであったので耐圧、オン抵抗の両
方が改善された。As a result of fabricating a prototype FET with the above structure, a semiconductor chip with a 5.5-run opening and a withstand voltage of 550 cm and an on-resistance of 0.42 Ω were obtained. The prototype manufactured using the conventional method has a breakdown voltage of 530
Since the on-resistance was 0.6Ω at V, both the withstand voltage and on-resistance were improved.
以上述べた様に本発明は周辺部表面層の比抵抗を半導体
層からなるドレインの比抵抗より大きくすることにより
、外周部での空乏層の延びを大きくして耐圧を高くする
と共に能動領域の表面層の比抵抗をドレインの比抵抗よ
り小さくしてドレイン抵抗を下げ低オン抵抗で高耐圧の
電界効果トランジスタを提供できるという効果がある。As described above, the present invention makes the specific resistance of the surface layer of the peripheral part larger than the specific resistance of the drain made of the semiconductor layer, thereby increasing the extension of the depletion layer in the outer peripheral part, increasing the breakdown voltage, and increasing the breakdown voltage of the active region. The specific resistance of the surface layer is made smaller than the specific resistance of the drain, thereby reducing the drain resistance and providing a field effect transistor with low on-resistance and high breakdown voltage.
又、能動領域表面の比抵抗を小さくすることによって更
にパターンを微細化してパターン密度を上げゲート幅を
増やして性能を向上することができるという効果もある
。Further, by reducing the specific resistance of the surface of the active region, it is possible to further miniaturize the pattern, increase the pattern density, and increase the gate width, thereby improving performance.
第１及び第２図はそれぞれ本発明の第１及び第２の実施
例の断面図、第３図は従来のＦＥＴの一例の断面図であ
る。
１・・・シリコン基板、２・・・ドレイン、３，４・・
・不鈍物層、５・・・拡散層、６・・・ベース、７・・
・ソース、８・・・ゲート、９・・・絶縁膜、１０・・
・フィールドプレート、１１・・・ソース電極、１２・
・・ドレイン電極。
第 １ 回1 and 2 are sectional views of the first and second embodiments of the present invention, respectively, and FIG. 3 is a sectional view of an example of a conventional FET. 1... Silicon substrate, 2... Drain, 3, 4...
・Undull material layer, 5... Diffusion layer, 6... Base, 7...
・Source, 8... Gate, 9... Insulating film, 10...
・Field plate, 11...source electrode, 12・
...Drain electrode. 1st
Claims (1)
た所定のパターンの前記ドレインより高濃度の一導電型
の第１の不純物層と、前記ドレイン表面の前記第１の不
純物層の周囲に設けた前記ドレインより低濃度の一導電
型の第２の不純物層と、前記第１の不純物層表面に設け
た反対導電型のベースと、該ベース表面に設けた一導電
型高濃度のソースと、前記ベース表面の前記ソース及び
前記不純物層に挟まれた部分の上にゲート絶縁膜を介し
て設けたゲートとを少くとも有することを特徴とする電
界効果トランジスタ。A first impurity layer of one conductivity type with a higher concentration than the drain in a predetermined pattern provided on the surface of the drain made of a low concentration semiconductor layer of one conductivity type, and a first impurity layer of one conductivity type provided around the first impurity layer on the surface of the drain. a second impurity layer of one conductivity type with a lower concentration than the drain; a base of the opposite conductivity type provided on the surface of the first impurity layer; and a high concentration source of one conductivity type provided on the surface of the base; A field effect transistor comprising at least a gate provided on a portion of the base surface sandwiched between the source and the impurity layer with a gate insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP668187A JPS63173373A (en) | 1987-01-13 | 1987-01-13 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP668187A JPS63173373A (en) | 1987-01-13 | 1987-01-13 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63173373A true JPS63173373A (en) | 1988-07-16 |
Family
ID=11645106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP668187A Pending JPS63173373A (en) | 1987-01-13 | 1987-01-13 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63173373A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557127A (en) * | 1995-03-23 | 1996-09-17 | International Rectifier Corporation | Termination structure for mosgated device with reduced mask count and process for its manufacture |
| WO2002082553A1 (en) * | 2001-04-04 | 2002-10-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2009076930A (en) * | 2008-11-13 | 2009-04-09 | Mitsubishi Electric Corp | Semiconductor device |
| JP2009187994A (en) * | 2008-02-04 | 2009-08-20 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2018107477A (en) * | 2018-04-02 | 2018-07-05 | 三菱電機株式会社 | Power semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5553462A (en) * | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
| JPS5987871A (en) * | 1982-11-12 | 1984-05-21 | Hitachi Ltd | Insulated gate field effect semiconductor device |
-
1987
- 1987-01-13 JP JP668187A patent/JPS63173373A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5553462A (en) * | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
| JPS5987871A (en) * | 1982-11-12 | 1984-05-21 | Hitachi Ltd | Insulated gate field effect semiconductor device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557127A (en) * | 1995-03-23 | 1996-09-17 | International Rectifier Corporation | Termination structure for mosgated device with reduced mask count and process for its manufacture |
| WO2002082553A1 (en) * | 2001-04-04 | 2002-10-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JPWO2002082553A1 (en) * | 2001-04-04 | 2004-07-29 | 三菱電機株式会社 | Semiconductor device |
| US7180106B2 (en) | 2001-04-04 | 2007-02-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having enhanced di/dt tolerance and dV/dt tolerance |
| JP4837236B2 (en) * | 2001-04-04 | 2011-12-14 | 三菱電機株式会社 | Semiconductor device |
| US8183631B2 (en) | 2001-04-04 | 2012-05-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US8692323B2 (en) | 2001-04-04 | 2014-04-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with peripheral base region connected to main electrode |
| JP2009187994A (en) * | 2008-02-04 | 2009-08-20 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2009076930A (en) * | 2008-11-13 | 2009-04-09 | Mitsubishi Electric Corp | Semiconductor device |
| JP2018107477A (en) * | 2018-04-02 | 2018-07-05 | 三菱電機株式会社 | Power semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2585331B2 (en) | High breakdown voltage planar element | |
| JP2766239B2 (en) | High voltage semiconductor device | |
| JP2003298052A (en) | Semiconductor device | |
| JP2000183348A (en) | Mos gate power device | |
| JPH0783119B2 (en) | Field effect transistor | |
| JP3484690B2 (en) | Vertical field-effect transistor | |
| JPH0228270B2 (en) | ||
| JP3114069B2 (en) | Power element having double field plate structure | |
| JPH03262130A (en) | Manufacture of semiconductor element | |
| JPH0237777A (en) | Vertical type field-effect transistor | |
| JPS63173373A (en) | Field-effect transistor | |
| JPS58175872A (en) | Insulated gate field effect transistor | |
| JP3192857B2 (en) | Vertical MOS semiconductor device and method of manufacturing the same | |
| JP2926969B2 (en) | Semiconductor device having MIS type field effect transistor | |
| JP3885844B2 (en) | Semiconductor device | |
| JP3186298B2 (en) | Method for manufacturing MOS type semiconductor device | |
| JPH0758776B2 (en) | Composite semiconductor device | |
| JPH09129878A (en) | Semiconductor device | |
| JPH01132167A (en) | Semiconductor device | |
| JP4017763B2 (en) | Static induction transistor | |
| JP3301271B2 (en) | Horizontal power MOSFET | |
| JPS62229977A (en) | Manufacture of conduction-modulation mosfet | |
| JPS63177566A (en) | Field-effect transistor | |
| JPH11186402A (en) | Semiconductor device and manufacture of semiconductor | |
| JPH06268162A (en) | Semiconductor device and its manufacture |