JPS63172361A - Inter-processor communication system for multi-processor system - Google Patents

Abstract

PURPOSE:To reduce the load of a main processor in the inter-processor communication by giving an access to a private memory of the main processor from a subprocessor via a system bus. CONSTITUTION:A main processor 2, subprocessors 31-33, a common memory 12, and a bus controller 11 exclusive for a system bus are all connected to the bus 1. The processor 2 contains an instruction executing part 21 and a private memory 22. A specified area 221 of the memory 22 receives an access from the memory 2 via a signal line 200 as a starting area for subprocessors 31-33. While a specific area 222 receives accesses from subprocessors 31-33 connected to the bus 1 via a signal line 202 as an answer area through which the answers are given to the processor 2 from subprocessors 31-33. Each of those processors writes its own ID codes into the control flags 121 and 122 of the memory 12 and then uses areas 221 and 222.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inter-processor communication system in a multiprocessor system.

[Conventional technology]

By performing processing in parallel with multiple processors, the data processing capacity of the entire system can be improved. This type of system is called a multiprocessor system.

Multiprocessor systems require organic coupling between processors. In other words, data communication a between the preprocessors is regarded as essential J-, h. P. For example, Japanese Patent Application Laid-Open No. 60-3051
There is a publication.

[Problem that the invention seeks to solve]

It is known that the processing capacity of a multiprocessor system does not double even if the number of processors is doubled. This is a system management program that allows each processor to share common hardware resources and efficiently distribute the load of a single process.
That is, the operating system program must be executed by one processor, and the processing capacity of the entire system is limited by the execution speed of this operating system processor (hereinafter referred to as the main processor).

The above conventional technology does not take into account the overhead of the main processor as a 4J method for inter-processor communication, and the processing capacity of the system does not improve even if the number of processors is increased due to load concentration on the main processor due to the inter-processor communication overhead.↓ There was a problem.

An object of the present invention is to reduce the load on a main processor in inter-processor communication in order to improve the processing capacity of a multiprocessor system.

[Means for solving problems]

The above purpose is to exchange information between processors, i.e. from the main processor to another processor (called a sub-processor).
The startup information from the sub-processor to the main processor and the response information from the sub-processor to the main processor are transferred from the main processor both logically and physically.
Place it in a nearby memory.

- This can be achieved by shortening the access time from the L processor to the above information.

[Effect]

1: In order to make the exchange information between the processor and the sub-processor accessible from the main processor in a short access time, it is sufficient to place the exchange information on the private memory inside the main processor. In other words, the private memory of the main processor, which can be accessed from the main processor in a short access time, can also be accessed from the sub-processor via the system bus.

Access from the secondary processor to the private memory of the main processor does not need to occur in a short period of time since it does not contribute to the overhead of the main processor.

The above means can reduce the load on the main processor. However, if the main processor and sub-processor write and read from the same address at the same time, malfunctions may occur. Therefore, a common memory that does not belong to any processor is provided on the system bus, and a flag is placed on the common memory to indicate access rights to a specific area of private memory, so that only one processor can always access the specific area. The above-mentioned malfunction can be prevented by only having access.

A method of managing the above flags will be explained. A processor that requires a read or write operation, that is, access to the area, sets its own processor's I in the above flag.
Write the D code. However, if the ID code of another processor has already been written to that flag, the ID code will be written on top of it.
Overwriting the code is prohibited. If the flag is 0, writing the ID code is allowed. In this way, only the processor that has been able to write its own processor's ID code in the flag is allowed to access a specific area of the private memory of the main processor, and the processor that has completed the access clears the flag to 0.

By using the common memory management flag method described above, it is possible to prevent malfunctions due to contention between processors, that is, simultaneous access to specific areas of the driver 1 to memory.

However, this method does not prevent all malfunctions. The reason for this is that while one processor is reading the management flag, another processor may write it. Then, a certain processor reads the flag and determines whether it is 0, and if it is 0, I
While writing the D code, measures must be taken to prevent other processors from accessing the flag.

- The system bus is a hardware resource that is commonly used by multiple processors, and if one processor is using it, other processors cannot use it. Since the common memory does not belong to any processor and is connected to the system bus, all processors must access the common memory using the system bus. Therefore, if the above flag is O, the processor that needs to write its own processor's IL) code will:
By continuing to occupy the system bus until the processing is completed, contention for access to the flag can be prevented.

If set, other processors cannot access the storage device; flags used in this way are called semaphore flags. but.

The interlock using the semaphore flag is a software interlock means and cannot completely eliminate contention between accesses to the storage device by two processors. That is, between a read operation to test if the semaphore flag is set and a write operation to set it.

If other processors read or write to the flag, they will erroneously give more than one processor access to the storage device.

Therefore, it is necessary to implement in hardware a means that prevents other processors from accessing the semaphore flag while testing (reading) and setting (writing) the semaphore flag.

In conventional systems, in order to achieve the above hardware interlock, one processor continues to hold the exclusive right to the bus to which the storage device is connected during the test-setting of the semaphore flag, and other processors do not What is not passed on is done.

〔Example〕

FIG. 1 shows an overall configuration diagram of the present invention.

Main processor 2 is connected to system bus 1, signal line 201.2
02 and the secondary processors 31.32.33
are connected via signal lines 310, 320 and 330, respectively, and the common memory 12 is connected via a signal line 120.

System bus 1 is 1. Main processor 2 and sub processor 3
Only one of the four machines 1, 32, and 33 will be occupied and used. These occupation controls are performed by the bicon l-roller 11.

The main processor 2 includes an instruction execution section 21 and a private memory 22. private memory 2
2 can be accessed simultaneously from the instruction execution unit 21 via the signal line 200 and from other processors 31, 32, 33 connected to the system bus 1 via the signal line 202.

Specific area 221゜222 on plusbait memory 22
are reserved as an area for startup data from the main processor 2 to the sub-processor 31 and an area for response data from the sub-processor 31 to the main processor 2, respectively.

The common memory 12 has a management flag 121 in a startup data area 221 and a management flag 122 in a response data area 222.

A processor that uses the startup data area 221 and the processor area 222 has the management flag 122.
Please write your ID code on the card before use. However, when writing to the management flags 121 and 122, the flags are "
It is only allowed when the value is 0.

FIG. 2 shows the detailed configuration of the system bus 1. Since this figure is a diagram for explaining occupancy control of the system bus 1, the state of connection between the common memory 12 and the sub-processors 32 and 33 is omitted.

The system bus 1 has an address common line 104. Data common line 105. Read request common line 102. Write request common line 103. A common signal line group consisting of a response common line 106 and a bus occupancy request line 2010 of the processor 2. The processor 31's occupancy request, the bus occupancy request lines such as W3100, and the processor 2's bus occupancy permission 120L1. The bus occupancy permission line group includes a bus occupancy permission line group such as a bus occupancy permission line 3101 of the processor 31.

The bus occupancy request lines 2010 and 3100 are connected to the bus controller 11 and send a bus occupancy permission signal 12011 to a processor with a higher priority.

3101 is output.

Main processor 2 read request line 2012. Write request line 2013. Address line 2014. Data line 2015. The response input lines 2016 are connected to the read request lines 102 . Write request line 103, address line 104.
Data lines 105, ), t; are connected to the valley line 106. Also, the read request line 3102 of the sub-processor 31.
Write request line 3103° Address line 3104. Data line 3105. Similarly, the response input lines 3106 are also connected to the read request lines 1o2. of the system bus 1, respectively. Write request line 10
3° address line 104. Data line 105. Response line 106
It is connected to the.

Furthermore, access a202 from the system bus 1 to the private memory 22 of the main processor 2 is accessed from the system bus l.
Read request M102. Write request line 103. Address line 104. Read request line 2022 and write request line 2023 connected to data line 105 and response line 106, respectively
．． It consists of an address line 2024 and a response output line 2025.

FIG. 3 is a time chart showing the normal operation of the system bus 1.

Consider a case where processor 2 performs a read operation and processor 31 performs a write operation.

First, when the bus occupancy request signal 2010 is turned on.

A bus occupancy permission signal 2011 to the processor 2 is output. Once the bus occupancy permission signal is turned on, until it is turned off, even if another processor's bus occupancy request No. 42 No. 31
Even if 00 is turned on, a permission signal for it is not output.

When the bus occupancy permission signal 2011 is turned on, the processor 2 turns on the address line 2014 and then turns on the read request line 2012. After receiving the read request line 2012, the memory busses the memory contents corresponding to the address onto the data line 2015, and then turns on the response line 2016. When these series of cycles are completed, the bus occupancy request line 2100 is turned off, and the bus occupancy permission line 2011 is turned off.

When the bus occupancy permission line 2011 is turned off, the next bus occupancy permission line 3101 is output in response to the suspended bus occupancy request signal 3100. The sub-processor 31 that received the bus occupancy permission line 3101 receives the address 3104. The data 3105 is placed on the bus and the write request 3103 is turned on. The memory that received this access receives a response signal 3L.
Turn on 06.

Next, FIG. 4 shows how the nodes are occupied for reading and writing the management flags 121 and 122 in the common memory 12.

This figure shows how the processor 2 occupies the bus until it completes the read and write operations.

The first half of the read operation is the same as that shown in FIG.
It remains on without being turned off. Since the bus is occupied until the subsequent write operation is completed, other processors cannot use the bus, and as a result, conflict in access to the management flags 121 and 122 can be prevented.

FIG. 5 shows the address assignment of the system bus 1. A certain area of the address is allocated to the common memory 12, and a certain area is allocated to the private memory 22.

FIG. 6 shows the configuration of the common memory 12.

The address line 104 of the system bus l is connected to an address line 1204 in the common memory, and the address line 120
4 is an address decoder 12040 and a memory section 120
It is connected to the. The address decoder 12040 checks whether the address area is in the common memory 12 shown in FIG. 5 or not, and turns on the address match output 12041 if the address area is in the common memory 12.

AND gate 12021 connected to the read request line 1202 in the common memory whose other input is connected to the read request line 102;
AND gate 12031 connected to write request line 1203 in common memory connected to write request line 103
and is connected to. AND gates 12021 and 120
The output of 31 is connected to the memory section 120, and only when the addresses match, the contents of the data line 1205 in the common memory connected to the data line 105 of the system bus 1 are transferred to the memory, or the contents of the memory are put on the bus. .

To output a response signal 106 to other processors,
The outputs of AND gates +2021 and 12031 are passed through OR gate 12061 to delay element 12062 and address-rescue force 12041, which generate appropriate timing.
The output 120 of the AND gate 12063 which takes the AND with
6 is connected to the response NlA 106. As a result, when there is a read request or a read mill request to the common memory 12, the response signal 106 is output at an appropriate timing.

FIG. 7 shows the configuration of the private memory 22.

The private memory 22 is composed of a two-point RAM 220 to which an access line 200 of the instruction execution unit 21 of the main processor 2 and an access line 202 from the system bus 1 are connected. 2-bot RAM means 2 sets of addresses.
It is a memory that has data and control signal input/output, and can accept two accesses at the same time.

The access line 200 of the instruction execution unit 21 is the read request line 2
002. Write request line 2003. Address line 2004.
It consists of data [2005 and response signal line 2006]. The response signal 2006 is an OR gate 20061 that takes the logical sum of the read request 2002 and the write request 2003.
and No. 43 generated by the delay element 20062 for timing generation.

The access line 202 from the system bus 1 is a read request line 2022. Write request line 2023. address line 202
4. Data line 2025. It is composed of response lines 2026, and these signal lines are respectively connected to the 4n line group of the system bus 1, as shown in FIG.

Address line 2024 is connected to address decoder 202'IO
and a two-point RAM 220. The address decoder 20240 outputs an address match output 202 when the address area of the private memory 22 shown in FIG.
Turn on 41. The address-rescue force 20241 receives the other input from the read request line 2022 and the write request line 202.
AND Gamegoo 20221, 20231 connected to 3
Connected to 2 buttons 1 to RAM only when ADLS matches.
220 is started. The response output 2026 to system bus 1 is the AND gate 202
OR gate 20261 that takes the logical sum of 21 and 20231
is generated by a delay element 20262 for timing generation, and an address matching gate 20263.

Next, the processing when starting the sub-processor 31 from the main processor 2, and the process when starting the sub-processor 31 from the main processor 2
The response process for the completion report will be explained.

FIG. 8 is a flowchart showing the startup process of the main processor 2.

First, in step 231, the management flag 121 of the common memory 12 is read, and in step 232, the flag is set to [0].
” to test whether or not. If “0”, step 233
If it is not rOJ, the process returns to step 231. In step 233, the ID code (set to 2) of the own processor is written.

Processing 230 from step 231 to step 233 is performed while the system bus 1 is occupied as shown in FIG. This prevents other processors from accessing the flag 121.

After entering the ID code δ into the flag 121 in step 233, desired activation information is written into the activation data area 221 of the private memory 22 in step 234. After step 234 is completed, in step 235, flag 1
21 and wakes up the sub-processor 31 in step 236! 11.

FIG. 9 is a flowchart of the startup process of the sub-processor 31. When Ijs is activated in step 236 in FIG. 8, this process is started.

The process 350 from step 351 to step 353 is a process of writing the ID code (31) of the own processor to the management flag 121 of the common memory 12. Processed as is.

If the ID code can be written to the flag 121 in step 350, the right to access the activation data area 221 can be acquired, and in step 354, the area 22
Read the startup information of 1.

In the next step 355, the flag 121 is cleared to O,
In the next step 356, processing based on the activation information is started.

FIG. 10 is a flowchart of response processing when processing based on the activation information is completed.

The process 360 from step 361 to step 363 is a process of entering the ID code of the own processor for four years into the management flag 122 of the response data area 222 and acquiring the right to access the area 222. This process 360 occupies the bus as shown in FIG. Processed up to If the access right is acquired, response data representing the processing result is written into the response data area 222 in step 364. After step 364 is completed, the flag 122 is cleared to O in step 365, and the processor 2 is activated in step 366.

FIG. 11 is a flowchart of the response processing of the main processor 2. This process is the process started at step 366 in FIG.

The process 240 from step 241 to step 243 is a process of writing an ID code to the flag 122, and the fourth
As shown in the figure, the system bus 1 is occupied.

After the process 240 is completed, the response data of the area 222 is read in step 244, the flag 122 is cleared rOJ in step 245, and the process based on the response data is started in step 246.

〔Effect of the invention〕

According to the present invention, the main processor can handle relatively large amounts of data such as startup data and response data without competing with the sub-processor, so the main processor can communicate with other processors in a multiprocessor system. (The overhead of Δ can be reduced.

The processing power of a multiprocessor system can be improved.

[Brief explanation of the drawing]

1 is a system configuration diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of the system bus, FIG. 3 is a time chart of bus transfer, and 414 is a time chart 1 when the bus is occupied.
〜, FIG. 5 is a diagram showing address allocation in this embodiment,
Fig. 6 is a configuration diagram of the common memory, Fig. 7 is a configuration of the private memory - Fig. 1, Fig. 9, Fig. 10, and Fig. 11 are the main processor startup processing, sub-processor startup processing, 3 is a flowchart of a response process of a sub-processor and a start-up process of a main processor. 1... System bus, 2... Main processor, 31°32.33... Sub-processor, 12... Common memory. 22...Private memory, 121...Management flag for area for startup data, 122...) Management flag for area for answer data, 221...Area for startup data. 222...Response data area.

Claims (1)

[Claims] 1. In a multiprocessor system in which a main processor that executes a system management program and a plurality of sub-processors that execute jobs are connected to the same system bus, the main processor is connected to its own processor and the system bus. It has a private memory that is accessed from a sub-processor via a bus, and a common memory that is accessed by a plurality of processors and a bus occupancy control means that controls occupancy of the system bus are connected to the system bus. Data exchange between the two is performed via a specific area of the private memory,
An inter-processor communication system characterized in that access rights to the area are managed using an occupancy flag provided on the common memory.