JP2952896B2 - Shared memory access method in multitask multiprocessor system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory access method in a multitask multiprocessor system.

[Conventional technology]

In order to increase the processing capacity of the entire system, a multi-task multi-processor system in which the system is constituted by a plurality of processors of the same level and a plurality of tasks are operated in parallel on each processor, is generally used. Are provided with a shared memory, and each processor is configured to be able to access the shared memory via a common bus. Then, as a shared memory access method for avoiding inconsistency due to simultaneous updating of the same data on the shared memory by a plurality of processors,
Conventionally, the following method using a lock flag has been adopted.

First, when a task operating on a certain processor attempts to update data on the shared memory or the like, the processor reads the value of a lock flag provided on the shared memory via the common bus, and reads the value of the lock flag. If it is an off value indicating that the data is not occupied, access to the data is performed after writing an on value indicating that the data is occupied to the lock flag via the common bus, that is, acquiring the lock, and after the access is completed, The lock flag is accessed via the common bus and written back to the off value. On the other hand, if the value of the lock flag is ON when the value is read, the other processor is accessing the data on the shared memory. The operation of continuously reading the value of the flag is continued until the lock flag becomes an off value, or (2) the operation of reading the value of the lock flag after waiting for a certain fixed time is performed by the lock flag. Repeat until off value. And these (1),
When detecting that the lock flag has become an off value in the operation (2), the lock flag is replaced with an on value to access the shared memory.

[Problems to be solved by the invention]

The conventional shared memory access method described above has no problem in preventing simultaneous updating of data in the shared memory, but has the following problem in terms of system processing capability.

In the method (1) of scanning the lock flag when the lock flag is ON, the capability of the processor is occupied by the scan, and the capability as a multitask cannot be fully utilized.

Similarly, when the lock flag is on, the system waits for a certain time and tries again (2). And it is difficult to access the data.

Therefore, an object of the present invention is to reduce the processing capability of the processor when the lock flag is on,
An object of the present invention is to acquire a lock in a shortest time and access data on a shared memory.

Means for Solving the Problems In order to achieve the above object, the present invention comprises a plurality of processors each running a plurality of tasks, and a shared memory connected to the plurality of processors via a common bus. A multi-task multi-processor system for performing exclusive control on data on the shared memory by using a lock flag accessible from each processor via the common bus; and a latch circuit for holding data set by the processor. A comparison circuit for comparing the data held in the latch circuit with an address at the time of writing on the common bus, and generating an interrupt to the processor when a match signal is output from the comparison circuit; An additional circuit including an interrupt circuit for outputting a reset signal is provided for each processor. If the value of the lock flag read via the common bus in the processing of a certain task indicates that the processor is occupied, the address of the lock flag is set in the latch circuit in the additional circuit corresponding to the own processor. After that, the task is put into a wait state, another task is executed, and the interrupted circuit in the additional circuit corresponding to the own processor causes the task in the wait state to be in an executable state.

[Action]

In the shared memory access method in the multi-task multi-processor system of the present invention, each processor, if the value of the lock flag read via the common bus in the processing of a certain task indicates that the processor is occupied, After setting the address of the lock flag in the latch circuit in the additional circuit, the task is put into a wait state and another task is executed, and the comparison circuit in the additional circuit in which the address of the lock flag is set is assigned to the address. And compare it with the address at the time of writing on the common bus. Thereafter, when the other processor terminates the access to the data on the shared memory and outputs the address of the lock flag to the common bus in order to write the value corresponding to the non-occupied state to the lock flag, the comparison circuit in the additional circuit described above outputs When a comparison match is detected, an interrupt is generated from the interrupt circuit to the corresponding processor, and the processor that has received the interrupt makes the task in the wait state executable. Also, the reset signal is output to the interrupt circuit latch circuit.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a main part of an embodiment of the present invention.
It includes a plurality of processing devices 1 and 2 each running a plurality of tasks, and a shared memory 4 connected to these processing devices 1 and 2 via a common bus 3. Exclusive control of data on the shared memory 4 is performed. The present invention is applied to a multitasking multiprocessor system using a lock flag accessible from each of the processing devices 1 and 2 via the common bus 3, for example, a lock flag provided on the shared memory 4.

As shown in FIG. 1, the processing device 1 includes a processor 10
A bus buffer 11 controlled by the processor 10 to connect the bus of the processor 10 to the common bus 3;
The latch circuit 12 holds the data output from the processor 10 by the instruction of 10, and compares the address value when the address for writing data is output to the common bus 3 with the data held in the latch circuit 12. A comparison circuit 13 that outputs a coincidence signal by matching,
And an interrupt circuit 14 for generating an interrupt signal to the processor 10 by outputting a coincidence signal from the processor 10 and generating a reset signal to the latch circuit 12. The processing device 2 also has the same configuration as the processing device 1.

FIG. 2 is a flowchart showing a processing example of the processor in the processing devices 1 and 2, and the operation of the present embodiment will be described below with reference to the drawings.

In FIG. 1, when performing a process of updating data in the shared memory 4 or the like in a certain task process, the processor 10 of the processing device 1 checks a lock flag concerning the data as shown in FIG. 51) If the lock flag is off, turn on the lock flag (step 54)
Data processing including the data update processing is performed (step 55).

On the other hand, when detecting that the lock flag is on in step 51 because the other processing device 2 has acquired the lock, the processor 10 sets the address of the lock flag in the latch circuit 12 (step 52), The task is put into a wait state (step 53). Then, another task in the executable state is executed.

Thereafter, when the processing device 2 outputs the address of the lock flag to the common bus 3 as part of the process of rewriting the lock flag to off, the comparison circuit 13 detects a match between the address and the address held in the latch circuit 12, and
An interrupt signal is sent from the interrupt circuit 14 to the processor 10. At this time, the latch circuit 12 is reset.

When an interrupt signal is applied from the interrupt circuit 14, the processor 10 enters an interrupt process shown in FIG. 2, posts the task in the wait state described above (step 56), and sets the task in an executable state. When the task enters the execution state, the processor 10 turns on the lock flag (step 54) and performs data processing (step 55), as shown in FIG.

The above is the operation of the processing apparatus 1, but the processing apparatus 2 performs the same operation.

〔The invention's effect〕

As described above, in the shared memory access method in the multitask multiprocessor system of the present invention, for each processor, the data set by the processor and the address at the time of writing on the common bus are compared and matched. An additional circuit that generates an interrupt to the processor is provided.If each processor has already occupied another processor when processing data on the shared memory, the address of the lock flag is set in the additional circuit corresponding to its own processor. At the same time, the task is put into a waiting state, another task is processed, and the interrupt from the additional circuit generated when the other processor which has occupied the data on the shared memory releases the occupation. Since the above-mentioned tasks in the waiting state can be executed, the ability as a multitask can be fully utilized. Can be, without reducing the processing capacity of the processor, it is possible to perform access to data in the shared memory to get the lock in the shortest time.

[Brief description of the drawings]

 FIG. 1 is a block diagram of a main part of an embodiment of the present invention, and FIG. 2 is a flowchart of a processing example of a processor. In the figure, 1, 2 processing unit 3 common bus 4 shared memory 10 processor 11 bus buffer 12 latch circuit 13 comparison circuit 14 interrupt circuit

Claims (1)

(57) [Claims] A plurality of processors each running a plurality of tasks; and a shared memory connected to the plurality of processors via a common bus, wherein exclusive control of data on the shared memory is performed by the common bus. A multi-task multi-processor system using a lock flag accessible from each processor through a latch circuit for holding data set by the processor, and writing the data held in the latch circuit and the data on the common bus An additional circuit including a comparison circuit that compares an address of the time and an interrupt circuit that generates an interrupt to a processor when a match signal is output from the comparison circuit and outputs a reset signal to the latch circuit. Provided for each processor, wherein each of the processors reads out via the common bus in processing of a certain task. If the value of the lock flag indicates occupancy, the task is set to a wait state after setting the address of the lock flag in the latch circuit in the additional circuit corresponding to the own processor, and execution of another task is performed. A shared memory access in a multitask multiprocessor system, wherein the task in the wait state is made executable by an interrupt from the interrupt circuit in the additional circuit corresponding to the own processor. method.