JPS63165859U - - Google Patents

Info

Publication number
JPS63165859U
JPS63165859U JP5880687U JP5880687U JPS63165859U JP S63165859 U JPS63165859 U JP S63165859U JP 5880687 U JP5880687 U JP 5880687U JP 5880687 U JP5880687 U JP 5880687U JP S63165859 U JPS63165859 U JP S63165859U
Authority
JP
Japan
Prior art keywords
semiconductor element
integrated circuit
hybrid integrated
conductive path
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5880687U
Other languages
English (en)
Other versions
JP2503984Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987058806U priority Critical patent/JP2503984Y2/ja
Publication of JPS63165859U publication Critical patent/JPS63165859U/ja
Application granted granted Critical
Publication of JP2503984Y2 publication Critical patent/JP2503984Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第1図は本考案の実施例を示す断面図、第2図
は本実施例においてのROMライタによる書き込
みを示す概略図である。 1は混成集積回路基板、2は絶縁樹脂膜、3は
導電路、4,5は半導体素子、6は樹脂、7はケ
ース。

Claims (1)

    【実用新案登録請求の範囲】
  1. 混成集積回路基板と、前記混成集積回路基板上
    に設けられた所望形状の導電路と、前記導電路上
    に少なくとも設けられたプログラム可能な半導体
    素子あるいはプログラム可能な領域を有する半導
    体素子と、前記プログラム可能な半導体素子ある
    いは前記プログラム可能な領域を有する半導体素
    子と前記導電路とを接続するワイヤと、前記半導
    体素子を封止する封止樹脂と、前記半導体素子と
    空間を有し前記混成集積回路基板に固着されるケ
    ース材とを備えたことを特徴とする混成集積回路
JP1987058806U 1987-04-17 1987-04-17 混成集積回路 Expired - Lifetime JP2503984Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987058806U JP2503984Y2 (ja) 1987-04-17 1987-04-17 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987058806U JP2503984Y2 (ja) 1987-04-17 1987-04-17 混成集積回路

Publications (2)

Publication Number Publication Date
JPS63165859U true JPS63165859U (ja) 1988-10-28
JP2503984Y2 JP2503984Y2 (ja) 1996-07-03

Family

ID=30889709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987058806U Expired - Lifetime JP2503984Y2 (ja) 1987-04-17 1987-04-17 混成集積回路

Country Status (1)

Country Link
JP (1) JP2503984Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006171978A (ja) * 2004-12-14 2006-06-29 Denso Corp 電子機器の製造方法、基板の製造方法、電子機器及び基板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5937737U (ja) * 1982-09-03 1984-03-09 凸版印刷株式会社 集積回路塔載ボ−ド
JPS6013746U (ja) * 1983-07-06 1985-01-30 三洋電機株式会社 混成集積回路の封止構造

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5937737U (ja) * 1982-09-03 1984-03-09 凸版印刷株式会社 集積回路塔載ボ−ド
JPS6013746U (ja) * 1983-07-06 1985-01-30 三洋電機株式会社 混成集積回路の封止構造

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006171978A (ja) * 2004-12-14 2006-06-29 Denso Corp 電子機器の製造方法、基板の製造方法、電子機器及び基板
JP4626289B2 (ja) * 2004-12-14 2011-02-02 株式会社デンソー 電子機器の製造方法、基板の製造方法、電子機器及び基板

Also Published As

Publication number Publication date
JP2503984Y2 (ja) 1996-07-03

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