JPS63164546A - Phase control circuit - Google Patents

Abstract

PURPOSE:To shorten a leading-in time and to output clocks with a stabilized phase by detecting a phase shifted value by means of a shift register at the time of comparing phases and selecting a frequency dividing value in accordance with the phase shifted value. CONSTITUTION:An input signal 100 and shift clock 110 synchronizing with a master clock 180 are inputted to the shift register 120 and latched data are stored in the shift register 120. An output signal 170 and the master clock 180 are inputted to a decoder control circuit 130, and after counting up clocks from the rise of the signal 170 up to 1/2 the number of shifted bits by means of a master clock, a decode enable signal 131 is outputted to the decoder 140. The decoder 140 decodes the contents of the shift register 120 on the basis of the decode enable signal 131 and outputs a signal for selecting the frequency dividing ratio of a frequency divider 160 to a fluctuation deciding circuit 150 on the basis of the decoded result. The circuit 150 outputs a signal for specifying the final frequency dividing ratio under the consideration of 'fluctuation' to the frequency divider 160.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase control circuit widely used in digital communication receiving devices, and in particular to a phase control circuit that matches the phase of an internal clock with the phase of a received signal and maintains a stable phase. [Conventional technology] Regarding a phase control circuit having a unit that outputs a clock In data transmission, the receiving side must extract information without error from the transmission waveform containing jitter and noise sent from the other party. In serial transmission, data is sent bit by bit serially. Therefore, in order to extract data from the transmitted signal, it is necessary to find the bit boundaries, that is, to-soto synchronization.4 This synchronization technique is very important for transmission, and it is important to improve the synchronization ability. PLL (Phase L) is a major force in improving the quality of transmission2.
(locked Loop) and is automatic control regarding the phase. The purpose of the PLL is to match the phase of the internal clock with the phase of the received signal and to output a clock with a stable phase. Delay or lead is detected by a phase comparator, and control is performed to advance the internal clock if it is late, and to delay the internal clock if it is ahead. However, due to temporary fluctuations in the phase of the received signal due to fluctuations in the receiving system,
If you follow the internal clock, you will not be able to obtain a clock with a stable phase. Therefore, the conventional PL
The configuration of a conventional phase control circuit is shown in Figure 4, in which a filter is added to its components to absorb the "fluctuations" of phase fluctuations and obtain a clock with a stable phase. The operation will be explained below with reference to FIG.

In FIG. 4, the phase comparator 320 is a phase comparator that compares which phase of the input signal 300 and the output signal 310 of the frequency divider 340, and when the output signal 310 of the frequency divider 340 rises, the input signal 300 becomes a logic The 2 filter 330 that outputs either "0'" or "1'" is a filter that outputs a signal that changes the frequency divider to the frequency divider 340 according to the output of the phase comparator 320. The upper limit designation signal 350 and the lower limit designation signal 360, which are frequency dividers that change the frequency division ratio of the master clock 370 by the output signal of the filter 330, are used to specify the upper limit value and lower limit value used by the counter in the filter 330, respectively. This is a signal to Output signal 310 is the output signal of frequency divider 340.

5 filters 33 whose operation is explained below.
If the input from the phase comparator 320 is 1, +
1. There is an up/down counter that counts 11 when it is "0", and the filter 330 checks whether the count value has reached the upper limit or lower limit specified by the upper limit designation signal 350 or the lower limit designation signal 360. Judgment is made by the comparison circuit.

Here, if the count value does not reach the upper or lower limit, no processing is performed, but if the count value reaches the upper or lower limit, specify an increase or decrease in the division ratio. The signal is output to the frequency divider 3406. In other words, in the filter 330, an up/down counter counts how many times the phase shift occurs in the same direction, and the counter outputs a predetermined value (upper limit designation signal 350 or lower limit designation signal 360). By increasing or decreasing the division ratio, a phase-stable clock can be regenerated.6 Phase comparison between the human input signal and the output signal of the frequency divider. This is done in the form shown in Figure 5. For example, when the output signal is delayed in phase by three cumulative times with respect to the input signal, the denominator of the frequency division ratio is decreased by 1, and the cumulative phase is delayed by three times. The case where the denominator of the frequency division ratio is increased by 1 when the frequency advances is described below.5 In FIG. Therefore, even at point 2B where the counter of the filter 330 counts 11, the input signal has logic "0" at the rising edge of the output signal, and the counter further counts 11.
The counter indicates -2, and even at the 0 point, the input signal has logic ``0'' at the rising edge of the output signal, and the filter 33
The counter at 0 counts -1 and shows -3 6 In other words, the phase of the output signal is ahead of the input signal, cumulatively 3 times at point A, point B, and point 0.6 The phase of the output signal is ahead of the input signal. The frequency division ratio of the frequency divider is increased by 1 due to the output signal of the filter indicating that the frequency has advanced.As a result, the clock width of the signal output from the frequency divider becomes longer, as shown by point D. As shown in Figure 5(b), the phase of the output signal approaches that of the input signal.7 As these operations are repeated, the input signal and output signal become synchronized.2 In Figure 5(b), the phase comparator detects point E. Then, the output signal goes low and the input signal has logic II II II, so the filter counter counts +1.F
Even at the point, the input signal becomes logic "'1" at the rising edge of the output signal.
°' and the counter further counts +1 and shows +2. Similarly at point G, at the rise of the output signal -6=, the input signal has logic "1'" and the counter counts +1 and shows +3. In other words, point E・
At point F and point G, the phase of the output signal is delayed with respect to the input signal three times cumulatively.4 The output signal of the filter, which indicates that the phase is delayed three times cumulatively, changes the division ratio of the frequency divider. Since the denominator is decreased by 1, the clock width of the signal output from the frequency divider becomes shorter, and the phase of the output signal approaches the input signal as shown by point H. These operations are repeated. [Problem to be solved by the invention] In the conventional PLL configuration described above, when comparing the phases of the input signal and output signal, the magnitude of the phase shift is cannot be detected, so the frequency division ratio increases or decreases according to a certain value regardless of the amount of phase shift.7 In this case, there are only three ways for the frequency division ratio: increase by 1, no change, and decrease by 1. 6 Therefore, PLLs with conventional configurations have the disadvantage that the time it takes to enter a synchronous state from an unsynchronized state, that is, the pull-in time is long.6 Furthermore, the frequency divider
Since there are only three stages: increase by 1, no change, and decrease by 1, the tracking range becomes narrow.6 Also, if the frequency division ratio is N increase, no change, and N decrease (N is a natural number of 2 or more), the Although the integration time can be shortened and the tracking range can be widened, it has the disadvantage that the amount of jitter in the reproduced signal increases.6Furthermore, in the conventional PLL configuration, since a filter is used, it is possible to reduce the phase shift. Since the operation of counting the number of phase shift detections is repeated regardless of the amount, and the division ratio is specified only when the counter value reaches a predetermined value, it has the disadvantage that it takes time to follow up. Conventional PL
If the filter is removed, the tracking time will be shortened, but there is a drawback that the phase of the reproduced signal will not be stable.2 Therefore, in contrast to the conventional PLL configuration, the present invention By using a shift register and decoding the contents of the shift register, the phase difference between the input clock and the clock applied by the PLL is measured, and the frequency division amount of the frequency divider is specified according to the phase difference. In addition to outputting a signal,
By decoding a signal that specifies multiple frequency division amounts, the present invention provides an output with a stable phase that is not affected by phase fluctuations of the received signal without delaying the tracking time. [Means for solving the problem] The phase control circuit of the present invention has an original content of obtaining a signal, and the phase control circuit of the present invention has an original content of obtaining a signal.
A clock that is synchronized with this master clock is used as a shift clock, and an N-bit (N is a natural number of 2 or more) shift register that receives an input signal, a frequency divider that divides the frequency of the master clock, and a frequency divider. A decoder control circuit that receives an output signal and a master clock as input, a decoder that decodes the contents of the shift register using the signal output from this decoder control circuit, and a signal that uses the output signal of this decoder to control the frequency division ratio. The decoder control circuit has a fluctuation discrimination circuit that outputs to the frequency divider, and the decoder control circuit detects the master clock signal from the output signal from the frequency divider.
half the number of bits in the shift register, that is, N/
This is a means for outputting a decode enable signal to a decoder after two counts.7 [Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. In FIG. 1, reference number 100 is an input signal;
The output signal 170 is a clock obtained by applying a PLL to the input signal 100, and the shift register 120 receives the input signal 1.
00 and the output signal 170, and the decoder 140 is a register that is a means for performing a phase comparison between
It is a means for decoding the contents of 0, and the fluctuation discrimination circuit 1
50 is a means for determining "fluctuation" in the phase of the input signal based on the output of the decoder 140; a frequency divider 160 is a means for dividing the frequency of the master clock 180; The shift clock 110 is a clock that is synchronized with the master clock 180.
The decoder control circuit 130 receives an output signal 170 and a master clock 180, and after counting half the number of shift register bits using the master clock from the rising edge of the output clock, outputs a decode enable signal 131 to the decoder. The present invention will be described in detail with reference to FIGS. 1 and 3. As a first example, let us consider the case where the shift register 120 is 4 bits.7 This shift register 120 has an input signal 100 and a master clock 18.
The output signal 170 and the master clock 180 are input to the decoder control circuit 130 which inputs the shift clock 110 synchronized with 0 and stores the latched data in the shift register 120. After counting half the number of shift register bits (i.e. 1/2) from the rising edge using the master clock 180, the decode enable signal 13 is sent to the decoder 140.
In response to this decode enable signal 131 outputting 1, the decoder 140 decodes the contents of the shift register and outputs a signal for selecting the division ratio of the 1 frequency divider 160 to the fluctuation determination circuit 150 based on the decoding result.Here, The fluctuation discriminating circuit will be explained. An example of the configuration of the fluctuation discriminating circuit 150 is shown in FIG. The selector 200 is a counter that counts up and down by the decoder 140.
This is a selector that specifies the transfer destination of the input signal (input from terminal 151) from counter 2], which selects register 220 when 0 is 0, and selects register 230 when counter 210 is 1. Shi・Jista 220 and 2
30 stores two consecutive frequency division ratio designation signals. Also, when the value of the counter 210 is 1, the counter 210 outputs a decode enable signal to the decoder 240. This decode enable signal causes the decoder 240 to register The data input from 220 and register 230 are decoded, and a signal specifying the final frequency division ratio after considering "°fluctuation" is sent to frequency divider 160 from terminal 152.
Figure 6 shows the relationship between the input signal output to the output signal, the output signal, the master clock, and the contents of the shift register. (a, ) and (b) in Figure 6 are cases in which the output signal is ahead of the input signal. (c) in Figure 6 is a state in which the output signal and input signal are almost synchronized, and (d) and (e) are in a state in which the output signal is delayed with respect to the input signal. By decoding the contents of these shift registers, a frequency division ratio designation signal before taking into account phase fluctuations of the received signal can be obtained.9 Normally, the frequency division ratio of the frequency divider 160 is 1./N. For example, the value of the shift register is (a
), (b), (c), (d), and (e), the division ratio designation signal by the decoder output is the following five division ratios: 1.
1・(N+2)・l/(N+1)・17'N・l/(N
-1> ・1. /(N-2) In cases (a, ) and (b) in Figure 6, in both cases (a> and (b) in Figure 6, the output signal leads the input signal). (
When the state b) is reached, in the embodiment of the present invention, the frequency division ratio designation signal from the decoder output is set to the frequency division ratio 1/(NL+
-2)・1/(N+l), so if there is no fluctuation in the phase of the received signal, the frequency division ratio 1/(
N+2>, 1/(N+1> is output as is from the fluctuation discrimination circuit as a frequency division ratio designation signal, and the clock width of the output signal of the frequency divider becomes longer, the phase of the input signal and the output signal become closer, and the phase In case (a) where the amount of deviation is large, the division ratio is smaller, so the clock width of the output signal is longer than in case (b), and the 5 or ( In c), the input signal and output signal are almost synchronized, so if there is no "fluctuation" in the phase of the received signal, the division ratio is set to 1 using the same procedure as (a>・(b)). /N 6 Furthermore, (d>
- When the state (e) is reached, in the embodiment of the present invention, the frequency division ratio designation signal by the decoder output specifies the frequency division ratio 1/(N-1) and 1/(N-2), respectively. Therefore, if there is no fluctuation in the phase of the received signal, the frequency division ratio 1/(
N-1) and 1/(N-2) are output as they are from the fluctuation discrimination circuit as the division ratio designation signal, and the clock width of the output signal of the frequency divider becomes shorter, and the phase of the input signal and output signal become closer to each other. , in case (e) with a large phase shift, the frequency division ratio is larger, so the clock width of the output signal is shorter than in case (d), and it works to compensate for a large phase shift6. In other words, it works to change the amount of correction according to the phase shift. 5 Therefore, the pull-in time is shortened. It is shown in FIG. Corresponding to the combination of two consecutive frequency division ratios obtained from the decoder, the fluctuation discrimination circuit determines one frequency division ratio and designates it as the frequency division ratio. FIG. 7 is an example of the correspondence table. If the values of two consecutive frequency division ratios are similar (for example, 1/(N
+2) and 1/(N+1> or 1/(N-2) and 1/(
N-1>), this is regarded as a phase shift and a selected frequency division ratio is specified for the frequency divider.

If they are not similar (for example, 1/(N+2> and 1/(N
-2>), this is the phase of the received signal.
In other words, the phase control circuit according to the present invention eliminates the "fluctuation" in the phase of the received signal without delaying the follow-up time. It is possible to output an output signal with a stable phase that is not affected by This is the case when the shift register is 8 bits. When the shift register is 8 bits, the counter is decode enabled for the decoder after counting 4 clocks with the master clock at the same time as the output signal rises. Outputs a signal.If the shift register is 8 bits, the values that the shift register can take are OOH and OI.
H・03H・07H・OFH・IFH・3FH・7FH
-FFH (H indicates hexadecimal notation)
There are 9 types of frequency division ratios from 1/(N+4) to 1/(N
-4), the range becomes wider.

In this way, by increasing the number of bits in the shift register, the range of phase deviation between the input signal and output signal can be detected in detail, and the frequency division ratio is changed according to the phase deviation, resulting in faster pull-in time. However, in this case, the selection of the frequency division ratio value corresponding to the contents of the shift register does not necessarily have to be linear. For example, the selection of the frequency division ratio value corresponding to the contents of the shift register as shown in FIG. Conceivable.

〔Effect of the invention〕

As explained above, in the present invention, the amount of phase shift is detected using a shift register during phase comparison, and the amount of frequency division can be selected from among several levels according to the amount of phase shift. It has the effect of shortening the draw time.
6 In addition, the larger the number of bits in the shift register, the wider the tracking range and the higher the accuracy, as described in the second embodiment. However, it also has the effect of shortening the pull-in time.5 Also, in the present invention, instead of the filter used in the conventional phase control circuit, a register and a decoder are used to decode several frequency division ratio designation signals. By doing this, it is possible to detect "fluctuations" in the phase of the received signal, so it is possible to obtain an output signal with a stable phase that does not follow the "fluctuations" in the phase of the received signal, without delaying the tracking time. 6 In a phase control circuit, shortening the pull-in time and increasing accuracy and outputting a clock with a stable phase that is not affected by "'fluctuations" in the phase of the received signal mean that the functions of communication equipment can be improved. It is important for growth and its effects are large6

[Brief explanation of the drawing]

FIGS. 1 and 2 are professional diagrams showing the configurations of phase control circuits according to the first and second embodiments of the present invention, respectively, and FIG. 4 is a block diagram showing the configuration of a conventional phase control circuit of 18-type, FIG. 5 is a time chart of phase comparison of the conventional method, and FIG. 6 is a time chart of phase comparison according to the present invention. , FIG. 7 is a chart showing the correspondence between the combination of two consecutive frequency division ratio designation signals of the first embodiment and the frequency division ratio designated by the fluctuation discrimination circuit, and FIG. 8 is a diagram of the second embodiment. Chart 6120...4-bit shift register, 130...
Decoder control circuit, 140... Decoder, 150...
- Fluctuation discrimination circuit, 160... Frequency divider, 190...
8-bit shift register 6

Claims (1)

[Claims] In a phase control circuit that outputs a signal whose phase is controlled with respect to an input signal, the input signal is input and shifted using a shift clock synchronized with the master clock.N bit width (N is 2
or above), a decoder that decodes the contents of the shift register, a frequency divider that can vary the frequency division ratio that divides the master clock, and M outputs from the decoder (M is 2 a discriminating circuit that outputs a signal for controlling the frequency division ratio of the frequency divider using the above natural numbers), and a decoding enable signal to the decoder that receives the output of the frequency divider and the master clock as inputs. A phase control circuit comprising: a decoder control circuit that outputs an output.