JPH04304026A - Phase control circuit - Google Patents

Abstract

PURPOSE:To decrease a lock time reaching a synchronization state and a tracking time, to expand the tracking range and to realize the suppression of jitter by using a shift register so as to detect a phase shift and selecting a frequency division ratio in response to the phase shift. CONSTITUTION:An input signal IN and a master clock CLK are inputted to the phase control circuit and an output signal OUT being a clock applying phase control to the signal IN is obtained. A phase difference of a phase of the signal OUT and the phase of the signal IN is detected by a shift register 1 and the signal is shifted by using a shift clock 8 and the result is inputted to a filter 2. A mean output 10 from the filter 2 and a control signal from a control circuit 4 are decoded by a decoder 3 and a frequency division ratio control signal 12 is outputted to a frequency divider 7. A frequency divider 5 frequency-divides the clock CLK to output serial clocks fn, fm, a selection circuit 6 selects the clock and the shift clock 8 is inputted to the frequency divider 7. The frequency divider 7 frequency-divides the clock 8 in response to the signal 12 and an output signal OUT is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit used in a digital communication receiver, and more particularly to a phase control circuit having a function of matching the phase of an internal clock with the phase of a received signal.

0002

2. Description of the Related Art In a normal data transmission system, information must be extracted without error from a transmission waveform containing jitter and noise, which is sent from the receiving side. In particular, in serial data transmission, data is sent bit by bit serially, so in order to extract data from a transmission signal, it is necessary to find the boundaries between bits, that is, bit synchronization. Such synchronization technology is very important for transmission, and increasing the synchronization ability will be a major force in improving the quality of transmission. A phase-locked loop (PLL) is useful for this, which is an automatic phase control circuit. The purpose of this PLL is to match the phase of the internal clock with the phase of the received signal, eliminate jitter, and output a clock with a stable phase. Therefore, in this PLL (phase control circuit), the phase comparator detects the delay or lead of the rise time of the internal clock with respect to the rise time of the received signal, and advances the internal clock if it is late, and if it is ahead. is controlled to delay the internal clock. However, if the internal clock quickly follows temporary fluctuations in the phase of the received signal due to fluctuations (jitter), it becomes impossible to obtain a clock with a stable phase. A filter is added to absorb the "fluctuations" of phase fluctuations and obtain a clock with a stable phase.

FIG. 11 is a block diagram of a phase control circuit showing an example of such a conventional phase control circuit. As shown in FIG. 11, the conventional phase control circuit uses an input signal IN and an output signal O of a frequency divider 20.
It has a phase comparator 18 that compares the phase with UT, and outputs whether the input signal IN is logic "0" or "1" when the output signal OUT of the frequency divider 20 rises. Also, filter 1
Reference numeral 9 denotes a filter that outputs a signal that changes the frequency division ratio according to the output of the phase comparator 18 to the frequency divider 20;
0 is the master clock C by the output signal of the filter 19.
This is a frequency divider that changes the frequency division ratio of LK. Further, the filter 19 is supplied with signals 21 and 22 specifying upper and lower limit values used in a counter within the filter 19. Among these, the filter 19 has an up/down counter that counts +1 when the input from the phase comparator 18 is "1" and -1 when the input is "0", and a comparator circuit. The value is a predetermined upper limit value 21 or lower limit value 22
The comparison circuit determines whether or not this has been reached. here,
If the count value has not reached the upper limit or lower limit, no processing is performed, but if the count value has reached the upper or lower limit, a signal specifying an increase or decrease in the division ratio is divided. Output to frequency generator 20. That is, filter 19
counts the cumulative number of times the phase shift occurs in the same direction using an up/down counter, and increases or decreases the division ratio when the counter reaches the value specified by the predetermined value 21 or 22. By doing so, it is possible to reproduce a clock whose phase is stable.

FIGS. 12(a) and 12(b) are timing diagrams of input and output signals for explaining the phase comparison operation in the phase comparator shown in FIG. In this case, (b) shows the case where the process is proceeding in the opposite direction. As shown in FIGS. 12(a) and 12(b), the phase comparison between the input signal IN of the phase comparator 18 and the output signal OUT of the frequency divider 20 in FIG. The frequency division ratio is decreased by 1 when the phase is delayed three times cumulatively, and is increased by 1 when the phase is advanced three times cumulatively.

First, as shown in FIG. 12(a), at point A in the phase comparator 18, the input signal IN has a logic "0" at the rising edge of the output signal OUT, so the counter of the filter 19 has a -1 count. do. Also, at point B, the input signal has logic "0" at the rising edge of the output signal OUT, and the counter further counts -1, resulting in the counter indicating -2. Similarly, at point C, the input signal IN at the rising edge of the output signal OUT has logic "0", and the filter 1
Since the counter of 9 counts -1, it indicates -3. That is, the phase of the output signal OUT is ahead of the input signal IN three times cumulatively at points A, B, and C. Therefore, the filter 19 indicates that the phase has advanced three times cumulatively.
The frequency division ratio of the frequency divider 20 is increased by 1 by the output signal OUT. Therefore, the clock width of the signal output from the frequency divider 20 becomes longer, and the phase of the output signal OUT approaches that of the input signal IN, as shown by point D. As these operations are repeated, the input signal IN and output signal OUT become synchronized.

Next, as shown in FIG. 12(b), at point E in the phase comparator 18, the input signal IN has logic "1" at the rising edge of the output signal OUT, so the counter of the filter 19 counts +1. . Also, at point F, the input signal IN becomes logic “1” at the rising edge of the output signal OUT.
Therefore, the counter further counts +1 and shows +2. Similarly, at point G, when the output signal OUT rises, the input signal IN has logic "1", and the counter counts +1 and shows +3. That is, the phase of the output signal OUT is delayed with respect to the input signal IN three times cumulatively at points E, F, and G. The frequency division ratio of the frequency divider 20 is decreased by 1 based on the output signal of the filter 19 indicating that the phase has been delayed by three cumulative times. Therefore, the clock width of the signal output from the frequency divider 20 becomes shorter, and the phase of the output signal OUT approaches that of the input signal IN, as shown by point H. While repeating these operations, the input signal IN and output signal OU
T becomes synchronized.

[0007]

[Problems to be Solved by the Invention] The conventional phase control circuit described above cannot detect the magnitude of the phase shift when comparing the phases of the input signal and the output signal. The frequency division ratio is increased or decreased. In this case, there are only three ways for the frequency division ratio: increase by 1, no change, and decrease by 1. Therefore, the conventional phase control circuit is
When the initial convergence or phase suddenly shifts significantly, there is a drawback that the time required to enter the synchronized state from an unsynchronized state, that is, the pull-in time becomes long.

In addition, since the conventional phase control circuit has only three stages of increasing the division ratio by 1, leaving it unchanged, and decreasing it by 1, the tracking range is narrow, and the operation of counting the number of times a phase shift is detected is repeated and the counter value does not reach a predetermined value. Since the frequency division ratio is specified only when the value of is reached, there is a drawback that it takes time to follow up.

Furthermore, in the conventional phase control circuit, if the frequency division ratio is increased by N, remains unchanged, or decreased by N (N is a natural number of 2 or more), the pull-in time can be shortened and the tracking range can be widened. However, in this case, the amount of jitter in the reproduced signal increases. That is, in the conventional phase control circuit, suppressing jitter and widening the follow-up range and shortening the pull-in time conflict with each other, so there is a drawback that it is impossible to satisfy both at the same time.

An object of the present invention is to provide a phase control circuit that can shorten the pull-in time and follow-up time to reach the synchronized state, expand the follow-up range, and suppress the amount of jitter.

[0011]

[Means for Solving the Problems] The phase control circuit of the present invention is a phase control circuit that creates an output signal whose phase is controlled with respect to an input signal, in which the input signal is input and shifted using a shift clock synchronized with a master clock. a multi-bit width shift register that inputs, filters and outputs the contents of the shift register; a decoder that decodes the output of the filter and outputs a frequency division ratio control signal; a control circuit that outputs a control signal; a first frequency divider that divides the frequency of the master clock and outputs a plurality of serial clocks; and a first frequency divider that selects one of the serial clocks based on the control signal and supplies it to the shift register. a selection circuit that outputs the shift clock; and a second frequency divider that divides the frequency of the shift clock from the selection circuit and outputs an output signal at a division ratio according to a division ratio control signal of the decoder output. detecting a phase difference between the output signal and the input signal using the shift register, selecting a shift clock for the shift register according to the phase difference, and determining a frequency division ratio according to the phase difference. configured to select.

0012

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase control circuit showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment inputs an input signal IN and a master clock CLK to obtain an output signal OUT, and this output signal OUT is a clock obtained by applying phase control to the input signal IN. Also, the internal shift clock 8 is the master clock CLK.
is in sync with. In this embodiment, the output signal OUT
A shift register 1 that detects the amount of phase difference between the input signal IN and the shift clock 8, and a filter that stores the contents of the shift register 1 at the rising edge (or falling edge) of the output signal OUT, averages it, and outputs it. 2
and has. In addition, in this embodiment, these shift registers 1
In addition to the filter 2, the decoder 3 has a decoder 3 and a control circuit 4, and the decoder 3 decodes the average output 10 from the filter 2 and the control signal 11 output from the control circuit 4, and outputs a frequency division ratio control signal 12. do. Furthermore, this embodiment has a first frequency divider 5, a second frequency divider 7, and a selection circuit 6, and the first
A frequency divider 5 divides the master clock CLK and outputs two types of serial clocks fn and fm (frequency fm=4×fn). On the other hand, the selection circuit 6 has a control signal 11 of “0”.
”, selects fn, and conversely, if “1”, selects fm clock and outputs it as shift clock 8. In addition, the second frequency divider 7 uses the frequency division ratio that is the output of the decoder 3. The shift clock 8 (fn or f
m) is frequency divided (n+3 to n-3 for fn, 4 for fm)
(any natural number n+3 to 4n-3, n≧5) and outputs an output signal OUT. Here, the control circuit 4 is the decoder 3
Serial clock selection is controlled according to the frequency division ratio control signal 13 of .

FIG. 2 is a block diagram of the filter shown in FIG. 1. As shown in FIG. 2, the filter 2 includes N-bit first and second registers 14, 15 and an averaging circuit 16, and the filter 2 has N-bit signals stored in the shift register 1. Input output signal 9 and average circuit 1
6 outputs a filter average output of 10. Here, the second
The register 15 is a register whose N bits are all set to "1" by the register set signal 17. Also,
The averaging circuit 16 includes first and second registers 14 and 15.
It is a circuit that takes the AND of the contents of the input signal “
The filter output signal 10 is output by absorbing the "fluctuation", and the register set signal 17 is output corresponding to the filter output signal 10. For example, the filter output signal 10
outputs a register set signal 17 when outputting a frequency division ratio other than 1/n or 1/4n.

FIG. 3 is a diagram showing the correspondence between the filter averaged output and the frequency division ratio control signal in the decoder of FIG. As shown in FIG. 3, such a correspondence corresponds to the filter output 10 as input in the decoder 3 when the shift register 1 is 6 bits.
In addition to showing the correspondence between the control signal 11 and the frequency division ratio control signal 12 as an output, an example of the correspondence of the next control signal 11 is shown. In addition, in the upper row separated by the dotted line, the control signal 11 is “0”.
”, the fm clock is input to the second frequency divider 7 as the shift clock 8, the lower stage shows the case where the control signal 11 is “1”, and the 4×fn clock is input as the shift clock 8 to the second frequency divider 7. 2 is input to frequency divider 8.

Next, FIG. 4 is a transition diagram of input/output signals and the filter for explaining the operation of the filter in FIG. 1, and FIG. 6(a) to (g) are input/output signals and shift diagrams for explaining the phase comparison in the shift register of FIG. 1, respectively. FIG. It is a timing diagram of a clock. As shown in FIGS. 4 to 6, in the operation of the first embodiment, the shift register 1 is
Assuming that the configuration of filter 2 is shown in FIG. 2, input signal IN, output signal OUT, and shift register 1
The relationship between the outputs 9 of is shown in FIGS. 6(a) to 6(g). That is, FIGS. 6(a) to 6(c) show the case where the output signal is ahead of the input signal, FIG. 6(d) shows the case where the output signal and the input signal are almost synchronized, and FIGS. (g) is a case where the output signal lags behind the input signal.

However, the first frequency divider 5 in FIG. 1 divides the master clock CLK to generate the serial clock fn.
and fm are output. Further, the control circuit 4 outputs "0" when the amount of phase difference between the input signal IN and the output signal OUT is large, and outputs "1" when the amount of phase difference between the input signal and the output signal is small.
”, while the selection circuit 6 outputs the control circuit 4
When the output 11 is "0", the low frequency serial clock fn is selected, and when the output 11 is "1", the high frequency clock fm (frequency fm = 4 x fn) is selected and output as the shift clock 8. . Furthermore, the second frequency divider 7 divides the frequency of the shift clock 8 (fn or fm) based on the frequency division ratio control signal 12 to obtain an output signal OUT.

Therefore, in FIG. 4, the synchronization is not yet established, that is, the selection signal output from the control circuit 4 is "0".
” and the selection circuit 6 selects fn as the shift clock 8. In short, at point A in FIG.
This is a case where the clock is ahead by about 2 clocks of fn)8. This case corresponds to FIG. 6(f). Furthermore, the 6 bits of the comparison result stored in the shift register 1 at point A in FIG. 4 are transferred to the first register 14 in the filter 2 shown in FIG.
is stored in Next, the 6 bits of the comparison result stored in the shift register 1 at point B are stored in the first register 14 in the filter 2, and the 6 bits of the comparison result stored in the shift register 1 at point B are stored in the first register 14. The data ahead of is shifted to the second register 15. Furthermore, the contents of these first register 14 and second register 15 are averaged to obtain the filter output 10.

As an example of such averaging, assume that the product of each bit of the first register 14 and the second register 15 is the averaged output 10. That is, from the left of registers 14 and 15, i
If the th bits are respectively Ai and Bi, then Xi, which is the output 10 of the filter 2, is Xi=Ai×Bi. Therefore, in the case of FIG. 4, the filter output 10 becomes the output corresponding to FIG. Outputs 12. Therefore, the second frequency divider 7 converts the fn shift clock 8 to 1/(n-
2) Synchronize the output signal OUT with the input signal IN by dividing the frequency.

[0020] As a result, at point C, the output signal OUT and the input signal IN are almost synchronized. However, C
At the point, the second register 15 has the same value as the previous first register 1.
The contents of 4 are not shifted and are all set to "1". That is, when the filter output 10 is other than the outputs shown in FIGS. 3(D) and (d), the averaging circuit 16 outputs the set signal 17 that sets all the second registers 15 to "1". Therefore, the filter output 10 at point C becomes an output corresponding to FIG. 3(D), and the decoder 3 outputs the control signal 12 with a frequency division ratio of 1/n, so the output signal OUT is stable without changing the frequency division ratio. The clock will be However, as shown in the correspondence in FIG.
m. Changes in this shift clock 8 will be explained with reference to FIG. 7 below.

FIGS. 7A and 7B are timing diagrams of input/output signals and shift clocks for explaining the operation of the shift register at point C in FIGS. 1 and 4, respectively. As shown in FIG. 7(a), the phase comparison results of shift register 1 are almost synchronized when the shift clock is fn, but as shown in FIG. 7(b), the shift clock is fn.
The phase comparison result in units of m (=4fn) is the input signal I
N is in a state where it is ahead of the output signal OUT by about two shift clocks (fm). Therefore, after point C in FIG. 4 where shift clock 8 is selected as fm, the timing of phase control becomes as shown in FIG. 5. In FIG. 5, the shift clock 8 output from the selection circuit 6 is fm
At point D immediately after switching to , the input signal IN is ahead of the output signal OUT by about 2 clocks. That is, this case corresponds to FIG. 6(f).

Next, the 6 bits of the comparison result stored in the shift register 1 at point D in FIG. 5 are stored in the first register 14 in the filter 2, and the comparison result at the previous point C,
That is, the data ahead of the first register 14 is shifted to the second register 15. Here, when the shift clock 8 is fn, the filter 2 similarly averages the contents of the first and second registers 14 and 15 to obtain a filter output 10. Therefore, the filter output 10 becomes an output corresponding to FIG. 3(f), and the decoder 3 outputs a frequency division ratio control signal 12 with a frequency division ratio of 1/(4n-2) to the filter output 10 in accordance with the correspondence shown in FIG. As a result, the second frequency divider 7 receives the frequency division ratio control signal 1.
2, fm shift clock 8 is 1/(4n-2)
The frequency is divided and the output signal OUT is synchronized with the input signal IN.

Therefore, at point E in FIG.
UT and the input signal IN are almost synchronized. However, at point E, the averaging circuit 16 outputs a set signal 17 that sets all the second registers 15 to "1". As a result, the filter output 10 at point E is as shown in Fig. 3 (d
), and the decoder 3 has a frequency division ratio of 1/4.
Since n control signals 12 are output, a clock with a stable phase can be output as the output signal OUT.

FIG. 8 is a filter transition diagram for explaining the filter operation when the input signal in FIG. 1 has fluctuations. As shown in FIG. 8, when the input signal IN is “
In the case of a signal with "fluctuation", the contents of A4 and B4 in the first register 14 and second register 15 in the filter 2 are stored alternately as "0" and "1".
Since the filter output X4 is averaged by the product of A4 and B4, it is always "0". That is, since the filter output signal 10 always outputs only the state corresponding to FIG. 3(d), the decoder 3 has a frequency division ratio of 1/4n corresponding to this output.
A control signal 12 is output. Therefore, the second frequency divider 7 has a frequency division ratio of 1/4 regardless of the "fluctuations" of the input signal IN.
Outputs n stable output signals OUT.

FIG. 9 is a block diagram of a phase control circuit showing a second embodiment of the present invention, and FIG. 10 is a diagram showing the correspondence between the averaged output and the frequency division ratio control signal in the decoder of FIG. As shown in FIG. 9, in comparison with the first embodiment described above, this embodiment uses three types of serial clocks: fm, fn, and fk (
fm=4×fn, fn=4×fk), and the rest are the same. Moreover, as shown in FIG. 10, this correspondence relationship is the correspondence between the control signal 11 of the filter output 10 as an input in the decoder 3 when there are three types of serial clocks, and the frequency division ratio control signal 12 as an output, and the next time A corresponding example of the control signal 11 output is shown below. That is, for A to G, when the control circuit output is "0", the fk clock is input to the second frequency divider 7, and for a to g, when the control circuit output is "1", fn=4×fk The clock shown in FIG. 1 is input to the second frequency divider 7. Similarly,
AA~GG is fm=16 when the control circuit output is "2"
This indicates that the clock of ×fk is input to the second frequency divider 7. It is assumed that 4k=n and 16k=m. In this way, if there are three types of shift clocks, (A
) to (G) show slow serial clock fk (=4×f
When phase control is performed with n), the control amount for one clock is four times that of fn in the first embodiment, so the tracking range becomes wider. By increasing the number of types of such shift clocks (clocks whose frequency is divided), it is possible to detect a wide and fine range of phase shift between the input signal IN and the output signal OUT. In other words, by changing the frequency division ratio according to the phase shift, it is possible to achieve fast pull-in time and highly accurate phase control. In addition, here, the selection of the frequency division ratio corresponding to the contents of shift register 1 is shown in FIG. 10 (A).
By making it nonlinear as shown in ~(G), the pull-in time is further shortened. Note that in the present invention, it is naturally possible to widen the tracking range by increasing the number of bits in the shift register 1.

[0026]

[Effects of the Invention] As explained above, the phase control circuit of the present invention detects the amount of phase shift using a shift register during phase comparison, and changes the amount of frequency division to several stages depending on the amount of phase shift. Since it is possible to select from among the following, there is an effect that the pull-in time can be shortened and highly accurate phase control can be realized. Furthermore, since the present invention allows the shift clock and the input clock of the frequency divider to be selected, even when the initial convergence or the phase suddenly shifts significantly, the serial clock with a lower frequency can be selected and the phase shift can be controlled. Since the output signal is obtained by dividing the frequency of the serial clock according to the amount, it is possible to obtain the effect that the pull-in time can be further shortened.

Furthermore, the present invention uses a filter including a register and an averaging circuit to absorb phase fluctuations and noise of the received signal, so that the tracking time is not delayed and the phase fluctuations and noise of the received signal are not tracked. In addition to being able to obtain an output signal with a stable phase, by selecting a shift clock, it is possible to realize stable phase control in response to the magnitude of fluctuation.

In short, according to the phase control circuit of the present invention, the pull-in time and tracking time are shortened, the tracking range is wide and resistant to noise and fluctuations, and a stable phase that is unaffected by fluctuations in the phase of the received signal is achieved. Since the clock can be outputted, the functionality of communication equipment can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a phase control circuit showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of the filter shown in FIG. 1.

FIG. 3 is a diagram showing the correspondence between the filter averaged output and the frequency division ratio control signal in the decoder of FIG. 1;

FIG. 4 is a transition diagram of input/output signals and a filter for explaining the operation of the filter in FIG. 1;

5 is a transition diagram of the filter when the output signal is delayed by two shift clocks with respect to the input signal, for explaining the operation of the filter in FIG. 1; FIG.

6 is a timing diagram of various input/output signals and a shift clock for explaining phase comparison in the shift register of FIG. 1. FIG.

7 is a timing chart of input/output signals and shift clocks for explaining the operation of the shift register at point C in FIGS. 1 and 4. FIG.

8 is a transition diagram of the filter for explaining the filter operation when the input signal in FIG. 1 has fluctuations; FIG.

FIG. 9 is a block diagram of a phase control circuit showing a second embodiment of the present invention.

10 is a diagram showing the correspondence between the filter averaged output and the frequency division ratio control signal in the decoder of FIG. 9; FIG.

FIG. 11 is a block diagram of a phase control circuit showing a conventional example.

12 is a timing diagram of input and output signals for explaining a phase comparison operation in the phase comparator of FIG. 11. FIG.

[Explanation of symbols]

1 Shift register 2 Filter 3 Decoder 4 Control circuit 5 First frequency divider 6 Selection circuit 7 Second frequency divider 8 Shift clock 9 Shift register output 10 Filter average output 11 Control signal 12, 13 Frequency division ratio control signal 14 First register 15 Second register 16 Averaging circuit 17 Register set signal IN Input signal OUT Output signal CLK Master clock

Claims (2)

[Claims] 1. A phase control circuit that creates an output signal whose phase is controlled with respect to an input signal, comprising: a multi-bit width shift register that inputs the input signal and shifts it using a shift clock synchronized with a master clock; and the shift register. a decoder that decodes the output of the filter and outputs a frequency division ratio control signal, a control circuit that outputs a control signal based on the output of the decoder, and the master clock. a first frequency divider that divides the frequency of the serial clock and outputs a plurality of serial clocks; a selection circuit that selects one of the serial clocks based on the control signal and outputs the shift clock to the shift register; a second frequency divider that divides the frequency of the shift clock from the circuit and outputs an output signal at a frequency division ratio according to a frequency division ratio control signal of the decoder output;
A phase difference amount between the output signal and the input signal is detected by the shift register, a shift clock of the shift register is selected according to the phase difference amount, and a frequency division ratio is selected according to the phase difference amount. A phase control circuit characterized by: 2. The phase control circuit according to claim 1, wherein the second frequency divider can vary a frequency division ratio to a plurality of values.