JPH0748720B2 - Phase control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit widely used in a receiver for digital communication, and more particularly to a phase control circuit that matches the phase of an internal clock with the phase of a received signal to obtain a stable phase. The present invention relates to a phase control circuit having a function of outputting a clock.

[Conventional technology]

In data transmission, the receiving side must extract information without error from the transmission waveform having jitter or noise sent from the other side. In serial transmission, data is sent serially bit by bit. Therefore, in order to extract the data from the transmission signal, it is necessary to find a bit boundary, that is, bit synchronization.

This synchronization technique is very important for transmission, and increasing the synchronization capability is a great force for improving transmission quality. PLL (phase locked loop) is useful for this.
Then, it is the automatic control regarding the phase. The purpose of the PLL is to match the phase of the internal clock with the phase of the received signal and to output a clock with a stable phase.

Therefore, in the PLL, the phase comparator detects the delay or advance of the rising timing of the internal clock with respect to the rising timing of the received signal.If it is delayed, the internal clock is advanced, and if it is advanced, the internal clock is delayed. Control is performed. However, if the internal clock is made to follow the temporary fluctuation of the phase of the received signal due to the "fluctuation" of the receiving system, it becomes impossible to obtain a clock having a stable phase. Therefore, the conventional PLL adds a filter to its constituent elements to absorb the "fluctuation" of the phase fluctuation and obtain a clock with a stable phase.

The structure of a conventional phase control circuit is shown in FIG. The operation will be described below with reference to FIG. In FIG. 4, the phase comparator 320 is a phase comparator for comparing the phases of the input signal 300 and the output signal 310 of the frequency divider 340.
Input signal 300 is logical "0" at the rising edge of output signal 310 of
Or outputs "1". The filter 330 is a filter that outputs a signal for changing the frequency divider to the frequency divider 340 according to the output of the phase comparator 320.The frequency divider 340 uses the output signal of the filter 330 to divide the frequency of the master clock 370. Is a frequency divider that changes. Upper limit designation signal 350 and lower limit designation signal 360
Is a signal designating the upper limit value and the lower limit value used by the counter in the filter 330, respectively. Output signal 310 is frequency divider 3
40 output signals.

The operation of the filter 330 will be described below. In the filter 330, +1 when the input from the phase comparator 320 is "1", "0"
There is an up-down counter that counts -1 when
The count value is the upper limit designation signal 350 or the lower limit designation signal 3
The comparison circuit in the filter 330 determines whether the upper limit value or the lower limit value designated by 60 is reached. Here, if the count value does not reach the upper limit value or the lower limit value, no processing is performed, but if the count value reaches the upper limit value or the lower limit value, the increase or decrease of the division ratio is specified. The signal is output to the frequency divider 340.

That is, in the filter 330, the up-down counter counts the cumulative number of phase shifts in the same direction, and when the counter reaches a predetermined value (the value specified by the upper limit designating signal 350 or the lower limit designating signal 360). For example, by increasing or decreasing the frequency division ratio, it is possible to reproduce a clock whose phase is stable.

The phase comparison between the input signal and the output signal of the frequency divider is performed as shown in FIG. For example, in the case where the denominator of the frequency division ratio is decreased by 1 when the phase of the output signal is accumulated three times behind the input signal, and the denominator of the frequency division ratio is increased by 1 when the phase of the output signal is advanced three times. It will be described below.

In FIG. 5A, in the phase comparator 320, at the point A, the input signal has a logical "0" at the rising edge of the output signal 310, so that the counter of the filter 330 counts -1. Even at the point B, the input signal has the logic "0" at the rising edge of the output signal, the counter further counts -1, and the counter indicates -2. Similarly at the point C, the input signal has a logic "0" at the rising edge of the output signal, and the counter of the filter 330 counts -1 and indicates -3. That is, point A, point B,
At point C, the phase of the output signal leads the input signal three times in total. The frequency division ratio of the frequency divider is increased by 1 by the output signal of the filter indicating that the phase has advanced three times in total. Therefore, the clock width of the signal output from the frequency divider becomes long, and the phase of the output signal approaches that of the input signal as indicated by point D. By repeating these operations, the input signal and the output signal are in a synchronized state.

In FIG. 5 (b), at the point E in the phase comparator, the input signal has a logic "1" at the rising edge of the output signal, so the counter of the filter counts +1. Even at the point F, the input signal has the logic "1" at the rising edge of the output signal, and the counter further counts by +1 and indicates +2. Similarly at point G, the input signal has a logic "1" at the rising edge of the output signal,
The counter counts +1 and indicates +3. That is, E
This means that the phase of the output signal is delayed with respect to the input signal three times at the points, F point and G point. The denominator of the frequency division ratio of the frequency divider is decreased by 1 by the output signal of the filter indicating that the phase has been accumulated three times. Therefore, the clock width of the signal output from the frequency divider becomes short, and the phase of the output signal approaches the input signal, as indicated by point H. By repeating these operations, the input signal and the output signal are in a synchronized state.

[Problems to be solved by the invention]

In the configuration of the conventional PLL described above, the magnitude of the phase shift cannot be detected in the phase comparison between the input signal and the output signal, and therefore the division ratio is increased or decreased according to a certain value regardless of the amount of the phase shift. . In this case, there are only three division ratios: increase by 1, no change, decrease by 1.
Therefore, the conventional PLL has a drawback in that the time from the unsynchronized state to the synchronized state, that is, the pull-in time becomes long. Further, since the frequency division ratio has only three stages of 1 increase, no change, and 1 decrease, the follow-up range is narrowed.

Also, if the frequency division ratio is N increased / no change / N decreased (N is a natural number of 2 or more), the pull-in time can be shortened and the tracking range can be widened, but the amount of jitter in the reproduced signal is said to be large. It has drawbacks.

Furthermore, in the configuration of the conventional PLL, since the filter is used, the operation of counting the number of times of phase shift detection is repeated regardless of the amount of phase shift, and only when the counter value reaches a predetermined value, the frequency division ratio Since the designation is made, it has a drawback that it takes time to follow up. Also, conventional PLL
When the filter is removed from the constituent elements of (1), the tracking time is shortened, but there is a drawback that the phase of the reproduced signal becomes unstable.

Therefore, in contrast to the configuration of the conventional PLL, the present invention uses a shift register at the time of phase comparison and decodes the contents of the shift register to measure the phase difference between the input clock and the clock applied by the PLL, and the phase difference In addition to outputting a signal designating the frequency division amount of the frequency divider according to the present invention, the present invention decodes the signals designating a plurality of frequency division amounts, so that the time required for tracking is not delayed. It has the original content of obtaining an output signal with a stable phase that is not affected by the "fluctuation" of the phase of the signal.

[Means for solving problems]

A phase control circuit of the present invention controls a frequency divider that divides a master clock and outputs a divided clock output signal, and outputs the divided clock output signal whose phase is controlled with respect to a clock input signal. In a phase control circuit for outputting a control signal for obtaining to the frequency divider, a shift of N bit width (N is a natural number of 2 or more) shifting with a shift clock which is input with the input signal and synchronized with the master clock. The contents of the shift register are decoded based on the register and the decode enable signal, and a selection signal that can change the frequency division ratio of the frequency divider so that the phase of the output signal matches the phase of the input signal is output. A decoder, and M from the decoder when the decode enable signal is generated based on the decode enable signal and the selection signal A fluctuation determination circuit that determines a fluctuation from an output (M is a natural number of 2 or more) and sends a control symbol that determines the change width of the frequency division ratio of the frequency divider to the frequency divider, and the frequency division circuit. The output signal of the converter and the master clock as inputs, and the decoder and the fluctuation determination circuit count the number closest to half the number of bits of the shift register in the master clock from the rise of the output signal, and then perform the decoding. And a decoder control circuit for outputting an enable signal.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, reference numeral 100 is an input signal, an output signal 170 is a clock obtained by applying a PLL to the input signal 100, and a shift register 120 is an input signal 100 and an output signal 170.
And the decoder 140 is a means for decoding the contents of the shift register 120, and the fluctuation determination circuit 150 determines the "fluctuation" of the phase of the input signal based on the output of the decoder 140. The frequency divider 160 is a means for dividing the master clock 180, and the frequency divider 160 is a frequency divider whose frequency division ratio is variable by the output of the fluctuation determination circuit 150.
Is a clock that is synchronized with the master clock 180, the decoder control circuit 130 receives the output signal 170 and the master clock 180 as input, and after counting the value of half of the number of shift register bits from the rising edge of the output clock with the master clock, Decode enable signal 13 for decoder
It is a means to output 1.

The operation of the present invention will be described with reference to FIGS. As an example, the case where the shift register 120 has 4 bits will be described. The input signal 100 and the shift clock 110 synchronized with the master clock 180 are input to the shift register 120, and the latched data is stored in the shift register 120. The output signal 170 and the master clock 180 are input to the decoder control circuit 130, and half the number of shift register bits (that is, 1 /
2) After counting the master clock 180, the decoder 140
A decode enable signal 131 is output to The decode enable signal 131 causes the decodecoder 140 to decode the contents of the shift register, and outputs a signal for selecting the frequency division ratio of the frequency divider 160 to the fluctuation determination circuit 150 according to the result of the decoding.

Here, the fluctuation determination circuit will be described. FIG. 3 shows a configuration example of the fluctuation determination circuit 150. 1-bit counter 2
10 is a counter that counts up in synchronization with the decode enable signal 131 (input from the terminal 153), and the selector 200 is a selector that specifies the transfer destination of the input signal from the decoder 140 (input from the terminal 151). ,counter
When 210 is 0, the register 220 is selected, and when the counter 210 is 1, the register 230 is selected. This allows register 220 and
Two continuous frequency division ratio designation signals are stored in 230. Further, the counter 210 has a decoder 2 when its value is 1.
Decode enable signal is output to 40. This decode enable signal causes decoder 240 to register 220
And decode the data input from the register 230,
A signal designating a final division ratio in consideration of “fluctuation” is output from terminal 152 to frequency divider 160.

The relationship between the input signal, the output signal, the master clock and the contents of the shift register is shown in FIG. 6 (a) and (b)
Is when the output signal leads the input signal,
FIG. 6 (c) shows a state where the output signal and the input signal are substantially synchronized, and (d) and (e) show a case where the output signal is delayed with respect to the input signal. By decoding the contents of these shift registers, the frequency division ratio designation signal before considering the "fluctuation" of the phase of the received signal is obtained.
Normally, it is assumed that the frequency division ratio of the frequency divider 160 is 1 / N, and the value of the shift register is, for example, (a), (b), (c) in FIG.
In the case of (d) and (e), the frequency division ratio designation signals by the decoder output are the following five types of frequency division ratios, 1 / (N + 2) / 1 / (N +
1) ・ 1 / N ・ 1 / (N-1) ・ 1 / (N-2) shall be specified. In both cases (a) and (b) of FIG. 6, the output signal leads the input signal in both cases. When the states shown in FIGS. 6 (a) and 6 (b) are reached, as the embodiment of the present invention, the frequency division ratio designating signal by the decoder output is
Since (N + 2) · 1 / (N + 1) is specified, if there is no “fluctuation” in the phase of the received signal, the division ratio 1 / (N +
2), 1 / (N + 1) is output as it is from the fluctuation discriminating circuit as a frequency division ratio designating signal, and the clock width of the output signal of the frequency divider becomes longer and the phases of the input signal and the output signal come closer. Further, since the frequency division ratio is larger in the case of the larger amount of phase shift (a), the clock width of the output signal becomes longer than in the case of (b), and it works to largely correct a large phase shift. . Further, in (c), since the input signal and the output signal are almost synchronized with each other, if there is no “fluctuation” in the phase of the received signal, the frequency division ratio is the same as in (a) and (b). Is 1 / N. Further, when the states (d) and (e) occur, the frequency division ratio designating signal by the decoder output is the frequency division ratio 1 / (N-1), respectively, as an embodiment of the present invention.
Since 1 / (N-2) is specified, if there is no "fluctuation" in the phase of the received signal, the division ratio 1 / (N-1) / 1 / (N-
2) is output as it is from the fluctuation determination circuit as a frequency division ratio designation signal, and the clock width of the output signal of the frequency divider is shortened, and the phases of the input signal and the output signal are close to each other. Further, since the frequency division ratio (e) having a larger phase shift has a larger frequency division ratio, the clock width of the output signal becomes shorter than that in the case (d), and a large phase shift is corrected. That is, the correction amount is changed according to the phase shift. Therefore, the pull-in time becomes short.

FIG. 7 shows the relationship between the frequency division ratio designated by the decoder and the frequency division ratio designated by the fluctuation determination circuit. The fluctuation determination circuit determines one frequency division ratio corresponding to a combination of two consecutive frequency division ratios obtained from the decoder, and designates one frequency division ratio. FIG. 7 shows an example of the correspondence table, but when the values of two consecutive division ratios are similar (for example, 1 / (N +
2) and 1 / (N + 1) or 1 / (N-2) and 1 / (N-1)
In this case), this is regarded as a phase shift and the frequency division ratio selected for the frequency divider is specified. When they are not similar (for example, 1 / (N + 2) and 1 / (N-2)), this is regarded as “fluctuation” of the phase of the received signal and the frequency division ratio 1 / Specify N. That is, the phase control circuit according to the present invention can output an output signal having a stable phase that is not affected by the "fluctuation" of the phase of the received signal without delaying the tracking time.

Next, a second embodiment will be described.

FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. This is the case when the shift register has 8 bits. When the shift register has 8 bits, the counter outputs a decode enable signal to the decoder after counting 4 clocks with the master clock at the same time when the output signal rises. If the shift register is set to 8 bits, the possible values for the shift register are 00H, 01H, 03.
There are 9 types of H, 07H, 0FH, 1FH, 3FH, 7FH, FFH, (H indicates hexadecimal notation), and the division ratio is 1 /
The range becomes wide from (N + 4) to 1 / (N-4). In this way, by increasing the number of bits of the shift register, the range of the phase shift between the input signal and the output signal can be detected in detail, and the frequency division ratio is changed according to the phase shift, so the pull-in time becomes faster. . However, in this case, the selection of the value of the frequency division ratio corresponding to the contents of the shift register does not necessarily have to be linear. For example, selection of the division ratio for the contents of the shift register as shown in FIG. 8 can be considered.

〔The invention's effect〕

As described above, in the present invention, the amount of phase shift can be detected using the shift register during phase comparison, and the frequency division amount can be selected from among several levels according to the amount of phase shift. This has the effect of shortening the withdrawal time. Also, the larger the number of bits of the shift register, the wider the tracking range as described in the second embodiment, and the higher the accuracy. Further, there is an effect that the pulling time can be shortened although the accuracy can be increased.

In the present invention, instead of the filter used in the conventional phase control circuit, a register and a decoder are used to decode several frequency division ratio specifying signals to detect the "fluctuation" of the phase of the received signal. Therefore, it is possible to obtain an output signal having a stable phase that does not follow the "fluctuation" of the phase of the received signal without delaying the tracking time.

In the phase control circuit, shortening the pull-in time to improve accuracy and outputting a clock with a stable phase that is not affected by "fluctuations" in the phase of the received signal are important for improving the functions of communication equipment. And, the effect is great.

[Brief description of drawings]

1 and 2 are block diagrams showing the configurations of the phase control circuits according to the first and second embodiments of the present invention, respectively.
FIG. 3 is a block diagram showing a configuration example of a fluctuation determination circuit according to the present invention, FIG. 4 is a block diagram showing a configuration of a conventional phase control circuit, and FIG. 5 is a time chart of a conventional phase comparison. FIG. 7 is a time chart of phase comparison according to the present invention, and FIG. 7 is a table showing the correspondence between the combination of two continuous frequency division ratio designation signals of the first embodiment and the frequency division ratio designated by the fluctuation discrimination circuit. FIG. 8 is a table showing the correspondence between the contents of the shift register of the second embodiment and the frequency division ratio designated by the output signal of the decoder. 120 ... 4-bit shift register, 130 ... Decoder control circuit, 140 ... Decoder, 150 ... Fluctuation determination circuit, 160
...... Divider, 190 …… 8-bit shift register.

Claims (1)

[Claims] 1. A frequency divider that outputs a divided clock output signal by dividing a master clock, and is for obtaining the divided clock output signal whose phase is controlled with respect to a clock input signal. In a phase control circuit for outputting a control signal to the frequency divider, a shift register having an N-bit width (N is a natural number of 2 or more) for inputting the input signal and shifting with a shift clock synchronized with the master clock, A decoder that decodes the contents of the shift register based on a decode enable signal, and outputs a selection signal that can change the frequency division ratio of the frequency divider so that the phase of the output signal matches the phase of the input signal; Based on the decode enable signal and the selection signal, M outputs from the decoder when the decode enable signal is generated (M is A fluctuation determination circuit that determines a fluctuation from the above natural number) and sends a control signal that determines the change width of the frequency division ratio of the frequency divider to the frequency divider, and an output signal of the frequency divider. The master clock is input to the decoder and the fluctuation determination circuit, and the decode enable signal is output after counting the number closest to half the number of bits of the shift register by the master clock from the rising of the output signal. A phase control circuit comprising a decoder control circuit.