JPS62122325A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit mechanism and to reduce a circuit scale by deciding to which of plural preset ranges a phase difference between a reproduced clock pulse and a data signal is included, and making the frequency dividing ratio of a variable frequency division circuit different from each said range. CONSTITUTION:An output pulse (a) of an oscillation circuit 1 is frequency-divided by a frequency division circuit 2 having a prescribed frequency division ratio and the result is fed to a variable frequency division circuit 3 and a window signal generating circuit 8 as a reference clock (b). A variable frequency division circuit 3 frequency- divides the reference clock pulse (b) by a frequency division ratio set by a frequency division ratio set circuit 4 to generate a recovered clock pulse c1. An input clock pulse (received data signal) (i) inputted from an input terminal 9 is fed to phase comparison circuits 5-7. Further, the recovered clock pulse c1 is fed to the phase comparison circuits, a window signal c2 from a window signal generating circuit 8 is fed to the phase comparison circuit 6 and a window signal c3 is fed respectively to the phase comparison circuit 7 respectively. A prescribed signal among these signals is selected in response to the frequency division ratio set by the variable frequency division circuit 3 and formed from the selected signal.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a phase-locked loop circuit suitable for use in cellular radios, etc., and in particular, it is capable of generating a regenerated clock pulse synchronized with a received data signal. This invention relates to a phase-locked loop circuit.

[Background of the invention]

For example, in digital data communication systems such as mobile radio systems, data signals are transmitted in a form in which clock pulses for data processing can be reproduced.
At the receiver, this clock pulse can be recovered from the received data signal. One method of regenerating this clock pulse is conventionally used, for example, in cellular radio equipment, by dividing the reference clock pulse from a crystal generator with high frequency stability using a variable frequency divider circuit. The frequency division ratio of the variable frequency divider circuit is increased or decreased according to the phase advance or lag of the data signal with respect to this clock pulse, and the clock pulse outputted by the variable frequency divider circuit is converted into a data signal. A known method is to use a phase-locked loop circuit that is synchronized to provide recovered clock pulses necessary for processing data signals.

In this phase-locked loop circuit, the frequency division ratio of the variable frequency divider circuit changes according to the lead or lag of the data signal with respect to the regenerated clock pulse, and the frequency and two phases of the regenerated clock pulse are changed so that both are synchronized. However,
Even after the two are synchronized, the frequency division ratio of the variable frequency divider circuit is not fixed, but if a certain frequency division ratio is set and the phase of the data signal with respect to the reproduced clock pulse advances and exceeds a predetermined amount, the frequency division will start. The ratio is changed so that the phase of the reproduced clock pulse advances, and when the phase of the data signal with respect to the reproduced clock pulse lags by a predetermined amount or more, the division ratio is changed again so that the phase of the reproduced clock pulse is delayed. There is. In this way, even if both are synchronized, the frequency division ratio changes, and in the end, the synchronized state of both is a state in which the average frequency and average phase of the reproduced clock pulse are synchronized with the data signal. Therefore, even if the two are synchronized, the reproduced clock pulse instantaneously causes a phase fluctuation (i.e., jitter) with respect to the data signal.

By the way, according to such a phase-locked loop circuit, in order to quickly draw the reproduced clock pulse into the data signal, it is necessary to increase the amount of phase change of the reproduced clock pulse due to frequency division by the variable frequency divider circuit. However, if this is done, the amount of jitter of the reproduced clock pulse in the synchronized state becomes extremely large, which causes problems in data signal processing.

Conversely, if the division ratio of the variable frequency divider circuit is determined so that the amount of jitter is small, the synchronization pull-in time of the reproduced clock pulse becomes longer.

In order to solve this problem, a technique is known in which the phase difference between the data and the reproduced clock pulse is detected and the frequency division ratio of the variable frequency divider circuit is changed in proportion to this phase difference. According to this technique, the frequency division ratio of the variable frequency divider circuit is set so that the larger the phase difference between the two, the more the phase of the reproduced clock pulse changes, thereby reducing the synchronization pull-in time. The frequency division ratio of the variable frequency divider circuit is set so that as the phase difference between the two becomes smaller, the amount of phase change of the reproduced clock pulse becomes smaller, and the amount of jitter of the reproduced clock pulse in the synchronized state becomes smaller. I have to.

However, according to such prior art, a counter circuit is used to detect the phase difference between the reproduced clock pulse and the data signal, and an up/down counter is used to determine the frequency division ratio according to this phase difference. Therefore, there was a problem that the circuit scale became large.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked loop circuit which solves the problems of the prior art, simplifies the circuit structure, and allows the circuit scale to be reduced.

[Summary of the invention]

In order to achieve this object, the present invention determines which of a plurality of preset ranges the phase difference between the reproduced clock pulse and the data signal falls in, and sets a variable amount for each range. By varying the frequency division ratios of the frequency dividing circuits, the larger the phase difference, the larger the amount of phase change of the reproduced clock pulse due to the frequency division of the variable frequency divider circuit, and the smaller the phase difference, the greater the phase change of the reproduced clock pulse. The feature is that the amount of phase change of the clock pulse is made small.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a phase-locked loop circuit according to the present invention, in which 1 is an oscillation circuit, 2 is a frequency divider circuit, 3 is a variable frequency divider circuit, 4 is a frequency division ratio setting circuit, 5 -7 are phase comparison circuits, 8 is a window signal generation circuit, and 9 is an input terminal.

In the figure, the oscillation circuit 1 is a crystal oscillation circuit, etc.
The oscillation frequency is very stable. The output pulse a of this oscillation circuit 1 is frequency-divided by a frequency divider circuit 2 having a constant frequency division ratio, and is supplied to a variable frequency divider circuit 3 and a window signal generation circuit 8 as a reference clock b. As will be described later, the variable frequency divider circuit 3 divides the reference clock pulse b using a frequency division ratio set by the frequency division ratio setting circuit 4, and generates a reproduced clock pulse c1. This reproduced clock pulse c1 is supplied to a data processing circuit (not shown).

On the other hand, the input clock pulse (
That is, the received data signal) i is the phase comparator circuit 5
~7. In addition, these phase comparison circuits 5 to 7 are supplied with the reproduced clock pulse c1 obtained by the variable frequency dividing circuit 3.
Further, the phase comparison circuit 6 is supplied with a window signal c2 from the window signal generation circuit 8, and the phase comparison circuit 7 is similarly supplied with a window signal c3.

Here, the window signal C2 is a signal that represents a phase range of ±π15 centered on the rising edge of the reproduced clock pulse c1 (it becomes “1” in this phase range), and the window signal c3 is a signal that also has a phase of ±π/2. This is a signal representing a range (it becomes "1" in this phase range). Such window signal c2. c3 can be formed in various ways, for example, it can be formed from the reference clock pulse b and the recovered clock pulse C1, or it can be formed from the variable frequency divider circuit 3 in response to the recovered clock pulse c1. Since signals of various phases can be obtained, a predetermined signal among these can be selected according to the frequency division ratio set in the variable frequency divider circuit 3, and the signal can also be generated from the selected signal.

The phase comparison circuit 5 compares the phases of the input clock pulse i and the reproduced clock pulse C1, and outputs two detection signals d and h. The detection signal d is a signal that becomes "O" when the phase of the input clock pulse l is equal to or leads the reproduced clock pulse c1, and becomes "1" when it lags behind the reproduced clock pulse c1. This signal is "1" when there is a change point (that is, a rising point, a falling point) of the input clock pulse i within one cycle of the input clock pulse i, and "O" when there is not.

The phase comparator circuits 6.7 phase the input clock pulse l and the reciprocating clock pulse c1, respectively, and further, No. 18 representing the phase difference between them is used as a window signal c2. It is determined whether it is within the period of "1" of c3. That is, when the signal representing the phase difference is within the "1" period of the window signal c2 (that is, when the rising edge of the input clock pulse i is centered on the rising edge of the reproduced clock pulse c1), When the detection signal e is within the phase range of ±π15), it becomes "0", and when it is not, it outputs the detection signal e that becomes "1". Similarly, when the rising edge of the input clock pulse i is within the phase range of ±π/2 centered on the rising edge of the recovered clock pulse C1, the phase comparator circuit 7 detects “
0", and if not, outputs a detection signal f which becomes "1".

The frequency division ratio setting circuit 4 receives these detection signals.

Upon receiving signals e and r, a frequency division ratio value g is generated and output in order to set the frequency division ratio in the variable frequency division circuit 3 according to the detection signals d, e, and f. The detection signal d is used to cause the variable frequency divider circuit 3 to advance or delay the phase of the reciprocating click pulse C1, and the detection signals e and f are used to cause the variable frequency divider circuit 3 to advance or delay the phase of the reproduced clock pulse C1. This is for determining the magnitude of phase change. In addition, the detection signal 1 indicates the presence or absence of a large clock pulse 5, and is '1' when the input clock pulse i is received, but when it is not received or is lost due to fading etc. Sometimes it is ``0''.

Here, when go is the center value of the frequency division ratio value g, and α is a positive constant and the change in the frequency division ratio value g, the detection signals d, e, f, h
An example of the frequency division ratio value g for the following table is shown below.

As is clear from the above table, when the detection signal RI is "0", the frequency division ratio value g of the variable frequency divider circuit 3 is held at the center value g0. Furthermore, when the detection signal d is "1" and the detection signal d is "0", the phase of the input clock pulse i is ahead of the reproduced clock pulse c1, so the division ratio value g
is smaller than the center value g0, and the reproduced clock pulse c1
By increasing the frequency of the regenerated clock pulse c
The phase of 1 is advanced to reduce the phase difference between the two. When the detection signal d is "1', the phase of the high-power clock pulse i is behind the reproduced clock pulse c1, so conversely, the frequency division ratio value g is made larger than the center value g0, and the reproduced clock pulse c1 is By lowering the frequency, the phase of the reproduced clock pulse cl is delayed and the phase difference between the two is reduced.

In this embodiment, the detection signals e and f determine the magnitude of the division ratio value g that differs from the center value go, depending on the magnitude of the phase difference between the input clock pulse i and the reproduced clock pulse c1. It's different. In the above table, when the phase of the input clock pulse i is within the range of ±π15 of the phase of the reproduced clock pulse c1, the division ratio value g is made to differ by ±α from the center value g0, If the phase shifts to the range of /2, the division ratio value g will be ± from the center value g0.
If the phase difference greatly differs by 2α and the phase shift exceeds ±π/2, the frequency division ratio value g will further greatly differ from the central value g0 to ±4α.

From the above, the larger the phase difference between the powerful clock pulse i and the reproduced clock pulse c1, the greater the frequency change of the reproduced clock pulse c1 by the variable frequency divider circuit 3, and therefore the larger the phase change.

Conversely, the smaller the phase difference, the smaller the phase change of the reproduced clock pulse c1.

Therefore, the temporal change in the phase difference between the large-power clock pulse i and the reproduced clock pulse C1 in this embodiment is shown in FIG. 2 when the initial phase difference is 3/4π. As is clear from the figure, in period A where the phase difference exceeds π/2, the division ratio value g becomes go-4α, so the phase difference decreases rapidly, and then the phase difference increases from π/2 to In period B, where π15, the frequency division ratio value g becomes go-2α, and the decreasing speed of the phase difference becomes 1/2 of that in period A. Then, when the phase difference becomes less than π15 (period c), the frequency division ratio value g becomes g,
-α, the change in phase difference becomes small, and a synchronized state is reached.

When the frequency division ratio value is changed in accordance with the phase difference in this manner, when the phase difference is large, the phase difference changes rapidly and the synchronization pull-in time can be shortened. Also, when the synchronization state is entered, the detection signal d is "l" while the detection signals a and f are "0".
, "O", and the division ratio (IIg is (go-α
) and (go+α). As a result, the phase of the reproduced clock pulse C1 is advanced or delayed, but
Since the amount of change α is small, the amount of change in this phase is small;
Therefore, the amount of jitter is sufficiently small.

Here, the phase comparator circuit 5 only detects the lead or lag in the phase of the input clock pulse i with respect to the reproduced clock pulse C1, and the change point of the input clock pulse i, so it requires a complex configuration and a large-scale counter circuit. It is not necessary to use the phase comparison circuit 6.7, and the same applies to the phase comparison circuit 6.7.

Roughly speaking, the frequency division ratio setting circuit 4 also receives detection signals of "1" and "0", d.

Since the frequency division ratio value g is generated and output using e and f, there is no need for an up/down counter as in the prior art described above.

Therefore, in this embodiment, the circuit configuration is simplified and the circuit scale is significantly reduced.

FIG. 3 shows a specific example of the phase comparator circuits 5 to 7 in FIG. ), 24 to 28 are inverters, and parts corresponding to those in FIG. 1 are given the same reference numerals.

FIG. 4 is a timing chart showing the operation of each circuit in FIG. 3, and signals corresponding to those in FIG. 3 are given the same symbols.

First, the phase comparator circuit 5 will be explained.

Input clock pulse i from input terminal 9 is D-FF10
．． It is supplied to the D (data) terminal of No. 11. In addition, the reproduced clock pulse c1 is inverted by the C (clock) terminal of D-FFII and the inverter 24, and is sent to D-F FIo,
12.13 is supplied to the C terminal. In D-FF10,
The rising edge of the inverted pulse version of the recovered clock pulse C1 (i.e., the rising edge of the recovered clock pulse C1)
The input clock pulse i is sampled and held every time, and the pulse 1 is obtained from its Q terminal. This pulse kl
The rising and falling edges of input clock pulse i are delayed until the falling edge of the next reproduced clock pulse C1.

This pulse 1 and the human clock pulse i are supplied to the ExOR gate 20 to generate a pulse 2. This pulse 2 is a pulse that rises at each rising edge and falling edge of the input clock pulse i, and falls at the next pulse 1 edge. This pulse 2 is supplied to the D terminal of the D-FF 12 and sampled and held every falling edge of the reproduced clock pulse C1.

By the way, when input clock pulse i exists,
2 is obtained as a pulse in which the period between the edge of the input clock pulse i and the edge of 1 in the next pulse is "1", and the falling edge of 2 in this pulse is due to the delay effect of the circuit, etc. Since it lags slightly behind the falling edge of C1, the detection signal obtained from the Q terminal of the D-FF 12 is always "1". On the other hand, when there is no input clock pulse i, the level of the input terminal 9 is held at "1", and as a result, the output of the Q terminal of the D-FFIO is always "1", and the ExOR gate 20 The output of 2 is always "O'". Therefore, the detection signal at this time becomes "0".

In this way, a detection signal indicating the presence or absence of the input clock pulse i is obtained.

In part, because the D-FFII samples and holds the input clock pulse i at every rising edge of the recovered clock pulse C1, the edge of the input clock pulse i from its Q terminal is delayed until the next rising edge of the recovered clock pulse C1. We get 3 on the pulse. 3 is D-F for this pulse
ExOR gate 2 along with 1 to the pulse obtained by FIO
1.

Now, as shown in the left part of FIG. 4, if it is assumed that the input clock pulse l is ahead in phase with respect to the reproduced clock pulse C1, then 3°kl is added to the pulse after the rise of the manual clock pulse i. Since it rises at the rising edge and falling edge of the regenerated clock pulse C1, the pulse
The rising edge of pulse 1 is ahead of the rising edge of pulse 1 by the "1" period of recovered clock pulse C1, and similarly, the falling edge of pulse 3 is ahead of the falling edge of pulse 1 of recovered clock pulse C1. Therefore, the pulse output from the ExOR gate 21 has a lead of "13" of the recovered clock pulse C1.
This is the same pulse that becomes "1" during the "period", that is, the reproduction clock pulse C1.

However, this pulse 4 is slightly delayed due to the delay effect of the circuit, so when this pulse 4 is sampled and held at the falling edge of the reproduced clock pulse C1 in the D-FF13, the "1 degree detection signal d" is You will get it.

On the other hand, when the input clock pulse i lags behind the recovered clock pulse C1, the pulse has a rising edge of 3 and a falling edge of the recovered clock pulse c1 has a 10 edge than a rising edge of 1 and a falling edge of the recovered clock pulse C1, respectively. ”
It will be delayed by a certain amount of time. For this reason, the pulse 4 output from the ExOR gate 21 becomes a pulse that becomes "1" during the "0" period of the reproduced clock pulse c1, that is, the inverted pulse of the reproduced clock pulse CI.

This inverted pulse d is also slightly delayed by the delay effect of the circuit, so when 4 is sampled and held in this pulse at the falling edge of the reproduced clock pulse C1 in the D-FF 13, a detection signal d of "0" is obtained. It turns out.

In this way, the phase comparator circuit 5 outputs a detection signal indicating the presence or absence of the input clock pulse i, and a phase advance of the input clock pulse i with respect to the reproduced clock pulse C1.
A detection signal d representing the delay is obtained.

Next, the phase comparator circuit 6 will be explained.

The manual clock pulse l applied to the input terminal 9 is D −
FF Supplied to D@ of F14.15. Also, ±π15 around the rising edge of the reproduced clock pulse cl.
The window signal c2, which becomes "1" in the phase range of , is supplied to the C terminal of the D-FF 15 and the C terminal of the D-FF 14 after being inverted by the inverter 25 . Therefore, in the D-FF 14, the input clock pulse i is sampled and held at every falling edge of the window signal C2, and rises at the falling edge of the window signal C2 after the rising edge of the high-power clock pulse i. 5 is obtained in the falling pulse at the falling edge of the window signal C2 after the falling edge. Also, D-F
In F15, the input clock pulse i is sampled and held every rising edge of the window signal C2, and rises at the rising edge of the window signal C2 after the rising edge of the input clock pulse l, and the window after the falling edge of the input clock pulse i is sampled and held. 6 is obtained for the falling pulse at the rising edge of signal C2.

Here, as shown on the left side of FIG. 4, when the edge of the input clock pulse i does not exist in the "1" period of the window signal C2 (that is, the phase of the input clock pulse l is π15 or more), the pulse has a rising edge of 6.

The falling edge leads in phase by the "1" period of the window signal C2 than the rising edge and the falling edge, respectively.

Therefore, 5. When 6 is supplied to the ExOR gate 22, 7 is obtained as a pulse that becomes "1" during the "L" period of the window signal C2. In other words, the pulse 7 is the same as the window signal C2. This pulse 7 is supplied to the D terminal of the D-FF 16, and the inverted pulse d of the reproduced clock pulse C1 by the inverter 26 is supplied to the C terminal. Therefore, the pulse 7 is sampled and held every rising edge of this inverted pulse εi, that is, every falling edge of the reproduced clock pulse C1, and a detection signal e of "1" is obtained from the D-FF 16.

On the other hand, when the edge of the input clock pulse i exists in the 1° period of the window signal C2 (that is, the phase of the input clock pulse i is ±
(within π15), the rising edge of window signal C2 is immediately before the edge of input clock pulse l, and the falling edge of window signal c2 is immediately after the edge of input clock pulse l, so D-FF14 outputs 5 pulses
The rising and falling edges of the window signal C2 are higher than the rising and falling edges of the pulse output from the D-FF 15, respectively.
It advances by the period from the falling edge of to the next rising edge.

For this reason, the pulse 7 obtained from the ExOR gate 22 becomes "Om" during the "1" period of the window signal C2, and becomes "11" during the other periods, that is, the inverted signal of the window signal C2. Therefore on this pulse? GD-FF1
By sampling and holding the falling edge of the regenerated clock pulse C1 at 6, the signal from the blue terminal to “0°
A detection signal e is obtained.

In this way, the phase comparison circuit 6 adjusts the phase of the input clock pulse i to ±π15 of the phase of the reproduced clock pulse cl.
A detection signal e is obtained which is 1'' when the value is outside the range of , and 0 when it is within the range.

The phase comparator circuit 7 has the same configuration and the same operation as the phase comparator circuit 6, except that the window signal C3 becomes "1" within a range of ±π/2 around the rising edge of the reproduced clock pulse CI. Since it is only different from the window signal C2, as explained earlier, when the phase of the high-power clock pulse l is in the range of ±π/2 of the phase of the reproduced clock pulse c1, it is "1".
, and the detection signal f becomes “0” when within that range.
is obtained.

As described above, there is no need to use a counter circuit in the phase comparator circuits 5 to 7.

FIG. 5 is a circuit configuration diagram showing a specific example of the frequency division ratio setting circuit 4 in FIG.
is an output terminal, and 41 to 46 are changeover switches.

In the figure, this specific example has phase comparator circuits 5 to 7 (
Detection signals from FIGS. 1 and 3), d.

e and f, the frequency division ratio value go shown in the table above.

It is assumed that either g0±α9g・±2α+go ±4α is generated. For this purpose, this specific example is comprised of six changeover switches 41-46.

The changeover switch 41 is controlled by the detection signal input to the input terminal 29. When the detection signal is "1", it closes to the side near the "1" side to which the changeover switch 42 is connected, and when it is "0", it closes. , division ratio value g.

It closes to the piece near the "0" side that is read directly to the input terminal 33 where is input.

The changeover switch 42 is controlled by the detection signal d input to the input terminal 30. When the detection signal d is "0", it closes to the "0" side piece to which the changeover switch 43 is connected, and when it is "1", it closes. , to which the selector switch 44 is connected.
1” Close to the lateral piece.

The changeover switches 43 and 44 are controlled by the detection signal f input to the input terminal 31, and the respective detection signals f are "
When it is "0", it closes to the "0" side piece, and when it is "1", it closes to the "1" side piece. "0" of the changeover switch 43
The side piece is connected to the changeover switch 45, and the “1” side piece is connected to the input terminal 34 to which the frequency division ratio value (go+4α) is input. Further, the piece near the “0” side of the changeover switch 44 is connected to the changeover switch 46, and the piece beside the “1” side is connected to the division ratio value (go
4α) are connected to input terminals 35, respectively.

The changeover switches 45 and 46 are controlled by the detection signal e input to the input terminal 32, and the detection signal e is "
When it is "0", it closes to the "0" side piece, and when it is "1", it closes to the "1" side piece. Further, the piece near the "0" side of the changeover switch 45 is the frequency division ratio value (g).

+α) is input to the input terminal 36, the piece on the “1” side is connected to the input terminal 37 to which the division ratio value (go+2α) is input, and the piece on the “0” side of the changeover switch 46 is connected to the input terminal 36 for the frequency division ratio. The "1" side piece is connected to the input terminal 38 to which the ratio value (go-α) is input, and the input terminal 39 to which the frequency division ratio value (go 2α) is input.

With this circuit configuration, the detection signals d, f.

The frequency division ratio value g inputted from the input terminals 33 to 39 is selected according to the signal e, and is sent from the output terminal 40 to the variable frequency division circuit 3 (FIG. 1). This selection based on the detection signals d, e, and f is
Needless to say, follow the table above.

As the variable frequency divider circuit 3 (FIG. 1) for the frequency division ratio setting circuit 4, for example, a circuit such as a programmable counter whose frequency division ratio can be changed by the frequency division ratio value g is used.

FIG. 6 is a block diagram showing another specific example of the variable frequency divider circuit 3 and the frequency division ratio setting circuit 4 in FIG.
8 is an OR circuit, 49.50 is an AND gate, 51 is a frequency dividing circuit, 52, 53, 56 is an inverter, 54.55 is a variable pulse generation circuit, and the parts corresponding to FIGS. 1 and 5 are They are given the same code.

In FIG. 6, the variable frequency divider circuit 3 includes OR circuits 47, 4
B, AND game) 49.50, frequency divider circuit 5 with constant frequency division ratio
1 and inverters 52 and 56.

The reference clock pulse b output from the frequency dividing circuit 2 is output from the OR circuit 47. The signal is supplied to the frequency dividing circuit 51 via the AND gate 49. The OR circuit 47 adds the pulse m2 from the AND gate 50 to the reference clock pulse b in accordance with the detection signals d, f, and e from the input terminals 29 to 32. Pulse m1 supplied to 51
increases, and the frequency division ratio value of the variable frequency divider circuit 3 equivalently decreases. Further, the AND gate 49 has input terminals 29 to 32.
Detection signal from

The output pulses of the OR circuit 47 are thinned out according to d, f, and e, and as a result, the pulse ml supplied to the frequency divider circuit 51 is reduced, and the frequency division ratio of the variable frequency divider circuit 3 is equivalently reduced. The value increases.

The AND gate 50 receives the detection signal from the input terminal 29.

It is turned on by the signal J obtained by inverting the detection signal d from the input terminal 30 by the inverter 56 and the pulse m5 output by the variable pulse orderer 54 of the frequency division ratio setting circuit 4.

It is controlled off and passes the output pulse a of the oscillation circuit l.

Cut off. The OR circuit 48 also receives an inverted signal π obtained by inverting the detection signal R by the inverter 52, an output signal J of the inverter 56, and an output pulse of the variable pulse generator 55 in the frequency division ratio setting circuit 4. The AND gate 49 is turned off and the output pulse of the OR circuit 47 is cut off during the period during which the pulses m4 obtained by inversion at 53 are supplied and these pulses are simultaneously "0".

Here, assuming that the frequency division ratio value g of the variable frequency divider circuit 3 is set as shown in the table above, only the reference clock pulse b is applied to the OR circuit 47. Passes through AND gate 49 and pulse m1
The variable frequency divider circuit 3 when supplied to the frequency divider circuit 51 as
The frequency dividing circuit 51
The frequency division ratio is set.

The frequency division ratio setting circuit 4 includes an inverter 53 and variable pulse generators 54 and 55. The variable pulse generator 54 is supplied with the reproduced clock pulse -CI and the detection signals f and e,
It rises at the falling edge of the reproduction clock pulse cl, and generates and outputs a pulse m5 of "1" whose pulse width differs according to the detection signals f and e. The pulse width of this pulse m5 is
It is narrowest when both detection signals f and e are "0", wider when detection signal f is "0" and detection signal e is "1", and when both detection signals f and e are "1", it is narrowest. Sometimes the widest.

Similarly, the variable pulse generator 55 is also supplied with the reproduced clock pulse C1 and the detection signals f and e, and the impark 5
3, it falls at the falling edge of the reproduced clock pulse cl, and generates and outputs a pulse m4 of "0" whose pulse width differs according to the detection signals f and c. The pulse width of this pulse m4 is also the detection signal f.

It is narrowest when both e are “0”, and both are “1”.
However, while the pulse width of pulse m5 is an integer multiple of the period of the output pulse a of the oscillation circuit 1, the pulse width of pulse m4 is much wider than this and is an integer multiple of the period of the reference clock pulse b. It's double.

Next, the operation of this specific example will be explained using the timing charts of FIGS. 7 and 8.

First, when the detection signal from the input terminal 29 is “O” (
That is, when there is no input clock pulse i), as shown in area A of FIG. 47 passes only the reference clock pulse b. Furthermore, since the inverted signal π of the detection signal is "1", the output signal m3 of the OR circuit 48 is always "1",
The AND gate 49 is turned on and the reference clock pulse b output from the OR circuit 47 is passed through. This reference clock pulse b is supplied to the frequency dividing circuit 51 as a pulse m1, and a reproduced clock pulse C1 which sets the frequency dividing ratio value of the variable frequency dividing circuit 3 to g is obtained.6 Next, the detection signal R becomes "1". The case where the detection signal d is "l" will be explained below.

When both detection signals f and e are “1” (i.e.,
Input clock pulse l with respect to recovered clock pulse C1
(when the phase of is assumed to be four synchronized portions of the reference clock pulse b.

In this case, since the detection signal 1d is "l", the output 1 of the inverter 56 becomes "0", and the AND gate 50
is turned off, the output signal m2 is held at "0", and the OR circuit 47 passes only the reference clock pulse b. On the other hand, the output signal m3 of 08 times 84B is “
During this "0" period, the AND gate 49 is turned off, and four reference clock pulses b are deleted after the falling edge of the reproduced clock pulse C1.The output pulse m1 of the AND gate 49 is The period of the reproduced clock pulse cl obtained at this time is greater than that of the reference clock pulse b when the frequency division ratio value g is g6.
It becomes longer by 4 cycles. The frequency division ratio value g of the variable frequency divider circuit 3 at this time is g0+4α. Therefore, the frequency of the reproduced clock pulse CI becomes low, and its phase gradually lags and approaches the phase of the input clock pulse i.

When the detection signal e is "1" and the detection signal f is "0" (that is, when the phase of the input clock pulse i is delayed between π15 and π/2 with respect to the reproduced clock pulse cl), the above However, as shown in area C of FIG. 7, the pulse width of pulse m4 is narrower than the above. Here, if this pulse width is equal to two periods of the reference clock pulse b, the period of the reproduced clock pulse C1 is 2 periods of the reference clock pulse b than when the division ratio value g is go.
The cycle becomes longer. Frequency division ratio value g of variable frequency divider circuit 3 at this time
is g0+2α.

Similarly, when the detection signals e and f are both "0" (that is, when the phase of the manual clock pulse i is delayed by π15 or less with respect to the reproduced clock pulse C1),
As shown in the area of FIG. 7, assuming that the pulse width of pulse m4 is one period of reference clock pulse b, the period of the resulting reproduced clock pulse C1 is the division ratio value g7'J<g
It is longer by 1 period of the reference clock pulse b than when it is o.

At this time, the frequency division ratio value g of the variable frequency divider circuit 3 is g0+α.

Next, a case where the detection signal ri is "1" and the detection signal d is "0" will be explained.

In this case, since the output signal 1 of the inverter 56 is "1", the output signal m3 of the OR circuit 48 is also "1", and the AND gate 49 is held in the on state. Also, A
The ND gate 50 is turned on only during the period of the "1" pulse m5 from the variable pulse generator 54, and allows the output pulse a of the oscillation circuit 1 to pass during this period.

Therefore, when the detection signals e and f are both "1 degree" (that is, when the phase of the input clock pulse i is ahead of the reproduced clock pulse cl by more than π/2), the area shown in FIG. As shown at A, a variable pulse generator 54
The pulse width of the “1” pulse m5 from the AN
Passes D date 50 and outputs it as pulse m2 to OR circuit 47
is added to the reference clock pulse b. As a result, the frequency dividing circuit 51 also counts the four added pulses, so the period of the reproduced clock pulse c1 is shorter by four periods of the reference clock pulse b than when the frequency division ratio value g is go. . The frequency division ratio value g at this time is go 4α,
As a result, the phase of the reproduced clock pulse c1 advances and approaches the phase of the input clock pulse i.

Even when the detection signal e is "L" and the detection signal f is "O" (that is, when the phase of the input clock pulse i is ahead in the range of π15 to π/2 with respect to the reproduced clock pulse (142)) Similarly, as shown in region B of FIG.
The pulse width of pulse m5 is narrower, and assuming that this is two periods of pulse a, the period of the reproduced clock pulse C1 obtained from the frequency dividing circuit 51 is shorter than that of the reference clock than when the frequency division ratio value g is g. It becomes shorter by two periods of pulse b. The frequency division ratio value g at this time is go 2α.

Similarly, when the detection signals e and f are both "O" (that is, when the phase of the input clock pulse i leads the reproduced clock pulse C1 by π15 or less),
As shown in area C in FIG. 8, the pulse width of pulse m5 becomes even narrower, and if this is taken as one period of pulse a, then
The period of the resulting reproduced clock pulse C1 is narrower by one period of the reference clock pulse b than when the frequency division ratio value g is go. The frequency division ratio value g at this time is go-α.

As described above, in the above embodiment, there is no need to use a counter in the phase comparison means or the division ratio setting circuit for detecting the phase difference between the input clock pulse and the reproduced clock pulse.

Note that the numerical values used in the above examples (such as the division ratio value and the boundaries of the phase difference range related to the division ratio value, ±π/2, ±π15, etc.) are merely examples, and any other values may be used. Needless to say, the number of phase difference ranges is not limited to seven as shown in the table above; the larger the phase difference, the larger the amount of phase change. , it may be any other number.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need to use counters for phase difference detection or frequency division ratio setting, and it is possible to significantly shorten synchronization pull-in time and significantly reduce jitter. Simplified configuration.

It is possible to provide a phase-locked loop circuit that is downsized and has excellent functionality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase-identical loop circuit according to the present invention, FIG. 2 is an explanatory diagram showing changes in the phase difference between an input clock pulse and a reproduced clock pulse in this embodiment, and FIG. The figure is a circuit configuration diagram showing an example of each phase comparator circuit in FIG. 1, FIG. 4 is a timing chart showing the operation of each phase comparator circuit shown in FIG. 3, and FIG.
FIG. 6 is a circuit configuration diagram showing an example of the frequency division ratio setting circuit in FIG. 1, FIG. 7 and 8 are timing charts showing the operation of the specific example shown in FIG. 6, respectively. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2... Minute P1 circuit, 3... Variable frequency divider circuit, 4... Frequency division ratio setting circuit, 5-6... Phase comparison circuit, 8... Window signal Generation circuit, 9...input terminal. Agent Patent Attorney Takeshi Kenjibe (1 other person) Fig. 1 Fig. 3 cl c2 c3 Fig. 4 i/1 Fig. 5 Fig. 6

Claims (1)

[Claims] A variable frequency dividing means for frequency dividing a reference clock pulse, and a frequency division ratio setting means for setting a frequency division ratio of the variable frequency dividing means,
In a phase-locked loop circuit capable of obtaining a recovered clock pulse synchronized with a data signal received from the variable frequency dividing means, a first means for detecting a phase relationship between the recovered clock pulse and the data signal. and second means for detecting in which of the ranges a plurality of different ranges are set in advance and the phase difference between the reproduced clock pulse and the data signal is included; A phase-locked loop circuit characterized in that the frequency division ratio setting means sets the frequency division ratio of the variable frequency division means based on the output of the means.