JPS61225926A - Digital logic pll circuit - Google Patents

Abstract

PURPOSE:To decrease the phase error of an input signal by controlling the frequency dividing ratio of a variable frequency divider in response to the output value of a data processing circuit adding phase difference levels. CONSTITUTION:When the edge point of a digital signal comes, the relation of phase is set to flip-flops 7-10 and the phase difference data is converted into binary codes A-C by a gate circuit GC 2. The phase difference data (a)-(c) generated by preceding edge information are latched to FFs 11-13 and a value dividing the result of addition of the phase difference data A-C at an adder ADD by 2 is outputted. The output is fed to an AND gate G15 and a NAND gate G16 via a gate circuit GC3. Outputs -GT, +GT of the gates G15, G16 are fed to the gate circuit GC1 of a variable frequency divider 12 as a frequency division ratio control signal. Thus, the phase error of the input signal is decreased.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital logic PLL (phase locked loop) circuit composed only of digital logic circuits, and in particular, detects a phase difference signal detected by phase comparison. It relates to products that have been improved so that components can be removed.

[Technical Background of the Invention] In recent years, there has been a tendency to adopt digital control methods for various devices, and in order to achieve high-density recording and playback, especially in information recording and playback systems, most of them are becoming digital recording and playback methods. . In order to reproduce correct digital data from recorded or transmitted digital information signals, these various digital control systems include channel bit recovery (PLGK), which separates bits in the first processing section. ) is provided. This PLL circuit generally compares the phase of input phase information with a clock from an oscillator (actually, a voltage-controlled oscillator VCO), and controls the oscillation frequency of the oscillator by passing the phase difference information through a low-pass filter. It is constructed by forming a loop to achieve phase locking.

Incidentally, as system circuits are increasingly integrated into ICs, PLL circuits with digital logic configurations suitable for integration into ICs have also appeared. As shown in FIG. 6, this digital logic PLL circuit generates a master clock Cpa+ having a frequency that is an integral multiple of the channel bit frequency by using a master clock generator 11 instead of C0, and makes the clock variable. A channel pit clock PLCK is generated through a frequency divider 12, and the clock PLCK from the frequency divider 12 and input phase information DRF are passed to a phase comparator 13.
A loop is formed so that the phases are compared and the phase difference information □out is passed through the timing control circuit 14 to control the frequency division ratio of the frequency divider 12, thereby locking the phase.

[Problems with background technology] However, the conventional digital logic P as described above
In the LL circuit, if a general PLL circuit is digitized as it is, the circuit becomes complicated, so the phase comparison only detects the lead/lag, and the variable frequency divider also changes the division ratio to 1/1.
In many cases, it is set to about (N±1).

On the other hand, for example, digital recording and reproducing systems generally have a seventh
As shown in the above, the digital signal is modulated to the recording medium 21.
The modulated signal RF is read out from this recording medium 21 using a pickup 22 or the like, and the data slice circuit 23
The first digital data can be played.

However, since the modulated signal RF is a signal that passes through a finite band, the DC level fluctuates due to the low frequency component of the information signal itself. Converting such a signal RF to a binary signal and converting it to P
A data slicing circuit 13 is provided to send data to the LL circuit 24, but since the slicing level actually changes due to the fluctuation of the DC level, slicing is performed at a point deviated from the optimum value. In other words, as shown in FIG. 8, the slice level is V with respect to the modulated signal RF.
1, V2, and V3, the digital signal DRF binarized by the data slice circuit 23 changes as DI, D2, and D3, respectively, and is sent to the PLL circuit 24 with incorrect phase information added. It will be done.

Therefore, a phase error occurs before the input to the PLL circuit due to fluctuations in the slice level, so in a digital logic PLL circuit that performs phase control without passing through a sufficient filter, the phase cannot be controlled beyond the correct phase shift. As a result, an accurate channel pit clock cannot be obtained.

[Object of the Invention] This invention was made to improve the above-mentioned problems, and provides a digital logic PLL circuit that can reduce the phase error of an input signal and generate a highly accurate channel pit clock. The purpose is to

[Summary of the Invention] That is, the digital logic PLL circuit according to the present invention generates a synchronous clock based on a digital signal obtained by inverting and modulating a digital information signal at maximum and minimum polarity inversion intervals, in which the synchronous clock frequency is a master clock generator that generates a master clock having a frequency that is an integral multiple of , a variable frequency divider that divides the master clock and whose division ratio can be arbitrarily varied, and an output of the variable frequency divider. and the digital signal; a delay circuit that delays the phase difference level obtained by the phase comparator by one phase comparison; and a phase difference level from the delay circuit and the phase difference level from the phase comparator. a data processing circuit that adds the phase difference level; and a timing for shifting the phase of the frequency-divided clock and synchronizing it with the digital signal by controlling the frequency division ratio of the variable frequency divider according to the output value of the data processing circuit. The device is characterized in that it includes a control circuit.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5. However, in FIG. 1, the same parts as in FIGS. 6 and 7 are denoted by the same reference numerals, and only the different parts will be described here.

FIG. 1 shows its basic configuration, in which a digital signal D from the data slice circuit 23 (not shown here) is shown.
The phase of RF is compared with the channel pit clock PLCK from the variable frequency divider 12 by the phase comparator 13.

The phase difference signal obtained here is output as a data signal [) out together with the channel pit clock PLCK to the demodulation circuit 25 (not shown here) and is also supplied to the delay circuit 16. The delay circuit 16 delays the phase difference signal by one phase difference and outputs the delayed signal [)n-1, which is supplied to the data processing circuit 17 together with the phase difference signal []n before the delay. This data processing circuit 17 adds the two human forces Dn-1 and Dn, and controls the timing setting of the timing control circuit 14 based on the addition result. That is, the frequency division ratio of the variable frequency divider 12 controlled by the timing control circuit 14 is set based on the currently output phase difference signal and the previous phase difference signal.

FIG. 2 shows its specific circuit configuration, in which the data slice circuit 23 has an analog level comparator 23.
It is composed of an a, o-pass filter (LPF) 23b and two inverters 23c and 23d, and the slice level is obtained by integrating the output of the comparator 23a with a low-pass filter 231).

The phase comparator 13 is composed of an edge detection circuit consisting of a flip 70-tube FF1 and an exclusive OR gate (hereinafter referred to as EX-OR gate) G1, and the data signal Dout is supplied from the non-inverting output terminal Q of the flip-flop FF1. can get.

The output of EX-OR gate G1 becomes edge information of the input signal.

The variable frequency divider 12 has flip 70 tubes FF2 to FF5.
It is a so-called Johnson counter. It becomes. In other words, the master clock Cp from the master clock 9 generator 11 is generated by FF2 to FF5.
Variably divide m by 1/(8±1). Further, the frequency division ratio control timing is set by FF6 and GCl. Then, by FF6 to FF9, the frequency division output of FF2 to FF5 and the input edge phase (phase comparator 13f7) EX-OR
The result of phase comparison with gate Gl (D output 5TP) is latched. The above channel pit clock PLCK is FF
It is obtained from the non-inverting output Q of I.

The delay circuit 15 is composed of a gate circuit GC2 consisting of gates G7 to G10 and a register section consisting of 70 flips FF11 to FF13. In other words, gate circuit G
The outputs of FF7 to FF10 are converted into binary codes by C2, and the current phase comparison result codes A, B,
Generate a C signal. Further, signals a, b, and c, which are codes of the previous phase comparison result, are stored by FF11 to FF13.

The data processing circuit 16 is composed of a 3-bit full adder ADD and a gate circuit GC3 consisting of gates G11 to Q14. That is, the 3-bit full adder ADD adds code data A-C representing the current phase comparison result and code data a-C representing the previous phase comparison result. Then, the gate circuit GC3 detects the phase lead/lag from the output of the adder ADD.

The timing control circuit 14 includes a flip-flop FF14 and a gate G15. It is composed of a gate circuit GC4 made of G16. That is, the control timing of the variable frequency divider 12 is set by l"l"14, and the variable amount of the frequency division ratio is controlled by the gate circuit GC4.

The operation of the above configuration will be described below with reference to the timing charts shown in FIGS. 3 to 5.

First, it is assumed that a lock PLCK as shown in FIG. 3 can be obtained by dividing the master clock Cpla from the master clock generator 11 by the FF2. It is also assumed that the data slice circuit 23 is supplied with a digital signal RF that is modulated by inversion at an interval of n times the modulation channel bit (n is an integer and has multiple values) as shown in the figure. . This digital signal RF is sent to the comparator 23a, sliced at the DC level of the digital signal RF obtained by the low-pass filter 23b, and binarized. This binary signal is sent to inverters 23c, 23
The digital signal DR whose waveform is shaped by d and shown in the same figure
It becomes F.

This digital signal DRF is transmitted to FF1 of the phase comparator 13.
It is synchronized with LCK and taken out as a data signal oout. Further, as shown in the figure, the rising and falling information is transmitted to the rising edge of the output STP of the EX-OR gate G1. At this time, the Q output of the FF 14 of the timing control circuit 14 is as shown in the figure.

The output STP of the above EX-OR gate G1 is FF1 to FF
It is supplied to each clock input terminal of l0. In other words, this S
The frequency division contents of FF2 to FF5 are changed to FF7 to F by the TP signal.
Set to F10. Through this operation, the input phase and the frequency-divided phase are compared, and the phase difference level thereof is detected.

The outputs of the FF7 to FF10 are supplied to the gate circuit GC2. This is because since the variable frequency divider 12 is a Johnson counter, it is easier to use it if the phase difference detection data is converted into a binary code. For example, the above F
When the data of FF2 to FF5 is code-converted when the D input and Q output of F7 to FF10 become free paths, code data A, B, and C as shown in FIG. 4 are obtained.

Here, since the input signal DRF uses the falling edge of the Q output of FF2 as the synchronization point, as is clear from FIG. When it is 2,4, it is considered to be +1.5, it is considered to be +2. Code A obtained by this gate circuit GC2,
B and C are latched by FF11 to FF13.

Now, when the edge point of the digital signal DRF arrives, the phase relationship at that time is set in FF7 to FFl0, and the phase difference data is converted into binary codes A, B, and C by the gate circuit GC2.

On the other hand, phase difference data generated by the previous edge information is latched in FF11 to FF13. Therefore, the phase difference data a, b, c of FF11 to FF13
and phase difference data A of FF7 to FF10.

Bl is added by an adder ADD. This adder ADD outputs a value obtained by dividing the addition result by two. The output data of this adder ADD is supplied to an AND gate G15 and a Nant gate G16 through a gate circuit GC3.

That is, when the output data of the adder ADD is 3 or 4, the gate G15. Each output of G16 -GT, +G
T is at the "0" level, when it is 5 or more, -GT is at the 1" level, and when it is 2 or less, +GT is at the "1" level. Here, the above-mentioned AND gate G15 and Nant gate G
The output timing of FF16 is determined by the Q output of FF14. As shown in FIG. 3, the Q output of the FF 14 is a one-cycle timing signal obtained by setting the STP signal with PLCK.

The outputs -GT and +GT of the gates G15 and G16 are supplied to the gate circuit GC1 of the variable frequency divider 12 as frequency division ratio control signals. In other words, the variable frequency divider 12 does not vary the frequency division ratio (1/N) when the frequency division control signals -GT and +GT are both 0", and lowers the frequency division ratio when -GT is "1". (1
/N-1>, when r is 1", the frequency division ratio is increased (1/N+1). This frequency division ratio control signal -GT
, +GT shows an example of the control timing of the variable frequency divider 12.

To explain the practical operation, digital signal DRF
Suppose that the falling edge of is entered at position "4" in FIG. 4, and the preceding rising edge is entered at position "1" in the same figure. Adding these together and dividing the result by 2 gives 2.5. Therefore, the phase of PLCK is equal to the input signal D.
It is assumed that there is a delay with respect to RF, and the frequency division ratio control signal -G
T is generated and the division ratio of the variable frequency divider 12 is set to 1/7 only once.
to advance the phase. 2. In this case, as shown in FIG. 8, the slice level is considered to be somewhat low. Also, the detection level at a certain point is "5" in Figure 4,
If the previous one is "2" in the figure, adding these and dividing by 2 gives 3.5, so -GT and +GT are "0", and the variable frequency divider 12 is Do not change the division ratio. This is because the slice level is considered to be incorrect. In other words, if the phase is controlled when the slice level is incorrect, the clock width will become too small and performance will deteriorate.

Therefore, the digital logic P configured as above
Even if a phase error occurs due to fluctuations in the slice level before its input, the LL circuit can determine the phase difference component due to this error and control the frequency division ratio of the variable frequency divider, so it can generate accurate channel bit clocks. can be generated.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a digital logic PLL circuit that can reduce the phase error of an input signal and generate a highly accurate channel bit clock.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram showing an embodiment of a digital logic PLL circuit according to the present invention, FIG. 2 is a circuit diagram specifically showing the circuit configuration of the embodiment, and FIGS. 2 is a timing chart for explaining the circuit operation, FIG. 6 is a block circuit diagram showing the configuration of a conventional digital PLL circuit, FIG. 7 is a configuration diagram of a digital recording and reproducing system using the above PLL circuit, and FIG. The figure is a timing chart for explaining a phase change due to slice level fluctuation of a PLL circuit input signal. DESCRIPTION OF SYMBOLS 11... Master clock generator, 12... Variable frequency divider, 13... Phase comparator, 14... Timing control circuit, 15... Delay circuit, 16... Data processing circuit, 21 ...Recording medium, 22...Pickup, 23...Data slice circuit, 24...PL
L circuit, 25... demodulation circuit, Cp-... master clock, PLCK... channel bit clock. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 8

Claims (1)

[Claims] In a digital logic PLL circuit that generates a synchronous clock based on a digital signal obtained by inverting and modulating a digital information signal at maximum and minimum polarity inversion intervals, a master clock that generates a master clock having a frequency that is an integral multiple of the synchronous clock frequency. a generator; a variable frequency divider that divides the master clock and whose frequency division ratio can be arbitrarily varied; and a phase comparator that compares the phase of the output of the variable frequency divider and the digital signal; a delay circuit that delays the phase difference level obtained by this phase comparator by one phase comparison; a data processing circuit that adds the phase difference level from this delay circuit and the phase difference level from the phase comparator; A digital logic P characterized by comprising: a timing control circuit that shifts the phase of the frequency-divided clock and synchronizes it with the digital signal by controlling the frequency division ratio of the variable frequency divider according to the output value of the processing circuit.
LL circuit.