JPS61227270A - Data strobe circuit - Google Patents

Abstract

PURPOSE:To prevent produce phase error from giving an influence to a bit synchronous clock produced in a PLL circuit by providing a data slice circuit, the first and the second phase synchronous loops, the first and the second frequency dividers, a synchronous signal detecting circuit, a synchronization circuit and a data producing circuit. CONSTITUTION:A binary digital signal DRF in a data slice circuit 13 is supplied to an A-PLL circuit 21 and a B-PLL circuit 22. Bit synchronous clocks H and L.PLCK obtained in the A and B-PLL circuits 21, 22 are respectively supplied to frequency dividers 23, 24. Respective data signals A and B-Da are supplied to a synchronous signal detecting circuit 25 and a latch circuit 26. The synchro nous signal detecting circuit 25 detects that a reverse interval of the binary signal DRF is two times a bit synchronous clock A.PLCK and sets operating timing of the frequency divider 23. The latch circuit 26 latches the data signal B-Da outputted from the B-PLL circuit 22 in accordance with an output clock of the frequency divider 24.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is used in a digital reproduction device that reproduces a digital signal using a high-density recording modulation method, and in particular generates a channel bit synchronized clock from the digital signal using a phase-locked loop circuit. The present invention relates to a data strobe circuit that performs bit separation of data.

[Technical background of the invention and its problems] In recent years, there has been a tendency for digital control methods to be adopted in various devices, but in order to achieve high-density recording and playback, especially in information recording and playback systems, most of them use digital recording. It is becoming a reproduction method. In these various digital control systems, in order to make maximum use of their characteristics, digital information signals are modulated based on a high-density recording modulation method and then recorded or transmitted. A data strobe circuit is provided as a circuit for reproducing correct data from a signal. This data strobe circuit uses a channel bit clock (hereinafter referred to as PLCK) that is necessary to separate the data bits of the input modulation signal.
) and a data reading circuit that reads input data using PLCK.

For example, as shown in FIG. 8, a digital recording/reproducing system generally modulates a digital signal and records it on a recording medium 11, reads out the modulated signal RF from this recording medium using a pickup 12, etc. Then, the PLL circuit 14 extracts the data signal [)out from the binary position DRFbX and synchronizes it with the channel bit of the data signal [)Out, and generates the DTS PLCK.
By demodulating the data signal in the demodulation circuit 15 based on PLCK, correct digital data can be obtained. Here, in the modulated input signal DRF, when the inversion point means phase information of PLCK and the inversion interval means digitally encoded data information, generally the PLL circuit 14
generates PLCK using the rising and falling edges of the input signal [)RF.

Then, input data is read from this PLCK and bit separation is performed.

By the way, when a digital signal is recorded, the signal RF read out by a pickup or the like during playback becomes a signal that passes through a finite band, so the DC level fluctuates due to dropouts due to scratches or the like and low frequency components of the information signal itself. The PLL circuit 1 converts such a signal RF into a binary signal [)RF.
Although a data slicing circuit 13 is provided for sending the data to the data 4, its slice level detection is also not ideal, and the level is far from the optimum value. As a result, the input signal RF is sliced at a position deviated from the optimum value, and the level error is converted into a phase error and sent to the PLL circuit 14. FIG. 9 shows a binary signal A obtained when the slice level of the data slice circuit fluctuates as shown in a, b, and c.

The phase relationship between B and C is shown.

As is clear from FIG. 9, the binary signal [)RF generated by the data slice circuit 13 is sent to the PLL circuit 14 with its phase alternately leading and delaying due to fluctuations in the slice level. On the other hand, the PLL circuit 14 passes the phase error signal through a low-pass filter and outputs a voltage control excavator (VCO).
) is common, and if the frequency of the modulation signal RF is high enough, the lead/lag is canceled out and does not affect the PLCK, but since there is no phase detection margin, the frequency control region is In a PLL circuit using a phase comparator that does not have a phase comparator, a phase error exceeding ±π may occur, which disturbs PLCK control.

[Purpose of the Invention] This invention was made to improve the above-mentioned problem, and it is possible that phase errors caused by slice level fluctuations in binarization processing affect the bit synchronized clock generated by the PLL circuit. The purpose of the present invention is to provide a data strobe circuit that does not cause

[Summary of the Invention] That is, a data strobe circuit according to the present invention includes a data slicing circuit that converts a high frequency signal including a digital signal into a binary signal by level slicing it, and a binary signal output from the data slicing circuit. A first bit synchronization clock is generated from the binary signal by synchronizing the phase of a reference clock with one of the rising and falling edges of the binary signal, and the binary signal is synchronized with the bit synchronization clock. a first phase-locked loop circuit for outputting the binarized signal;
a second phase-locked loop circuit that generates a second bit-synchronized clock from the binary signal by phase-synchronizing a reference clock with the other edge not used in the other edge of the phase-locked loop circuit; first and second frequency dividers that respectively divide the first and second bit-synchronized clocks obtained by the second phase-locked loop circuit; A synchronization signal detection circuit detects that the bit synchronization clock is twice the bit synchronization clock of A synchronization means for synchronizing the frequency output, and a data generation circuit for reading the data of the digital signal from the binary signal obtained by the first phase-locked loop circuit based on the synchronization timing of the synchronization means. It is characterized by the fact that

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7. However, in FIG. 1, the same parts as in FIG. 8 are denoted by the same reference numerals, and only the different parts will be described here.

FIG. 1 shows its basic configuration, in which the digital signal [)RF binarized by the data slice circuit 13 is A-
The signal is supplied to the PLL circuit 21 and the B-PLL circuit 22.

Here, the A-PLL circuit 21 is the data slice circuit 1
By synchronizing the phase of the reference clock with the rising edge of the binary signal [)RF outputted from 3, the first bit synchronized clock H-PLCK is generated from the binary signal [)RF. [) RF is synchronized with the bit synchronization clock H-PLCK to extract the data signal A-Da. Further, the B-PLL circuit 22 generates a second bit synchronization clock L-PLCK from the binary signal [)RF by synchronizing the phase of the reference clock with the falling edge of the binary signal [)RF. , the binary signal [)RF is synchronized with the bit synchronization clock L-PLCK to extract the data signal B-Db.

The bit synchronized clocks H and L-PLCK obtained by the A and B-PLL circuits 21 and 22 are each passed through a frequency divider 23.
．． 24. In addition, each data signal A and B-D
a is supplied to a synchronizing signal detection circuit 25 and a latch circuit 26, respectively.

Here, the frequency dividers 23 and 24 respectively divide the input clock into M
It divides the frequency. Furthermore, the synchronization signal detection circuit 25
The operation timing of the frequency divider 23 is set by detecting that the inversion interval of the binary signal [)RF is twice the bit synchronization clock A-PLCK. The latch circuit 26 outputs B-PL according to the output clock of the frequency divider 24.
It latches the data signal B-Da output from the L circuit 22. The data latched in the latch circuit 26 controls the frequency division ratio of the frequency divider 23, and the timing control circuit 26 synchronizes with the output clock of the frequency divider 23.
7.

On the other hand, the data signal A- taken out by the A-PLL circuit 21
Da is supplied to the data generation circuit 28, and the bit synchronization clock H-PLCK is derived as a channel bit clock to the demodulation circuit, and the data generation circuit 2
8 clock input terminal.

The timing control circuit 27 generates an inverted control signal for the data generation circuit 28 based on the latch data from the latch circuit 26 and the clock from the frequency divider 23. In addition, the data generation circuit 28
takes in the data signal A-Da at the input timing of the H-PLCK clock, inverts it in response to an inversion control signal from the timing control circuit 27, and outputs it as the data signal [)OUTt.

That is, this data strobe circuit sends the data-sliced binary signal [)' RF to the PLL circuit 21 whose phase is synchronized at its rising edge, and the PLL circuit 22 whose phase is synchronized at its falling edge, and each PLL circuit 21 .2
By detecting the inverted phase distance of the bit synchronization clock obtained from 2, the rising edge phase synchronization and the falling edge phase synchronization are synchronized on the data, and data reading is generated from the timing of both. .

FIG. 2 shows a specific configuration of the above A-PLL circuit 21. This PLL circuit 21 has input signals [)RF and PLL.
It is composed of a phase comparator 211 that compares the phases of CK, a low-pass filter 212, and a VCO circuit 213.

The phase comparator 211 is a D-type flip-flop DFFI.
, DFF2 and AND gate G1, OR gate G2 and P channel MO8 (Pch), N channel MO
Consists of 8 (Nch> switch circuits, input signal [)
The phase error between the rising edge of RF and PLCK is determined by P channel MO8 (Pch) and N channel MO3 (Nc
h) is obtained by switching a switch circuit consisting of the above-mentioned gates Gl and G2 using the outputs P-a and P-b. A voltage signal p-c corresponding to the phase error obtained by this switching is supplied to a control input terminal of a CO circuit 213 via an 0-pass filter 212. This VCO circuit 213 receives the voltage signal P-c and changes the generation frequency (MXPLCK).

Incidentally, the above B-PLL circuit 22c is shown in FIG. 20(a) 1. :
The AND gate G1 and OR gate G2 shown in the same figure (b
), it may be replaced with the Noah gate G3 and the Nantes gate G4.

That is, the A-PLL circuit 21 (or B-PLL circuit 21)
In the circuit 22), the rising (falling) edge phase of the input signal [)RF and the output clock PL of the CO circuit 213
The phase error with CK is obtained by outputting the difference between both signals. In other words, in the modulation method for high-density recording, if one period of the PLCK clock is one clock, the inversion interval is, for example, 3T to 1
1T, and since the input phase cannot be predicted in phase synchronization, +(-)π is added to the input phase as a phase error (as a result, the error signal of ±π is 2
After a certain period of time has elapsed, a -(+) signal is output, and the phase error is determined to be correct. This relationship is shown in FIG.

Here, the data slice circuit 13
When the slice level changes as shown in FIG. 4 a, b, and c, the relationship between the input signal DRF of the PLL circuits 21 and 22 and the H and L-PLCK generated therein becomes as shown in the figure.

As is clear from Fig. 4bX, if the edge phase of only the same polarity is used for phase comparison, if the time constant of phase synchronization is shorter than the time constant of the fluctuation in the slice level, it will always accompany the slice level fluctuation. Since the phase of the VCo output also follows the phase change, 100% of the detected phase region can be utilized and performance can be improved. However, if this continues, the phase error of the opposite polarity will double, making it impossible to read data correctly. Therefore, in this data strobe circuit, a synchronization signal detection circuit 25 is provided to control the frequency division ratio of the frequency divider 23 when the phase comparison signal is doubled. The read timing is changed.

FIG. 5 shows a specific configuration of the data strobe circuit, in which the A-PLL circuit 21 includes D-type flip-flops D F, Fll, D F F12, AND gate Gl, OR gate G2, P, and N channel MOS. It is composed of a phase comparator 211 consisting of gates Pch and Nch, a low pass filter (LPF) 212, and a VCO circuit 213. Further, the B-PLL circuit 22 includes a D-type flip 70 tube DFF21. D F F22, Noah Gate G3, Nantes Gate G4, P, N Channel M
Phase comparator 221 consisting of OS gates Pch and Nch
, low-pass filter (L P F ) 222 and VC
It is composed of an o circuit 223.

The frequency divider 23 is a D-type flip 70 tube DFF.
31 to DFF33, gate circuits GC1 and GC2.

Consists of GC3. Further, the frequency divider 24 is a D-type flip 70 tube DFF41. Consists of DFF42. On the other hand, the synchronization signal detection circuit 25 uses the counter C
0NT, NOR gate G5, and AND gate G6. The latch circuit 26 is a D-type flip 70 tube D.
F F51. It is composed of DFF52. The timing control circuit 27 is a D-type flip-flop D.
Consists of FF61. Then, the data generation circuit 2
8 is a D-type flip-flop DFF71゜DFF7
2 and J- are composed of flip 70 tube FF73.

The operation of the above configuration will be described below with reference to the timing charts shown in FIGS. 6 and 7.

FIG. 6 shows the circuit operation timing when the binary signal output from the data slice circuit 13 is obtained at the slice level a shown in FIG. That is, the input signal [)RF is sent to the A-PLL circuit 21 and the B-PLL circuit 22, and the bit synchronized clocks H-PLCK and L-PLCK are synchronized with the rising and falling edge phases in each PLL circuit 21 and 22, respectively. is generated. Here, the Q output of flip-flop DFF11 and DFF1
The output of the NOR gate G5 obtained by taking the NOR of the Q output of 2 is supplied to the clear terminal 5-8L of the counter C0NT.
This clears the counter C0NT.

Here, the counter C0NT is for converting the distance of the phase comparison point, and the inversion interval of the input signal RF is at least 3
T, that is, the minimum output period of NOR gate G5 is 6T, then 5 outputs of counter C0NT and gate G
The output of AND gate G6 inputting 5 outputs becomes "1" when the one-item period of gate G5 is 6 pieces.

Now, the above A-PLL circuit 21 and B-PLL circuit 22
H-PLCK and H-PLCK generated by frequency divider 2
The frequency is divided into four by 3.24. Here, the 7 lip filters DFF41. Each Q output of the DFF42 is connected to the latch circuit 26 at its phase comparison timing.
7 lips 70 tubes D F FS2. D F F51
is latched to. At this time, when the gate G6 output of the synchronous signal detection circuit 25 becomes "1", the D F of the frequency divider 23
F31. D F F32 is the same as the above D F F52.
The contents of DFF51 will now be preset.

In other words, when the output of gate G6 is "1", A-PLL
The phase comparison of the circuit 21 is at a position of 6T counted from the previous operation. Therefore, the data latched in the latch circuit 26 needs to be processed as 3T even if the timing from the phase comparison timing of the B-PLL circuit 22 to the output generation of the gate G6 is actually 2, 3, or 4T. There is.

Therefore, D F of the frequency divider 23 is determined by the output of the gate G6.
F31. DFF F1a is DFF of latch circuit 26
If the timing of presetting the latch data of the 52° DFF 51 is delayed by 1T, the result will be a delay of 4 kings from the phase comparison point (falling edge) of the B-PLL circuit 22 in terms of processing. Furthermore, DFF31. DF
F33. DFF52. Since the data set in the DFF 51 are each generated by frequency division by 4, the phase error detection operations at both edges are synchronized. This synchronization causes D F F31. D F F32 and D F F52. The timing difference between the DFF 51 and the actual operation corresponds to the phase difference due to the slice level fluctuation of the data slice circuit 13.

Then, the H-PLCK side directly takes out the data using that clock, and the L-PLCK side latches the data taken out using that clock. When the outputs of DFF31° and DFF33 become as shown in the following table, Data generation circuit 28
By outputting data (Q output of the FF 23) from the FF 23, the phase error described above can be corrected. However, L-PL
On the CK side, phase lead/lag occurs due to slice level fluctuations, so it is necessary to delay its output by a predetermined time. Therefore, in the data strobe circuit described above, by delaying the input by 3T and outputting it, the L-PLC
Even if there is a fluctuation of about ±2T on the K side, it can be solved by processing -1 to -5 teeth.

FIG. 7 shows the operation timing when the phase comparison on the L-PLCK side is delayed by 1/25th.

Note that in Figures 6 and 7, there is an error in the initial output, but this shows the result when synchronization is not performed. You can correct and output the data until it becomes incorrect.

Therefore, the data strobe circuit configured as described above can exhibit sufficient performance because slice level fluctuations do not affect the phase comparison range of the PLL circuit. Furthermore, it is possible to correct phase errors due to slice level fluctuations, resulting in extremely high performance. In other words, there is no need to increase the slice level setting ability of the data slicing circuit, it becomes possible to change vertical level fluctuations to the time axis and digitally process them, and furthermore, it is possible to reduce the number of external parts when converting to an IC. There are advantages.

[Effects of the Invention] As described in detail above, according to the present invention, the phase error caused by slice level fluctuations in binarization processing, etc.
It is possible to provide a data strobe circuit that does not affect the bit synchronization clock generated by the L circuit.

[Brief explanation of drawings]

1 to 7 show an embodiment of a data strobe circuit according to the present invention, FIG. 1 is a block circuit diagram showing its basic configuration, and FIG. 2 is a block circuit diagram used in the embodiment. '
A block circuit diagram showing a specific configuration of the P L 1 circuit,
FIG. 3 is an explanatory diagram of the operation of the above PLL circuit, FIG. 4 is a timing chart for explaining the relationship between slice level fluctuations with respect to input signals and bit synchronization clocks, and FIG. 5 is a concrete configuration of the above data strobe circuit. 6 and 7 are timing charts for explaining the operation of the data strobe circuit shown in FIG. 5, and FIG. 8 is a configuration of a digital recording and reproducing system to which the present invention is applied. FIG. 9 is a timing chart for explaining the phase error that occurs when the slice level changes with respect to the input signal. 13... Data slice circuit, 15... Demodulation circuit,
21... Rising edge detection PLL circuit, 22...
Falling edge detection PLL circuit, 23.24... Frequency divider, 25... Synchronous signal detection circuit, 21... Timing control circuit, 28... Data generation circuit, [)
RF...Binarized digital signal, PLCK...Bit synchronized clock, □out...Data signal. Applicant's representative Patent attorney Takehiko Suzue No. 85! ! F Figure 9 Procedural Amendment, 8ゎ6Q, 5. 48

Claims (1)

[Claims] a data slicing circuit that converts a high frequency signal including a digital signal into a binary signal by level slicing it;
By synchronizing the phase of the reference clock with either the rising or falling edge of the binary signal output from this data slice circuit, the first
a first phase-locked loop circuit that generates a bit-synchronized clock and outputs the binary signal in synchronization with the bit-synchronized clock; a second phase-locked loop circuit that generates a second bit-synchronized clock from the binary signal by phase-synchronizing a reference clock with the other edge that is not used; and the first and second phase-locked loop circuits. first and second frequency dividers that respectively divide first and second bit synchronous clocks obtained by the above, and an inversion interval of the binarized signal is twice that of the first or second bit synchronous clock. a synchronous signal detection circuit that detects that
a synchronization means for synchronizing the divided outputs of the first and second frequency dividers by controlling the division ratios of the first and second frequency dividers in the detection state of the synchronization signal detection circuit; and a data generation circuit that reads data of the digital signal from the binary signal obtained by the first phase-locked loop circuit based on the data.