JPS63164448A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63164448A JPS63164448A JP61315252A JP31525286A JPS63164448A JP S63164448 A JPS63164448 A JP S63164448A JP 61315252 A JP61315252 A JP 61315252A JP 31525286 A JP31525286 A JP 31525286A JP S63164448 A JPS63164448 A JP S63164448A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- film
- pattern
- forming material
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 150000002739 metals Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置を外部接続するための手法９例
えばインナーリードボンディング法・フリップチップボ
ンディング法に必要な半導体装置のパッド上に形成する
バンプの製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to bumps formed on pads of semiconductor devices necessary for methods 9 for externally connecting semiconductor devices, such as inner lead bonding and flip chip bonding. Relating to a manufacturing method.
この発明は、半導体装置上にバンプを形成するためのパ
ターンを形成するパターン形成材料膜の厚みを４μｍ以
上とすることにより不要となったパターン形成材料を剥
離した際にバンプ底部と半導体基板上６面の接触外周部
に、残存することを防止するようにしたものである。In this invention, the thickness of the pattern-forming material film used to form a pattern for forming bumps on a semiconductor device is set to 4 μm or more, so that when the unnecessary pattern-forming material is peeled off, the bottom of the bump and the top of the semiconductor substrate are removed. This prevents it from remaining on the contact outer periphery of the surface.
従来、第２図（ａ）に示すように、半導体基板６上に絶
縁Ｉ閑層５が形成され絶縁膜上に導電性膜の蒸着等によ
り、パ・ノド４を形成する。さらに。Conventionally, as shown in FIG. 2(a), an insulating I blank layer 5 is formed on a semiconductor substrate 6, and a conductive layer 4 is formed on the insulating film by vapor deposition or the like. moreover.
絶縁保護膜２を形成後、パッド４上の所要部分に形成さ
れるバンプ３を形成するために、絶縁保護膜２に孔７を
開ける。絶縁保護膜２の孔７を含む絶縁保護膜２全面に
、パッド金属およびバンプ金属との密着性の良好な導電
体１５！８を蒸着等で形成する。この後、パターン形成
材料膜ｌでバンプ形成パターンを形成する。このパター
ン形成材料■の厚みが、４μｍより薄い状態でバンプを
形成することが、一般的である。After forming the insulating protective film 2, holes 7 are made in the insulating protective film 2 in order to form bumps 3 at required portions on the pads 4. A conductor 15!8 having good adhesion to pad metals and bump metals is formed on the entire surface of the insulating protective film 2 including the holes 7 of the insulating protective film 2 by vapor deposition or the like. Thereafter, a bump forming pattern is formed using a pattern forming material film 1. It is common to form bumps in a state where the thickness of this pattern forming material (1) is less than 4 μm.
しかし、従来の４μｍより薄いパターン形成材料厚みで
バンプを形成した場合、第２図（ｂ）に示すようにバン
プ形成後にパターン形成材料を剥離する際９例えば剥離
溶液または例えば酸素プラズマが、パターン形成材料厚
みよりバンプが高く形成された場合、バンプ下部に拡散
しすらいためパターン形成材料が残存し、半導体装置の
電気的信頼性を低下させるという欠点があった。However, when a bump is formed with a thickness of pattern forming material thinner than the conventional 4 μm, as shown in FIG. If the bump is formed higher than the thickness of the material, the pattern forming material tends to diffuse to the lower part of the bump, resulting in a residual pattern forming material, which has the disadvantage of reducing the electrical reliability of the semiconductor device.
そこで、この発明は、従来のこのような欠点を解決する
ため、バンプ下部のパターン形成材料が残存しないよう
な製造方法を提供することを目的としている。SUMMARY OF THE INVENTION In order to solve these conventional drawbacks, it is an object of the present invention to provide a manufacturing method in which no pattern-forming material remains under the bumps.
上記問題点を解決するために、この発明は、バンプ形成
パターンを形成するパターン形成材料を４μｍ以上とし
た構造とし、バンプ下部のパターン形成材料の残存を防
止するようにした。In order to solve the above problems, the present invention has a structure in which the pattern forming material forming the bump forming pattern has a thickness of 4 μm or more to prevent the pattern forming material from remaining under the bumps.
上記のような構造でバンプを形成後、パターン形成物質
を剥離すると、バンプ下部のすきまが４μｍ以上となっ
ているため２例えば剥離溶液または例えば酸素プラズマ
の拡散が容易となるため。After forming bumps with the above structure, when the pattern forming material is peeled off, the gap below the bumps is 4 μm or more, which facilitates the diffusion of, for example, a stripping solution or oxygen plasma.
バンプ下部のパターン形成物質が完全に除去できるので
ある。The pattern forming material under the bump can be completely removed.
以下に、この発明の実施例を１図面にもとづいて説明す
る。第１図（ａ）において、半導体基板６上に絶縁膜層
５が形成され絶縁膜上導電性膜の蒸着等により、パッド
４を形成する。さらに、絶縁保護膜２を形成後、パッド
４上の所要部分に形成されるバンプ３を形成するために
、絶縁保護膜２に孔７を開ける。絶縁保護膜２の孔７を
含む絶縁保護膜２全面に、パッド金属およびバンプ金属
との密着性の良好な導電体膜８を蒸着等で形成する。こ
の後、パターン形成材料膜ｌを４μｍ以上の厚みで膜付
けし、バンプ形成パターンを形成する。この後、バンプ
をメッキ法にて形成する。第１図（ｂ）は、上記方法に
よりバンプ形成後、パターン形成材料膜１を剥離した後
の例を示すものである。Embodiments of the present invention will be described below based on one drawing. In FIG. 1(a), an insulating film layer 5 is formed on a semiconductor substrate 6, and a pad 4 is formed by depositing a conductive film on the insulating film. Furthermore, after forming the insulating protective film 2, holes 7 are made in the insulating protective film 2 in order to form bumps 3 at required portions on the pads 4. A conductive film 8 having good adhesion to pad metals and bump metals is formed on the entire surface of the insulating protective film 2 including the holes 7 in the insulating protective film 2 by vapor deposition or the like. Thereafter, a pattern forming material film 1 is deposited to a thickness of 4 μm or more to form a bump forming pattern. After this, bumps are formed by plating. FIG. 1(b) shows an example after the pattern forming material film 1 is peeled off after bumps are formed by the above method.
この発明は９以上説明したように、バンプを形成するパ
ターン形成材料膜の厚みを４μｍ以上とする簡単な構造
で、バンプ下部のパターン形成材料の残存を防止し、半
導体装置の電気的信頼性の低下を防止する効果がある。As explained in Section 9 above, this invention has a simple structure in which the thickness of the pattern forming material film forming the bump is 4 μm or more, which prevents the pattern forming material from remaining under the bump and improves the electrical reliability of the semiconductor device. It has the effect of preventing deterioration.
第１図（ａ）及び（ｂ）は、この発明の製造方法の工程
順断面図、第２図（ａ）及び（ｂ）は。
従来の製造方法の工程順断面図である。
１・・・パターン形成材料膜
８・・・導電性膜
４・・・パッド
ロ・・・半導体基板
３・・・バンプ金属
以上
出願人 セイコー電子工業株式会社
゛＼、１１FIGS. 1(a) and (b) are cross-sectional views of the manufacturing method of the present invention in the order of steps, and FIGS. 2(a) and (b) are sectional views. FIG. 3 is a step-by-step sectional view of a conventional manufacturing method. 1... Pattern forming material film 8... Conductive film 4... Padro... Semiconductor substrate 3... Bump metal and more Applicant: Seiko Electronics Co., Ltd., 11
Claims (1)
ンプを形成する際、バンプを形成するためのパターンを
形成するパターン形成材料膜の厚みを４μｍ以上とする
ことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, characterized in that when bumps made of any metal are formed on a semiconductor substrate by a plating method, the thickness of a pattern-forming material film that forms a pattern for forming the bumps is 4 μm or more. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61315252A JPS63164448A (en) | 1986-12-26 | 1986-12-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61315252A JPS63164448A (en) | 1986-12-26 | 1986-12-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63164448A true JPS63164448A (en) | 1988-07-07 |
Family
ID=18063196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61315252A Pending JPS63164448A (en) | 1986-12-26 | 1986-12-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63164448A (en) |
-
1986
- 1986-12-26 JP JP61315252A patent/JPS63164448A/en active Pending
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