JPS63308352A - Manufacture of semiconductor - Google Patents
Manufacture of semiconductorInfo
- Publication number
- JPS63308352A JPS63308352A JP62145629A JP14562987A JPS63308352A JP S63308352 A JPS63308352 A JP S63308352A JP 62145629 A JP62145629 A JP 62145629A JP 14562987 A JP14562987 A JP 14562987A JP S63308352 A JPS63308352 A JP S63308352A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- bump
- interlayer insulating
- opening
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010410 layer Substances 0.000 claims abstract description 41
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000007747 plating Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 230000006866 deterioration Effects 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract 4
- 238000006731 degradation reaction Methods 0.000 abstract 4
- 150000002739 metals Chemical class 0.000 abstract 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910052697 platinum Inorganic materials 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000009719 polyimide resin Substances 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に金属バンプ
を有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having metal bumps.
金属バンプを有する半導体装置はワイヤレスボンディン
グによシチヅプの実装が小容積にできるという特徴を有
するが、バンプの材質によっては酸化のための特性劣化
の問題点を有している。Semiconductor devices having metal bumps have the feature that the chip can be mounted in a small volume by wireless bonding, but depending on the material of the bumps, there is a problem of deterioration of characteristics due to oxidation.
第２図（ａｌ〜（Ｃ）は従来の半導体装置の製造方法の
−例を説明するための工程順に示した半導体チップの断
面図である。FIGS. 2A to 2C are cross-sectional views of a semiconductor chip shown in order of steps for explaining an example of a conventional method for manufacturing a semiconductor device.
第２図（ａ）に示すように、半導体基板１の表面に設け
られた絶縁膜２の上にアルミニクム等の金属層を堆積し
、選択的にエツチングしてバッド３を設け、バッド３を
含む表面に層間絶縁膜４ｆｔ形成し、選択的にエツチン
グしてパッド３の上に第１の開口部を設ける。次に、す
７トオフ法によシ前記第１の開口部のパッド３０表面お
よび前記第１の開口部周縁の層間絶縁膜４の上に延在す
るチタン層６および白金層７の積層を選択的に設ける。As shown in FIG. 2(a), a metal layer such as aluminum is deposited on the insulating film 2 provided on the surface of the semiconductor substrate 1, and selectively etched to form a pad 3. A 4ft interlayer insulating film is formed on the surface and selectively etched to form a first opening above the pad 3. Next, a stack of a titanium layer 6 and a platinum layer 7 extending over the surface of the pad 30 of the first opening and the interlayer insulating film 4 around the periphery of the first opening is selected by the 7-off method. to be established.
次に、第２図（ｂ）に示すように、前記白金層７を含む
表面にホトレジスト膜９を形成し、選択的に露光・現像
して前記第１の開口部を含み且つ前記第１の開口部よシ
僅か大きい第２の開口部を設ける。次に、前記第２の開
口部の白金層７の上に電気めっき法によフ銅めっき層を
堆積してバンプ１１を形成する。次に、バンプ１１の表
面に電気めっき法によシニッケル層１２および金層１３
を順次形成する。Next, as shown in FIG. 2(b), a photoresist film 9 is formed on the surface including the platinum layer 7, and is selectively exposed and developed to cover the first opening and the first opening. A second opening is provided which is slightly larger than the opening. Next, a bump 11 is formed by depositing a copper plating layer on the platinum layer 7 in the second opening by electroplating. Next, a nickel layer 12 and a gold layer 13 are deposited on the surface of the bump 11 by electroplating.
are formed sequentially.
次に、第２図（Ｃ）に示すように、ホトレジスト膜９を
除去する。Next, as shown in FIG. 2(C), the photoresist film 9 is removed.
上述した従来の半導体装置の製造方法は、ニッケル、金
層がめっきされているバンプの上表面以外はバッグの材
質そのものが露出しており、バンプ材として、例えばＣ
ｕまたははんだを使用した場合、露出部分が酸化されや
すく、酸化による表面の変質が電気的特性の劣化および
バンプ強度の劣化、または耐湿性低下等の信頼性の低下
を招くという問題点があった。In the conventional semiconductor device manufacturing method described above, the material of the bag itself is exposed except for the upper surface of the bumps, which are plated with nickel and gold layers.
When u or solder is used, the exposed parts are easily oxidized, and there is a problem in that the deterioration of the surface due to oxidation leads to deterioration of electrical characteristics, deterioration of bump strength, and deterioration of reliability such as deterioration of moisture resistance. .
本発明の目的は、バンプの全表面を酸化されに半導体装
置の製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device in which the entire surface of the bump is oxidized.
半導体基板表面に設けた絶縁膜の上に第１の金属層を堆
積し選択的にエツチングしてバッドを設ける工程と、該
パッドを含む表面に第１の層間絶縁膜を堆積し選択的に
エツチングして前記パッドの上に第１の開口部を設ける
工程と、前記第１の開口部のパッド表面および前記第１
の開口部周縁の前記第１の層間絶縁膜上に延在する第２
の金属層を設け該第２の金属層を含む表面に第２の層間
絶縁膜を設ける工程と、該第２の層間絶縁膜の上にホト
レジスト膜を形成し選択的ｔ／Ｃｇ光・現像して前記第
１の開口部を含み且つ前記第１の開口部よシ僅かに大き
い第２の開口部を設ける工程と、前記ホトレジスト膜を
マスクとして前記第２の層間絶縁膜をエツチングし前記
第２の金属層表面を露出させ且つ前記ホトレジスト膜の
下側にアンダーカット部を形成する工程と、熱処理で前
記ｔｆ、ｙ！トレジスト膜を軟化させて前記アンダーカ
ット部を塞ぐ工程と、前記第２の開口部の前記第２の金
Ｘ屑表面に金属をめっきしてバンプを形成し前記ホトレ
ジスト膜を除去する工程と、前記バンプに金属層をめっ
きし前記第２の層間絶縁膜を除去する工程とを含んで構
成される。A step of depositing a first metal layer on an insulating film provided on the surface of a semiconductor substrate and selectively etching it to provide a pad, and depositing a first interlayer insulating film on the surface including the pad and selectively etching it. forming a first opening on the pad;
a second interlayer insulating film extending on the first interlayer insulating film around the opening of the second interlayer insulating film;
a step of providing a second interlayer insulating film on the surface including the second metal layer, and forming a photoresist film on the second interlayer insulating film and selectively developing with t/Cg light. forming a second opening that includes the first opening and is slightly larger than the first opening; etching the second interlayer insulating film using the photoresist film as a mask; tf, y! by exposing the surface of the metal layer and forming an undercut portion under the photoresist film, and heat treatment. a step of softening the photoresist film to close the undercut portion; a step of plating a metal on the surface of the second gold X scrap in the second opening to form a bump and removing the photoresist film; The method includes the steps of plating a metal layer on the bump and removing the second interlayer insulating film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｇ）は本発明の一実施例を説明するた
めの工程ｊ１ハに示した半導体チップの断面図である。FIGS. 1(a) to 1(g) are cross-sectional views of a semiconductor chip shown in step j1c for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、半導体基板１０表面
に設けられたＭＡ緑模膜２上に蒸着法またはスパッタリ
ング法によシ膜厚１μｍのアルミエクム層を堆積し、反
応性イオンエツチングによ勺選択的に除去しバッド３を
形成する。First, as shown in FIG. 1(a), an aluminum Ecum layer with a thickness of 1 μm is deposited on the MA green film 2 provided on the surface of the semiconductor substrate 10 by vapor deposition or sputtering, and then reactive ion etching is performed. A pad 3 is formed by selectively removing the wafer.
次に、バッド３を含む表面にＣＶＤ法によシリコン窒化
物またはシリコン窒化物からなる層間絶縁膜４を堆積し
、選択的にエツチングしてバッド３の上に第１の開口部
５を形成する。Next, silicon nitride or an interlayer insulating film 4 made of silicon nitride is deposited on the surface including the pad 3 by the CVD method and selectively etched to form a first opening 5 on the pad 3. .
次に、第１図（ｂ）に示すように、リフトオフ法により
開口部５のパッド３０表面および開口部５０周縁の層間
絶縁膜４の上に延在する膜厚０．１μｍのチタン層６お
よび膜厚０．１μｍの白金層７を順次堆積させた積層を
選択的に設ける。次に、前記積層を含む表面にポリイミ
ド系樹脂膜８を２〜３μｍの厚さに形成し、１００〜１
５０℃で１５分間のベーキングを行う。Next, as shown in FIG. 1(b), a titanium layer 6 with a thickness of 0.1 μm and a titanium layer 6 extending on the surface of the pad 30 of the opening 5 and the interlayer insulating film 4 around the periphery of the opening 50 are then formed using a lift-off method. A laminated layer of platinum layers 7 having a thickness of 0.1 μm is selectively deposited in sequence. Next, a polyimide resin film 8 with a thickness of 2 to 3 μm is formed on the surface including the laminated layer, and
Bake for 15 minutes at 50°C.
次に、第１図（Ｃ）に示すように、ポリイミド系樹脂膜
８の上に厚さ約２０μｍのホトレジスト膜９を形成し、
選択的に露光・現像して開口部５を含み且つ開口部５よ
り僅か大きい開口部１０を設け、１５０℃で３０〜４５
分間のベーキングを行う０次に、ヒドラジンを含む溶液
によ）ポリイミド系樹脂膜８の側面ｔ−２〜５μｍエツ
チングしてホトレジスト族９の下側にアンダーカット部
１１を形成する。Next, as shown in FIG. 1(C), a photoresist film 9 with a thickness of about 20 μm is formed on the polyimide resin film 8.
Selectively exposed and developed to provide an opening 10 that includes the opening 5 and is slightly larger than the opening 5, and
Next, the side surface of the polyimide resin film 8 is etched by t-2 to 5 μm (using a solution containing hydrazine) to form an undercut portion 11 under the photoresist group 9.
次に、第１図（ｄ）に示すように、１８０℃程度のベー
キングを行ないホトレジスト膜９を軟化させてアンダー
カット部１１を塞ぐ。このとき、ポリイミド系樹脂膜８
の側面に空洞を生ずる可能性があるが、支障はない。Next, as shown in FIG. 1(d), baking is performed at about 180° C. to soften the photoresist film 9 and close the undercut portion 11. At this time, the polyimide resin film 8
Although there is a possibility that a cavity may be formed on the side surface, this is not a problem.
次に、第１図（ｅ）に示すように、白金層７の上に１８
〜２０μｍの厚さの銅めっき層を堆積してバンプ１２を
形成する。Next, as shown in FIG. 1(e), 18
Bumps 12 are formed by depositing a copper plating layer with a thickness of ~20 μm.
次に、第１図（ｆｌに示すように、ホトレジスト膜９を
除去し、ポリイミド系樹脂膜８をマスクとしてバンプ１
２の表面にニッケル層１３および金層１４をそれぞれ１
〜ｆ２μｍの厚さに順次めっきで堆積する。Next, as shown in FIG.
1 nickel layer 13 and gold layer 14 on the surface of 2
It is deposited by plating sequentially to a thickness of ~f2 μm.
次に、第１図（ｇ）に示すように、ポリイミド系樹脂膜
８を除去する。Next, as shown in FIG. 1(g), the polyimide resin film 8 is removed.
ここで、チタン層６の代シにクロム層を、白金層７の代
シに銅層を用いても艮い。Here, a chromium layer may be used instead of the titanium layer 6, and a copper layer may be used instead of the platinum layer 7.
以上説明したように本発明は、ホトレジスト膜をマスク
として金属をめっきしてバンプを形成し、第２の層間絶
縁膜をマスクとしてバンプの全表面を難酸化性金属のめ
っき層で被覆することにより、酸化、その他によるバン
プ表面の変′Ｒを防ぎ、電気的特性の劣化およびバンプ
強度の劣化を抑制して、半導体装置の信頼性の向上を実
現することができるという効果を有する。As explained above, the present invention forms bumps by plating metal using a photoresist film as a mask, and coats the entire surface of the bump with a plating layer of an oxidation-resistant metal using a second interlayer insulating film as a mask. This has the effect of preventing deformation of the bump surface due to oxidation, oxidation, etc., suppressing deterioration of electrical characteristics and deterioration of bump strength, and improving the reliability of the semiconductor device.
第１図（ａｌ〜（ωは本発明の一実施例を説明するため
の工程順に示した半導体チップの断面図、第２図（ａ）
〜（Ｃ）は従来の半導体装置の製造方法の一例を説明す
るための工程順に示した半導体チップの断面図である。
ｌ・・・・・・半導体基板、２・・・・・・絶縁膜、３
・・・・・・パッド、４・・・・・・層間絶縁膜、５・
・・・・・開口部、６・・・・・・チタン層、７・・・
・・・白金層、８・・・・・・ポリイミド系樹脂膜、９
・・・・・・ホトレジスト膜、１０・・・・・・開口部
、１１・・・・・・アンダーカット部、１２・・・・・
・バンプ、１３・・・・・・ニッケル層、１４・・・・
・・金層。
−轡ｒ＼
代理人 弁理士 内 原 晋・ 、？７）」 ｌ
図Figure 1 (al~(ω) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, Figure 2 (a)
-(C) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an example of a conventional method for manufacturing a semiconductor device. l... Semiconductor substrate, 2... Insulating film, 3
...Pad, 4...Interlayer insulating film, 5.
...Opening, 6...Titanium layer, 7...
...Platinum layer, 8...Polyimide resin film, 9
... Photoresist film, 10 ... Opening, 11 ... Undercut portion, 12 ...
・Bump, 13...Nickel layer, 14...
...Gold layer. −轡r＼ Agent: Susumu Uchihara, patent attorney? 7)"l
figure
Claims (1)
積し選択的にエッチングしてパッドを設ける工程と、該
パッドを含む表面に第１の層間絶縁膜を堆積し選択的に
エッチングして前記パッドの上に第１の開口部を設ける
工程と、前記第１の開口部のパッド表面および前記第１
の開口部周縁の前記第１の層間絶縁膜上に延在する第２
の金属層を設け該第２の金属層を含む表面に第２の層間
絶縁膜を設ける工程と、該第２の層間絶縁膜の上にホト
レジスト膜を形成し選択的に露光・現像して前記第１の
開口部を含み且つ前記第１の開口部より僅かに大きい第
２の開口部を設ける工程と、前記ホトレジスト膜をマス
クとして前記第２の層間絶縁膜をエッチングし前記第２
の金属層表面を露出させ且つ前記ホトレジスト膜の下側
にアンダーカット部を形成する工程と、熱処理で前記ホ
トレジスト膜を軟化させて前記アンダーカット部を塞ぐ
工程と、前記第２の開口部の前記第２の金属層表面に金
属をめっきしてバンプを形成し前記ホトレジスト膜を除
去する工程と、前記バンプに金属層をめっきし前記第２
の層間絶縁膜を除去する工程とを含むことを特徴とする
半導体装置の製造方法。A step of depositing a first metal layer on an insulating film provided on the surface of a semiconductor substrate and selectively etching it to provide a pad, and depositing a first interlayer insulating film on the surface including the pad and selectively etching it. forming a first opening on the pad;
a second interlayer insulating film extending on the first interlayer insulating film around the opening of the second interlayer insulating film;
forming a photoresist film on the second interlayer insulating film and selectively exposing and developing it to form the second interlayer insulating film on the surface including the second metal layer; a step of providing a second opening that includes the first opening and is slightly larger than the first opening; etching the second interlayer insulating film using the photoresist film as a mask;
a step of exposing the surface of the metal layer and forming an undercut portion under the photoresist film; a step of softening the photoresist film by heat treatment to close the undercut portion; plating a metal layer on the surface of the second metal layer to form bumps and removing the photoresist film; plating a metal layer on the bumps and forming bumps on the second metal layer;
A method for manufacturing a semiconductor device, comprising the step of removing an interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145629A JPS63308352A (en) | 1987-06-10 | 1987-06-10 | Manufacture of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145629A JPS63308352A (en) | 1987-06-10 | 1987-06-10 | Manufacture of semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63308352A true JPS63308352A (en) | 1988-12-15 |
Family
ID=15389423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62145629A Pending JPS63308352A (en) | 1987-06-10 | 1987-06-10 | Manufacture of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63308352A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5244833A (en) * | 1989-07-26 | 1993-09-14 | International Business Machines Corporation | Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer |
-
1987
- 1987-06-10 JP JP62145629A patent/JPS63308352A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5244833A (en) * | 1989-07-26 | 1993-09-14 | International Business Machines Corporation | Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer |
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