JPS63163641A - Test system for data processor - Google Patents

Abstract

PURPOSE:To shorten a time for manual investigation, by taking out and accumulating instructions one by one from a test instruction string and a test data, executing the instruction string accumulated until then by both a test object data processor and a simulation processing part, and comparing executed results. CONSTITUTION:The instructions are taken out and accumulated one by one from the test instruction string, and each time, the instruction strings accumulated until then are executed by both the test object data processor 12 and the simulation processing part 8, and the executed results are compared. And when abnormality is detected in the executed results of the test instruction string accumulated until a certain time is generated, no abnormality exists in the result of the instruction string accumulated and executed until just before, and the abnormality is detected by the accumulation of the said instruction in the instruction string. In such a way, it is possible to analyze the content of the abnormality by limiting the generation of an abnormal state on the said instruction.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device, and in particular, to localizing an instruction that causes an error in a test using a test instruction sequence of a large-scale data processing device having an acceleration logic. Accordingly, the present invention relates to a data processing device testing method suitable for reducing analysis time.

[Conventional technology]

In a test system that confirms the normality of functions in a data processing device, one expected value is prepared for one set of test data, the test data is executed on the device under test, and the processing results are compared with the expected value. was common.

However, as data processing devices have become larger in scale, methods have been adopted in which test data is composed of a sequence of test instructions, which is a set of ordered instructions, and an expected value for the sequence of instructions. . In this case, the conventional test method was as follows. Each test instruction sequence is executed on the device under test to confirm the normality of the device. The processing result of each test instruction string execution is compared with its expected value, and if they do not match, it means that an error has occurred in the test instruction in that test instruction string. If an abnormality is detected in the execution result of a certain test instruction string, it is manually investigated which test instruction in the test instruction string caused the error.

This testing method has problems in that it takes a lot of time to conduct the survey manually, and that the survey results also depend on the abilities of the researcher. In addition, to determine the test instruction that resulted in an error, refer to the assemble list, execute the test instruction sequence that resulted in the abnormal result multiple times, or
It also required patches to change instructions and data.

As a test method to solve the above problem, a software simulator of the device under test is installed in the test system, and first a sequence of test instructions is executed on the device under test according to the test data, and if it does not finish normally, then an error analysis is performed. In processing, there is a method in which each instruction is extracted from a test instruction string and executed on both the software simulator and the device under test, and the results are compared. FIG. 4 shows an example of the processing flow of this method. According to this, it is possible to easily recognize which test instruction in the test instruction sequence was not processed normally. This test method is described in detail in, for example, Japanese Unexamined Patent Publication No. 61-43351.

[Problem that the invention seeks to solve]

Generally, in large-scale data processing devices, acceleration logic, typified by advance control logic and pipeline control, is used to achieve faster processing.

In this type of data processing device, an ordered instruction sequence is not executed serially, but at a certain time axis, such as starting execution of a subsequent instruction in the middle of execution of a preceding instruction. Multiple instructions are executed in parallel.

When trying to apply the above test method to testing a data processing device having such acceleration logic, the following problems arise. During a test, a test instruction sequence is executed on the device under test. The instructions that make up the test instruction sequence are organically combined with each other and executed in parallel. However, in error analysis processing, the test instruction sequence is Since each instruction is extracted and executed one by one, the execution environment of the test instruction sequence changes. For example, in a test instruction sequence, the execution result of the preceding instruction is continuously executed, such as rewriting the instruction to be executed subsequently by the preceding instruction, or using the execution result of the preceding instruction in the subsequently executed instruction. Even if an error is detected in the execution of an organically combined instruction sequence that affects the execution of instructions (conflict condition), the error analysis process will detect the organic combination of each instruction that makes up this test instruction sequence. This means that the commands are ignored and executed one by one.

For this reason, the same result as when the instructions constituting the test instruction are executed individually and sequentially is obtained, resulting in a problem that errors cannot be accurately pointed out.

An object of the present invention is to solve the above-mentioned problems, and even in a data processing device having an acceleration logic, when an abnormality is detected in the execution of a test instruction sequence due to processing specific to the acceleration logic, the test instruction that has caused an error can be detected. An object of the present invention is to provide a test method for a data processing device that enables direct judgment of the data processing apparatus and reduces the time required for one-man investigation.

[Means for solving problems]

The present invention extracts and stores test command sequences and test data one instruction at a time, and in the process of storage, sequentially stores the stored command sequences in both the test target data processing device and the simulation processing unit. The feature is that the execution results are compared.

[For production]

Extract and accumulate instructions one by one from the test instruction string,
Each time, the accumulated instruction sequences up to that point are executed by both the test target device and the simulation processing unit, and the execution results are compared to detect abnormalities in the execution results of the test instruction sequences accumulated up to a certain point. In this case, there is no abnormality in the result of the instruction sequence that was accumulated and executed just before, and the abnormality is detected by accumulating the instruction in the instruction sequence, so the occurrence of the abnormal condition is limited to the instruction in question and the error is detected. It becomes possible to analyze the contents.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of a test system according to the present invention. In FIG. 1, a test system 1 is composed of a test data storage section 5 and a control section 11. The test data storage unit 5 stores a random value 2° test command sequence, test data 3, expected value data 4, and the like. The control unit 11 generates a test instruction sequence and test data and controls test execution, and the test data generation unit 6. It has a test data setting section 7, a simulation processing section 8, a test result determination section 9, and an error output section 10.

The test data generation section 6 generates a test instruction sequence 3a and test data 3b based on the random number value 2. The test data setting section 7 includes a test instruction sequence 3a and test data 3b.
is supplied to the simulation processing section 8 and the test electrical device 1 12. The test commands and test data on the device under test 12 are the test command sequence 3a and the test data 3.
It is set while accumulating one instruction at a time from b. The simulation processing section 8 executes the functions of the device under test 12 in a pseudo manner based on the test command sequence and test data received from the test data setting section 7, and creates the execution results as expected value data 4. The test result determination unit 9 compares the expected value created by the simulation processing unit 7 as an execution result of the test instruction sequence with the execution result of the test instruction sequence executed by the device under test 12, and when a discrepancy occurs. It detects abnormalities. The error output unit 10 separates the test command sequence and test data into an expected value and an execution result in the device under test 12 and outputs them as an error message when an abnormality is detected by the test result determination unit 9.

The data processing device 12, which is the device to be tested, is a general data processing device, and has a test data memory area 13 that stores the test command sequence 13a and test data 13b passed from the test system 1, and a test data memory area 13 that stores the test command sequence 13a. It includes a test execution unit 14 that executes according to test data 13b. Generally, the test data memory area 13 is located on the main memory, and the test execution unit 14 is the central processing unit itself.

First, FIG. 2 shows the processing flow of this embodiment.

Prior to the start of the test, a test instruction sequence 3a and test data 3b are generated in process 201, and the test instruction sequence 3a and test data 3b are generated by the test data generation section 5 based on the random number value 2.

In process 202 , the test data setting unit 6 extracts one instruction from the test command sequence and the test data 3 and sets them in the test data memory area 13 of the device under test 12 . In process 203, the instructions set in the test data memory area 13 of the device under test 12 are extracted from the test instruction sequence/test data 3 by the test data setting section 6, and executed by the simulation processing section 8. Processing 2
In step 04, the execution results in the simulation processing unit 8 are saved as expected value data 4. In process 205, the test instruction sequence 13a set in the test data memory area 13 of the device under test 12 is executed on the test execution unit 14 according to the test data 13b. In process 206, the test result determination unit 9 compares the expected value saved in process 204 with the result executed in process 206, and executes the test using the instruction sequence set in the memory area 13 of the device under test 12. Check the normality of execution in 14. If it is normal, it is checked in step 207 whether execution of all instructions in the test instruction sequence has been completed, and if not completed, processing is performed in step 20.
Return to 2.

By repeating the above processes 202 to 207, test instruction strings are accumulated in the memory area 13 of the test target bag [12, and the execution of the accumulated test instruction strings is executed one after another on the test execution unit 14. At the same time, the same test instruction sequence is executed in the simulation processing unit 8 of the test system 1 to confirm normality.

This will be explained in more detail with reference to FIG.

FIG. 3 shows the transition of the test command sequence 13a on the test data memory area 13 in the device under test 12 when the processes 202 to 207 are repeatedly executed. In the first execution of process 202, memory area 13
As shown in 220, an instruction sequence containing only one instruction is set, and the remaining area is filled with an instruction code that generates a trap (generally a software-controllable interrupt) to indicate the end of the test instruction. . In the second execution of process 202, two ordered instruction sequences as shown in 221 are set in the memory area 13, and an instruction code for generating a trap to indicate the end of the test instruction sequence is set in the remaining area. is filled in. When the process 202 has been executed n times, an instruction sequence consisting of n instructions with order is set in the memory area 13 as shown in 222, and a trap is set in the remaining area to indicate the end of the test instruction sequence. The instruction code that generates is filled in.

By processing 202, the memory area 13 of the device under test 12 is
The exact same test command sequence accumulated in the test system 1 is executed in the simulation mode of process 203.
The execution result is saved as expected value data in process 204. Next, in step 205, a test instruction string based on the same test data as that executed in the simulation mode in step 203 is executed on the test execution unit 14 using the instruction string in the memory area 13 of the test electrical equipment R12.

In this way, in the state 222 in FIG. 3, the normality of the execution of the instruction string consisting of n test instructions in the device under test 12 is checked in the test result determination unit 9 in step 206. As a result.

If an abnormality is detected, a process 209 is performed to determine that the error is a result of executing an instruction sequence in which n instructions are accumulated.
In step 210, the error output section 10 outputs the error, and in step 210, the cause is investigated. in this case.

Since the execution of an instruction sequence consisting of up to r>-1 test instructions was normal, it is possible to localize to the nth accumulated test instruction n and pursue the cause of the abnormality.

If no abnormality is detected even after the execution of the test instruction that has accumulated n test instructions, it is checked in step 208 whether the execution of the test instruction sequence including all the instructions has been completed, and if it has not been completed, the process returns to step 202.

Furthermore, the next sequence of sequential test instructions, such as n+1, is created in the test data memory area 13 of the device under test 12.

By repeating the above process, it is possible to check the normality of the operation of the device under test 12 in a state where a test instruction sequence is composed of a plurality of sequential test instructions while accumulating the number of test instructions one instruction at a time. Even if an abnormality is detected, it becomes possible to analyze the contents of the abnormality by limiting it to the storage instruction concerned.

Furthermore, processing 201 to processing 207 and processing 209.21
It is checked in process 208 that 0 has been executed a predetermined number of times, and if the predetermined number of times has not been reached, the execution is repeated. , it is possible to always test with different content.

In addition, in the above process, the test instruction sequence, the test data 35, and the expected value 4 may be incorporated into the test system in advance, instead of being generated from random values. In this case, there is no need to provide the test instruction sequence and test data generation process of process 201. Further, the simulation processing unit 8 is used to execute a test instruction sequence in a pseudo manner to obtain an expected value, and is a method in which a software simulator that satisfies the individual instruction specifications of the test target device 12 is provided in the test system 1. If normal operation is guaranteed by using an actual data processing device whose normal operation has been confirmed for devices other than the target device, or by fixing the operation mode of the device under test, the mode of the device under test 1lt12 may be changed. Either method of fixed execution is possible. Furthermore, it can also be used for error analysis processing when an abnormality is detected by executing a test instruction sequence.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when an abnormality is detected in the execution result of a test instruction sequence after accumulating n test instructions, execution is performed by accumulating up to n-1 test instructions. Since it was normal, the cause of the abnormality can be investigated by localizing it to the nth accumulated test instruction. In addition, it is possible to execute a test instruction sequence consisting of multiple consecutive test instructions with order.
Further effects can be obtained as a test of a data processing device having acceleration logic.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a test system according to the present invention, FIG. 2 is a flowchart for explaining the process shown in FIG. 1, and FIG. Figure 4 shows the transition of the test instruction sequence.
The figure is a flowchart for explaining a conventional test method. DESCRIPTION OF SYMBOLS 1... Test system, 5... Test data storage section, 6... Test data generation section, 7... Test data setting section, 8... Simulation processing section, 9...
・Test result determination section, 10...Error output section, 1
1... Control unit, 12... Test target device. 13...Test data memory area, 14...Test execution unit. Figure 1 Figure 2 Figure 3 Sub L/Izz.

Claims (1)

[Claims] (1) In a test system that tests the normality of a data processing device using an ordered test instruction sequence or test data, a simulation processing unit is provided to execute the test instruction sequence in a pseudo manner, and Extract and accumulate instructions one by one, and for each accumulation, sequentially,
A test method for a data processing device characterized by executing and comparing a sequence of instructions accumulated up to that point in a data processing device under test and a simulation processing unit.