CN116205184A

CN116205184A - Chip verification method, chip verification platform and readable storage medium

Info

Publication number: CN116205184A
Application number: CN202310144169.3A
Authority: CN
Inventors: 周鹏举
Original assignee: Zeku Technology Shanghai Corp Ltd
Current assignee: Zeku Technology Shanghai Corp Ltd
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-06-02

Abstract

The embodiment of the application discloses a chip verification method, a chip verification platform and a readable storage medium, which can improve the efficiency of chip verification. The method comprises the following steps: processing the test data through at least one hardware module corresponding to at least one test point in the chip, and determining at least one first processing result corresponding to the at least one test point; determining at least one first information abstract corresponding to the at least one first processing result through an information abstract calculation module; providing the at least one first information abstract to a chip verification platform so that the chip verification platform can determine at least one verification result corresponding to the at least one test point by comparing the at least one first information abstract with the at least one second information abstract; the at least one second information abstract is at least one information abstract corresponding to at least one second processing result determined by processing the test data through at least one software module corresponding to the at least one hardware module.

Description

Chip verification method, chip verification platform and readable storage medium

Technical Field

The present disclosure relates to the field of chip technologies, and in particular, to a chip verification method, a chip verification platform, and a readable storage medium.

Background

With the increasing scale of integrated circuits (Integrated Circuit Chip, ICs), the complexity of on-chip designs is also increasing. In order to eliminate design defects, ensuring design accuracy and high yield, efficient verification and debugging methods are particularly important.

At present, the IC design verification and debugging method mainly comprises the following steps: design verification (Design Verification, DV), chip verification (Chip Verification, CV), and design for testability (Design For Testability, DFT), and the like. However, using the above verification method generally consumes more time in performing the IC test and debug process, resulting in reduced efficiency of chip verification. .

Disclosure of Invention

The embodiment of the application expects to provide a chip verification method, a chip verification platform and a readable storage medium, and can improve the efficiency of chip verification.

The technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a chip verification method, applied to a chip, including:

processing test data through at least one hardware module corresponding to at least one test point in the chip, and determining at least one first processing result corresponding to the at least one test point;

Determining at least one first information abstract corresponding to the at least one first processing result through an information abstract calculation module;

providing the at least one first information abstract to a chip verification platform so that the chip verification platform can determine at least one verification result corresponding to the at least one test point by comparing the at least one first information abstract with at least one second information abstract; the at least one second information abstract is at least one information abstract corresponding to at least one second processing result determined by processing the test data through at least one software module corresponding to the at least one hardware module.

In a second aspect, an embodiment of the present application provides a chip verification method, applied to a chip verification platform, including:

acquiring at least one first information abstract from the chip; the at least one first information abstract is at least one information abstract corresponding to at least one first processing result determined by processing test data through at least one hardware module corresponding to at least one test point in the chip;

processing the test data through at least one software module corresponding to the at least one hardware module to obtain at least one second processing result corresponding to the at least one test point;

Performing information abstract calculation on the at least one second processing result to determine at least one second information abstract;

and determining at least one verification result corresponding to the at least one test point by comparing the at least one first information abstract with the at least one second information abstract.

In a third aspect, an embodiment of the present application provides a chip verification device, which is applied to a chip verification platform, including:

the acquisition module is used for acquiring at least one first information abstract from the chip; the at least one first information abstract is at least one information abstract corresponding to at least one first processing result determined by processing test data through at least one hardware module corresponding to at least one test point in the chip;

the data processing module is used for processing the test data through at least one software module corresponding to the at least one hardware module to obtain at least one second processing result corresponding to the at least one test point;

the computing module is used for carrying out information abstract computation on the at least one second processing result and determining at least one second information abstract;

and the comparison module is used for determining at least one verification result corresponding to the at least one test point by comparing the at least one first information abstract with the at least one second information abstract.

In a fourth aspect, embodiments of the present application provide a chip, including:

the information abstract calculation module, the first memory and the first processor, wherein,

the first memory is used for storing executable instructions;

the first processor is configured to process test data through at least one hardware module corresponding to at least one test point in the chip, and determine at least one first processing result corresponding to the at least one test point;

determining at least one first information abstract corresponding to the at least one first processing result through the information abstract calculation module;

In a fifth aspect, an embodiment of the present application provides an electronic device, where the above chip provided in the embodiment of the present application is integrated into the electronic device.

In a sixth aspect, an embodiment of the present application provides a chip verification platform, including:

a second memory for storing executable instructions;

and the second processor is used for executing the chip verification method applied to the chip verification platform when executing the executable instructions stored in the second memory.

In a seventh aspect, embodiments of the present application provide a readable storage medium storing executable instructions for implementing, when executed by a first processor, a chip verification method applied to a chip provided by embodiments of the present application; or when the second processor is caused to execute, the chip verification method applied to the chip verification platform is realized.

In an eighth aspect, embodiments of the present application provide a computer program product comprising a computer program or instructions that, when executed by a processor, implement the chip authentication method provided by embodiments of the present application.

The embodiment of the application provides a chip verification method, a chip verification platform and a readable storage medium, wherein test data are processed through at least one hardware module corresponding to at least one test point in the chip to obtain at least one first processing result corresponding to the at least one test point, and at least one first information abstract corresponding to the at least one first processing result is calculated through an information abstract calculation module; in this way, the verification result of the test point can be determined by comparing the first information abstract obtained by processing the test data by the hardware module with the second information abstract obtained by processing the test data by the software module on the chip verification platform. Because the information abstract data size is small, the comparison is easy, and the calculation consumption resource is low, the verification result of each test point can be obtained quickly, and further, the fault location and the further debugging can be realized quickly by comparing the verification results of each test point, so that the efficiency of chip verification is improved.

Drawings

Fig. 1 is a schematic flow chart of an alternative application of the chip verification method provided in the embodiment of the present application to a chip;

fig. 2 is a schematic flow chart of an alternative application of the chip verification method provided in the embodiment of the present application to a chip;

FIG. 3 is a schematic diagram of an alternative process of performing, by a message digest calculation module, message digest calculation on a selected test point on a chip according to an embodiment of the present application;

fig. 4 is a schematic flow chart of an alternative application of the chip verification method provided in the embodiment of the present application to a chip;

FIG. 5 is a schematic diagram of an alternative process for cryptographic hash function calculation by sub-message splitting according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of an alternative application of the chip verification method provided in the embodiment of the present application to a chip verification platform;

fig. 7 is a schematic diagram of an alternative process of applying the chip verification method provided in the embodiment of the present application to an actual scenario;

fig. 8 is a schematic structural diagram of an alternative chip verification device according to an embodiment of the present application;

FIG. 9 is a schematic diagram of an alternative structure of a chip according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of an alternative chip verification platform according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings, and the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a specific order or sequence, as permitted, to enable embodiments of the application described herein to be practiced otherwise than as illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

Before further describing embodiments of the present application in detail, the terms and expressions that are referred to in the embodiments of the present application are described, and are suitable for the following explanation.

1) The cryptographic hash function (Cryptographic Hash Function, CHF) is a one-way hash function that compresses messages of arbitrary length to a certain fixed-length message digest, an ideal cryptographic hash function should have four main characteristics: for any given message, it is easy to calculate the hash value. It is difficult to extrapolate the original message from a known hash value. Modifying the message content is not feasible without changing the hash value. For two different messages, it cannot be given the same hash value. The information digest generated by the one-way hash function is unpredictable and appears to have no relation to the original data. Moreover, any minor variations in the original data can have a significant impact on the generated message digest.

2) Message digest algorithm-4 (Message Digest Algorithm-4, MD4).

3) Message digest algorithm-5 (Message Digest Algorithm-5, MD5).

4) Secure hash algorithm-1 (Secure Hash Algorithm-1, SHA-1).

5) Secure hash algorithm-256 (Secure Hash Algorithm-256, SHA-256)

6) Secure hash algorithm-384 (Secure Hash Algorithm-384, SHA-384)

7) Secure hash algorithm-512 (Secure Hash Algorithm-512, SHA-512)

8) Design verification (Design Verification, DV)

9) Chip authentication (Chip Verification, CV)

At present, the DV verification method is widely applied to front-end design, can quickly help a Designer to find out design defects in the early stage, verifies the completeness of design ideas, and has the characteristics of rapidness and high efficiency. However, the DV validation method is only suitable for short-time test cases, and is extremely time-consuming for long-time tests, such as scene-level tests.

CV verification can be performed on a large verification platform for scene level testing or for playing up testing after film-back. However, the debugging of the CV verification method is inefficient, and once a problem is found, it can take days, or even weeks, to locate the problem.

The DFT test method is widely applied to automatic test equipment (Automatic Test Equipment, ATE) test, and can rapidly complete logic circuit fault detection. The fault detection is based on netlist detection, and besides design defects, the fault also comprises manufacturing defects, so that fault analysis is more complicated and time-consuming in problem positioning.

In addition, although the verification methods can be applied to different links of chip design, manufacture and production, the design and production links of the whole chip cannot be covered, so that the complexity of debugging the whole link is increased.

In summary, the current chip verification method is complex and takes a long time, so that the efficiency of chip verification is reduced.

The embodiment of the application provides a chip verification method, a chip verification platform and a readable storage medium, which can improve the efficiency of chip verification.

Referring to fig. 1, fig. 1 is a schematic flow chart of an application of the chip verification method provided in the embodiment of the present application to a chip, and will be described with reference to the steps shown in fig. 1.

S101, processing test data through at least one hardware module corresponding to at least one test point in a chip, and determining at least one first processing result corresponding to the at least one test point.

In the embodiment of the application, the chip is connected with the chip verification platform, the chip is a verification object of chip verification, and the chip verification platform is used for verifying the chip.

The chip of the embodiment of the application comprises at least one hardware module. And at least one test point is arranged in the chip and distributed on the input port and/or the output port of the at least one hardware module, that is, the at least one test point corresponds to the at least one hardware module.

In this embodiment of the present application, the test data may be input to the chip by the chip verification platform, or may be input to the chip by other devices or apparatuses. At least one hardware module in the chip is connected in a preset manner.

In some embodiments, the test data may be input to an input port of the chip, and the test data is processed by a first hardware module connected to the input port in at least one hardware module, so as to obtain output data of the first hardware module, and according to the output data of the first hardware module, a first processing result of a test point corresponding to the first hardware module is determined. And processing the output data of the hardware modules connected at the previous stage through the rest of each hardware module in at least one hardware module to obtain the output data of each rest of hardware modules, thereby obtaining a first processing result corresponding to the test point of the input port and/or the output port of each hardware module.

In some embodiments, the test data may also be directly input into an input port of one or more hardware modules in the at least one hardware module, and the at least one hardware module processes the test data based on the input data of the respective input port to determine data of an input port and/or an output port of each module in the at least one hardware module, thereby determining at least one first processing result corresponding to the at least one test point. Here, the input data of each hardware module may be test data or output data of a previous stage connection module.

In some embodiments, based on the function or type of the chip, the test data may be data in the form of images, audio, video, etc., which are specifically selected according to the actual situation, and the embodiments of the present application are not limited.

S102, determining at least one first information abstract corresponding to the at least one first processing result through the information abstract calculation module.

In the embodiment of the application, the chip contains a information abstract calculation module which is realized by hardware and is used for calculating the information abstract of the information or data. Here, the message and the data may be the first processing result. The chip can calculate the information abstract of each first processing result in the at least one first processing result through the information abstract calculation module, and determine the first information abstract corresponding to each first processing result, so as to determine the at least one first information abstract.

In some embodiments, the chip may perform the information digest calculation of the at least one first processing result in a synchronous manner, or may perform the calculation sequentially or in any execution manner or order until the at least one first information digest is obtained. The selection is specifically selected according to the actual situation, and the embodiment of the application is not limited.

In some embodiments, the chip may perform cryptographic hash function calculation on each first processing result of the at least one first processing result through the information digest calculation module to determine a first information digest corresponding to each first processing result, thereby determining the at least one first information digest.

Illustratively, the cryptographic hash function may include: any of MD4, MD5, SHA-1, SHA-256, SHA-384, or SHA-512.

In the embodiment of the application, because CHF calculation is mainly loop logic calculation and addition and subtraction operation, the consumption of hardware resources is small; moreover, the length of the information abstract generated by CHF is fixed, and the comparison and verification are easy to carry out. Therefore, the characteristics of fixed-length output, irreversibility and data integrity of the password hash function can be utilized to verify the data flow of the test data among all test points, quickly locate fault points and accelerate chip design and manufacturing iteration.

S103, providing at least one first information abstract to a chip verification platform so that the chip verification platform can determine at least one verification result corresponding to at least one test point by comparing the at least one first information abstract with at least one second information abstract; the at least one second information abstract is the information abstract corresponding to the at least one second processing result determined by processing the test data through at least one software module corresponding to the at least one hardware module.

In the embodiment of the application, the chip corresponds to a software model with completed debugging, and the software model with completed debugging comprises at least one software module. At least one software module is in one-to-one correspondence with at least one hardware module in the chip. Illustratively, in the design phase, a software model of the chip may be built from software modules by software modeling; in the software debugging stage, the software (simulation) debugging process can be adopted, for example, the software model is debugged by inputting debugging data; and according to the debugging result, the parameters of the software modules are adjusted, so that the output of each software module in the software model after the debugging is finished, namely the data processing result can reach the expected value. In the hardware implementation stage, hardware implementation is performed according to the software model after debugging, and the chip is obtained by implementing each software module in the software model as a corresponding hardware module. In this way, in the debugging stage of the chip, whether the hardware module works normally can be determined by comparing whether the processing results of the hardware module and the corresponding software module for the same test data are consistent.

In the embodiment of the application, whether the processing results of the software module and the hardware module on the same test data are consistent or not is determined through comparison of the information abstracts. The chip provides at least one first information abstract corresponding to the at least one test point, namely, the information abstract obtained by processing test data by at least one hardware module to the chip verification platform, the chip verification platform compares the at least one first information abstract with at least one second information abstract obtained by processing the test data by at least one software module, and at least one verification result corresponding to the at least one test point is determined according to whether the comparison results are consistent or not. The at least one second information abstract is at least one second processing result determined by processing the test data through at least one software module, and the information abstract of each second processing result in the at least one second processing result is calculated through a software-implemented information abstract algorithm.

It can be understood that, the test data is processed by at least one hardware module corresponding to at least one test point in the chip to obtain at least one first processing result corresponding to at least one test point, and at least one first information abstract corresponding to at least one first processing result is calculated by the information abstract calculation module; in this way, the verification result of the test point can be determined by comparing the first information abstract obtained by processing the test data by the hardware module with the second information abstract obtained by processing the test data by the software module on the chip verification platform. Because the information abstract data size is small, the comparison is easy, and the calculation consumption resource is low, the verification result of each test point can be obtained quickly, and further, the fault location and the further debugging can be realized quickly by comparing the verification results of each test point, so that the efficiency of chip verification is improved.

In some embodiments, S001-S002 may also be performed prior to S101, as shown in fig. 2, as follows:

s001, determining at least one candidate test point by receiving a test point setting command issued by the chip verification platform.

In the embodiment of the application, the user can set the test point in the chip through the chip verification platform based on the software model of the chip. The chip verification platform generates a test point setting command according to the test point set by the user and transmits the test point setting command to the chip, and the chip determines at least one candidate test point by receiving the test point setting command transmitted by the chip verification platform.

S002, determining at least one test point based on the at least one candidate test point.

In the embodiment of the application, the chip can determine at least one test point used for the current chip verification process based on at least one candidate test point.

In some embodiments, the electronic device may directly use at least one candidate test point as the at least one test point, or may also determine the at least one test point by receiving a test point selection command issued by the chip verification platform, where the candidate test point specified by the test point selection command is used as the at least one test point. The selection is specifically selected according to the actual situation, and the embodiment of the application is not limited.

That is, the user may also select at least one test point for the current chip verification process from the set at least one candidate test point through the chip verification platform, and issue the test point selection command to the chip through the chip verification platform. In this way, the chip may determine at least one test point among the at least one candidate test points by receiving a test point selection command issued by the chip verification platform. For the next chip verification process, a test point for the next chip verification process may also be selected at the at least one candidate test point by a test point selection command. Here, the one chip verification process may correspond to one or more test cases for chip verification, and specifically is selected according to practical situations, which is not limited in this embodiment of the present application.

Illustratively, as shown in fig. 3, the chip includes at least one connected hardware module (i.e., functional module 1, functional module 2, functional module 3, etc.), and by receiving a test point setting command, the chip determines at least one candidate test point on the input/output port of each functional module, such as test point 1, test point 2, test point 3, test point 4, and test point 5 shown in fig. 3. The chip selects one or more test points which are finally subjected to information abstract comparison verification from the test points 1-5 as at least one test point through a test selection module according to the received test point selection command, and sends the at least one test point into an information abstract calculation module in the chip to calculate at least one corresponding first information abstract. Therefore, under the condition that the verification result of the test point 1 is normal and the verification result of the test point 2 is abnormal by comparing the software and hardware information abstracts on the chip verification platform, the fault of the functional module 1 can be positioned.

It can be understood that by receiving the test point setting command and the test point selection command, flexible configuration adjustment of test point setting in the chip is realized, and debugging resources are optimized. And through reasonable planning of test points, the whole design production link can be covered, and quick fault positioning and debugging are facilitated, so that the efficiency of chip verification is improved.

In some embodiments, the on-chip information digest calculation module may include at least one cryptographic hash function calculation module. In this way, for each first processing result in the at least one first processing result, that is, the first processing result corresponding to each test point, the first information digest corresponding to each first processing result may be determined by performing a cryptographic hash function calculation on each first processing result through each cryptographic hash function calculation module in the at least one cryptographic hash function calculation module. That is, the information abstract of at least one test point can be synchronously calculated through at least one password hash function calculation module, so that the information abstract calculation efficiency is improved, and the chip verification efficiency is further improved.

In some embodiments, for the case where the information digest calculation module includes at least one cryptographic hash function calculation module, S102 described above may also be implemented by executing S1021-S1023 as follows:

s1021, extracting a first message with a preset message length from each first processing result of at least one first processing result.

In this embodiment of the present application, an appropriate data stream length may be preset as a message length according to a data stream characteristic of test data. For example, for an image data stream, the length of one frame may be taken as a preset message length, i.e. one frame image is taken as one first message.

S1022, dividing the first message, and determining at least one first sub-message.

In the embodiment of the application, because the possible data size of the first message is larger, the calculation efficiency is affected by directly performing information abstract calculation on the first message; alternatively, the data size of the first message may directly exceed the maximum data size that can be handled by a cryptographic hash function calculation module. Thus, the first message needs to be partitioned and at least one first sub-message is determined.

In some embodiments, the sub-message division may be based on the data flow characteristics of the test data. Illustratively, the number of sub-messages in the first message may be determined by equation (1) and equation (2), as follows:

n=ceil (preset message length/preset data stream bit width) (1)

In the formula (1), ceil represents a rounding-up process. The preset data stream bit width is the bit width of the data stream formed by processing the hardware modules based on the test data and transmitting the processing results. N represents the sub-message length. Through the formula (1), the sub-message length N can be determined according to the ratio of the preset message length to the preset data stream bit width.

It should be noted that, if the cryptographic hash function calculation module has a limitation on the message length, the divided sub-message length N needs to satisfy the limitation on the message length, that is, the sub-message needs to have a length less than or equal to the maximum message length that can be processed by the cryptographic hash function calculation module. And if the sub-message length N is larger than the maximum message length which can be processed by the password hash function calculation module, taking the maximum message length which can be processed by the password hash function calculation module as the sub-message length N.

Number of sub-messages = ceil (M/N) (2)

In equation (2), M is the number of clocks required by the hardware to process data of a predetermined message length, that is, the number of clocks required by the hardware to process a first message. Through the formula (2), the number of the sub-messages can be determined according to the ratio of the hardware processing clock number M to the length N of the sub-messages; the first message is further divided into at least one first sub-message based on the number of sub-messages.

S1023, performing password hash function calculation on at least one first sub-message synchronization through at least one password hash function calculation module, and determining at least one first sub-message digest as a first message digest corresponding to each first processing result, thereby determining at least one first message digest corresponding to at least one first processing result.

In the embodiment of the application, through at least one cryptographic hash function calculation module, digest calculation is independently and parallelly performed on each first sub-message in at least one first sub-message to obtain at least one first sub-message digest, and the at least one first sub-message digest is used as a first message digest corresponding to each first processing result, so that at least one first message digest corresponding to the at least one first processing result is determined.

For example, as shown in fig. 5, after dividing the first message into at least one first sub-message, at least one cryptographic hash function calculation module, that is, CHF1-N, performs independent synchronization calculation on each divided sub-message to obtain a first sub-message digest corresponding to each first sub-message.

Referring to fig. 6, fig. 6 is a schematic flowchart of an alternative application of the chip verification method provided in the embodiment of the present application to the chip verification platform, and will be described with reference to the steps shown in fig. 6.

S201, at least one first information abstract is obtained from the chip.

In the embodiment of the application, a chip verification platform acquires at least one first information abstract from a tested chip side; the at least one first information abstract is at least one information abstract corresponding to at least one first processing result determined by processing the test data through at least one hardware module corresponding to at least one test point in the chip.

S202, processing the test data through at least one software module corresponding to at least one hardware module to obtain at least one second processing result corresponding to at least one test point.

In the embodiment of the application, the chip verification platform processes the test data through at least one software module corresponding to at least one hardware module to obtain at least one second processing result corresponding to at least one test point. Here, the at least one software module is a module in the software model for which debugging is completed corresponding to the chip. It is understood that, since at least one hardware module corresponds to at least one software module, at least one hardware module corresponds to at least one test point, at least one software module also corresponds to at least one test point.

S203, performing information abstract calculation on at least one second processing result to determine at least one second information abstract.

S204, determining at least one verification result corresponding to the at least one test point by comparing the at least one first information abstract with the at least one second information abstract.

In the embodiment of the application, the chip verification platform performs information abstract calculation on at least one second processing result obtained by processing at least one software module to obtain at least one second information abstract corresponding to at least one test point. Furthermore, for each test point in the at least one test point, the verification result of each test point can be obtained by comparing the first information abstract and the second information abstract corresponding to each test point, so as to obtain at least one verification result corresponding to the at least one test point.

Here, the algorithm used by the chip verification platform to perform the information digest calculation on the at least one second processing result needs to be consistent with the algorithm used by the on-chip information digest calculation module.

In some embodiments, as described in S1021-S1023 above, in the case that the chip extracts the first message from each first processing result, divides the first message, determines at least one first sub-message, and calculates at least one first sub-information digest corresponding to the at least one first sub-message, correspondingly, for each second processing result, the chip verification platform extracts the second message from each second processing result in the same manner as the chip side, divides the second message into at least one second sub-message, synchronously performs cryptographic hash function calculation on the at least one second sub-message, determines at least one second sub-information digest as a second information digest corresponding to each second processing result, and thereby determines at least one second information digest corresponding to the at least one second processing result.

In some embodiments, for each test point in at least one test point, determining that the verification result of the test point is normal if the first information abstract corresponding to the test point is consistent with the second information abstract; and under the condition that the first information abstract corresponding to the test point is inconsistent with the second information abstract, determining that the verification result of the test point is abnormal.

It should be noted that, for the case that the first message digest of a certain test point includes at least one first sub-message digest and the second message digest includes at least one second sub-message digest, it is required that at least one first sub-message digest is identical to at least one second sub-message digest by comparison, and it is determined that the first message digest is identical to the second message digest. And under the condition that the sub-information summaries of which the comparison is inconsistent exist in at least one first sub-information summary and at least one second sub-information summary of the test point, determining that the first information summary is inconsistent with the second information summary.

In some embodiments, prior to S101, the chip verification platform may further determine at least one candidate test point by receiving a user' S set test point operation; generating a test point setting command containing at least one candidate test point, and issuing the test point setting command to the chip, so that the chip determines at least one test point based on the at least one candidate test point.

In some embodiments, the chip verification platform may further determine at least one test point of the at least one candidate test point according to a test point selection operation input by a user; generating a test point selection command containing at least one test point, and issuing the test point selection command to the chip.

Next, a process of applying the chip verification method in the embodiment of the present application to an actual scene will be described with reference to fig. 7.

S301, selecting test points.

In S301, the chip determines at least one test point corresponding to at least one hardware module in the chip by receiving a test point setting command and a test point selection command issued by the chip verification platform. One test point is selected from at least one test point for verification.

S302, calculating a hardware password hash function.

In S302, for the currently selected test point, a hardware module corresponding to the test point performs hardware cryptographic hash function calculation based on the first processing result of the test data by using an information abstract calculation module implemented by internal hardware of the chip, so as to obtain a hardware information abstract corresponding to the test point, i.e. a first information abstract.

Here, the process in S302 is identical to the process description in S102, and will not be repeated here.

S303, calculating a software password hash function.

In S303, for the software module corresponding to the test point, the chip verification platform performs software cryptographic hash function calculation according to the second processing result of the software module corresponding to the test point based on the test data, to obtain a software information abstract corresponding to the test point, that is, a second information abstract.

Here, the process in S302 is identical to the process description of S203 described above, and will not be repeated here.

Here, S302 and S303 may be executed synchronously, or may be executed in any order, and specifically, the selection is performed according to the actual situation, which is not limited in the embodiment of the present application.

S304, comparing the hardware information abstract with the software information abstract.

In S304, the chip sends the hardware information abstract of the test point to the chip verification platform, and the chip verification platform compares the hardware information abstract of the test point with the software information abstract to determine the comparison result.

S305, fault judgment.

In S305, it is determined whether the test point is a failure point according to the comparison result of S304. And under the condition that the hardware information abstract and the software information abstract of the test points are consistent in comparison, the verification result is normal, the test points are normal test points, and the step S301 is continuously executed, and the next test point is selected from at least one test point for verification. If the comparison of the hardware information abstract and the software information abstract at the test point is inconsistent, the verification result is abnormal, and S306 is executed.

S306, positioning as a fault point.

In S306, the test point where the comparison of the hardware information abstract and the software information abstract is inconsistent is determined as the fault point.

It can be understood that the embodiment of the application can flexibly adjust configuration according to different checked objects and optimize debugging resources. Moreover, because CHF calculation is mainly loop logic calculation and addition and subtraction operation, the consumption of hardware resources is small; the digest length generated by CHF is fixed length, and is easy to compare and check, so that the fixed-length output, the irreversibility and the data integrity of the password hash function can be used as verification means to check the data flow, quickly locate fault points and accelerate chip design and manufacturing iteration. The method and the device are suitable for a plurality of links and verification debugging before, during and after chip verification, the comparison data size is small, the verification result can be obtained rapidly no matter which link, and the efficiency of chip verification is greatly improved.

Based on the implementation basis of the foregoing embodiments, as shown in fig. 8, an embodiment of the present application provides a chip verification apparatus 1, applied to a chip verification platform, including:

an obtaining module 11, configured to obtain at least one first information summary from a chip; the at least one first information abstract is at least one information abstract corresponding to at least one first processing result determined by processing test data through at least one hardware module corresponding to at least one test point in the chip;

a data processing module 12, configured to process, by using at least one software module corresponding to the at least one hardware module, the test data to obtain at least one second processing result corresponding to the at least one test point;

a calculation module 13, configured to perform information summary calculation on the at least one second processing result, and determine at least one second information summary;

a comparing module 14, configured to determine at least one verification result corresponding to the at least one test point by comparing the at least one first information digest with the at least one second information digest.

In some embodiments, the comparing module 14 is further configured to determine, for each of the at least one test point, that the verification result of the test point is normal if the first information digest corresponding to the test point is consistent with the second information digest; and under the condition that the first information abstract corresponding to the test point is inconsistent with the second information abstract, determining that the verification result of the test point is abnormal.

In some embodiments, the chip verification device 1 further includes a test point setting module, where the test point setting module is configured to determine at least one candidate test point by receiving a user's operation of setting a test point before obtaining at least one first information summary from a chip; generating a test point setting command containing the at least one candidate test point, and issuing the test point setting command to the chip so that the chip determines the at least one test point based on the at least one candidate test point.

The test point setting module is further used for determining the at least one test point in the at least one candidate test point according to test point selection operation input by a user; generating a test point selection command containing the at least one test point, and transmitting the test point selection command to the chip.

It should be noted that the description of the above device embodiments is similar to the description of the method embodiments described above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

The embodiment of the application also provides a chip, and fig. 9 is an optional structural schematic diagram of the chip provided in the embodiment of the application. As shown in fig. 9, the chip 2 includes: the information summary calculation module 21, the first memory 22 and the first processor 23. Wherein the first memory 22 and the first processor 23 are connected by a first communication bus 24; a first memory 22 for storing executable instructions; the first processor 23 is configured to implement the chip verification method applied to the chip provided in the embodiment of the present application by using the information digest calculation module 21 when executing the executable instructions stored in the first memory 22.

The first processor 23 is configured to process test data through at least one hardware module corresponding to at least one test point in the chip, and determine at least one first processing result corresponding to the at least one test point;

the information abstract calculation module 21 is configured to determine at least one first information abstract corresponding to the at least one first processing result; and providing the at least one first information abstract to a chip verification platform, so that the chip verification platform determines at least one verification result corresponding to the at least one test point by comparing the at least one first information abstract with at least one second information abstract; the at least one second information abstract is at least one information abstract corresponding to at least one second processing result determined by processing the test data through at least one software module corresponding to the at least one hardware module.

In some embodiments, the information digest calculation module 21 is further configured to perform a cryptographic hash function calculation on each first processing result in the at least one first processing result, and determine a first information digest corresponding to each first processing result, thereby determining the at least one first information digest.

In some embodiments, the first processor 23 is further configured to determine, by receiving a test point setting command issued by the chip verification platform, at least one candidate test point before determining, by the at least one hardware module in the chip, the at least one first processing result corresponding to the at least one test point in the chip; the at least one test point is determined based on the at least one candidate test point.

In some embodiments, the first processor 23 is further configured to receive a test point selection command issued by the chip verification platform; and determining the at least one test point by the test point selection command, wherein the candidate test point is designated in the at least one candidate test point.

In some embodiments, the information summary calculation module 21 includes: at least one cryptographic hash function calculation module; the information abstract calculation module 21 is further configured to extract a first message with a preset message length from each first processing result; dividing the first message and determining at least one first sub-message; and performing password hash function calculation on the at least one first sub-message synchronization through the at least one password hash function calculation module to determine at least one first sub-message digest as the first message digest.

In some embodiments, the information summary calculation module 21 is further configured to determine a sub-message length according to a ratio of the preset message length to a preset data stream bit width; determining the hardware processing clock number corresponding to the preset message length; determining the number of sub-messages according to the ratio of the hardware processing clock number to the sub-message length; and dividing the first message based on the number of the sub-messages to determine at least one first sub-message.

In some embodiments, the information digest calculation module 21 is further configured to perform, by using each cryptographic hash function calculation module in the at least one cryptographic hash function calculation module, cryptographic hash function calculation on each first processing result, and determine a first information digest corresponding to each first processing result

The embodiment of the application also provides electronic equipment, and the chip provided by the embodiment can be integrated in the electronic equipment. Referring to fig. 9, the chip 2 may include: a message digest calculation module 21, a first processor 23, and a first memory 22 storing instructions executable by the first processor; the first processor 23 and the first memory 22 communicate via a first communication bus 24; the first processor 23 may call and execute executable instructions from the first memory 22, and implement the chip verification method applied to the chip provided in the embodiment of the present application through the information digest calculation module 21.

The embodiment of the present application further provides a chip verification platform, referring to fig. 10, the chip verification platform 3 includes: the second memory 32 and the second processor 33. Wherein the second memory 32 and the second processor 33 are connected by a second communication bus 34; a second memory 32 for storing executable instructions; the second processor 33 is configured to implement the chip verification method applied to the chip provided in the embodiment of the present application when executing the executable instructions stored in the second memory 32.

The embodiment of the application provides a readable storage medium storing executable data instructions, which when executed by the first processor, cause the first processor to execute the chip verification method applied to the chip provided by the embodiment of the application; when the executable data instruction is executed by the second processor, the second processor is caused to execute the chip verification method applied to the chip verification platform provided in the embodiment of the application.

In some embodiments, the readable storage medium may be a computer readable storage medium; the computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; but may be a variety of devices including one or any combination of the above memories.

In some embodiments, the executable data instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

As an example, executable data instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a hypertext markup language (HTML, hyper Text Markup Language) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).

As an example, executable data instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or, alternatively, distributed across multiple sites and interconnected by a communication network.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modifications, equivalent substitutions, improvements, etc. that are within the spirit and scope of the present application are intended to be included within the scope of the present application.

Claims

1. A chip verification method applied to a chip, comprising:

2. The method of claim 1, wherein determining, by the message digest calculation module, at least one first message digest corresponding to the at least one first processing result comprises:

and carrying out cryptographic hash function calculation on each first processing result in the at least one first processing result through the information digest calculation module, and determining a first information digest corresponding to each first processing result, thereby determining the at least one first information digest.

3. The method according to claim 1 or 2, wherein before said processing the test data by the at least one hardware module in the chip to determine at least one first processing result corresponding to at least one test point in the chip, the method further comprises:

determining at least one candidate test point by receiving a test point setting command issued by the chip verification platform;

the at least one test point is determined based on the at least one candidate test point.

4. The method of claim 3, wherein the determining the at least one test point based on the at least one candidate test point comprises:

receiving a test point selection command issued by the chip verification platform;

and determining the at least one test point by the test point selection command, wherein the candidate test point is designated in the at least one candidate test point.

5. The method of claim 2, wherein the message digest calculation module comprises: at least one cryptographic hash function calculation module; the step of performing, by the information digest calculation module, cryptographic hash function calculation on each first processing result in the at least one first processing result, and determining a first information digest corresponding to each first processing result includes:

Extracting first messages with preset message lengths from each first processing result;

dividing the first message and determining at least one first sub-message;

and performing password hash function calculation on the at least one first sub-message synchronization through the at least one password hash function calculation module to determine at least one first sub-message digest as the first message digest.

6. The method of claim 5, wherein the dividing the first message to determine at least one first sub-message comprises:

determining the length of the sub-message according to the ratio of the length of the preset message to the bit width of the preset data stream;

determining the hardware processing clock number corresponding to the preset message length;

determining the number of sub-messages according to the ratio of the hardware processing clock number to the sub-message length;

and dividing the first message based on the number of the sub-messages to determine at least one first sub-message.

7. The method of claim 2, wherein the message digest calculation module comprises: at least one cryptographic hash function calculation module; the step of performing, by the information digest calculation module, cryptographic hash function calculation on each first processing result in the at least one first processing result, and determining a first information digest corresponding to each first processing result includes:

And performing password hash function calculation on each first processing result through each password hash function calculation module in the at least one password hash function calculation module, and determining a first information abstract corresponding to each first processing result.

8. The chip verification method is applied to a chip verification platform and is characterized by comprising the following steps of:

9. The method of claim 8, the determining at least one verification result corresponding to the at least one test point by comparing the at least one first information digest with the at least one second information digest, comprising:

for each test point in the at least one test point, determining that the verification result of the test point is normal under the condition that the first information abstract corresponding to the test point is consistent with the second information abstract;

and under the condition that the first information abstract corresponding to the test point is inconsistent with the second information abstract, determining that the verification result of the test point is abnormal.

10. The method according to claim 8 or 9, wherein before the obtaining at least one first information digest from the chip, the method further comprises:

determining at least one candidate test point by receiving a user test point setting operation;

generating a test point setting command containing the at least one candidate test point, and issuing the test point setting command to the chip so that the chip determines the at least one test point based on the at least one candidate test point.

11. The method according to claim 10, wherein the method further comprises:

Determining at least one test point in the at least one candidate test point according to a test point selection operation input by a user;

generating a test point selection command containing the at least one test point, and transmitting the test point selection command to the chip.

12. A chip verification device, characterized in that it is applied to a chip debugging platform, comprising:

13. A chip, comprising: the information abstract calculation module, the first memory and the first processor, wherein,

the first memory is used for storing executable instructions;

the information abstract calculation module is used for determining at least one first information abstract corresponding to the at least one first processing result; and providing the at least one first information abstract to a chip verification platform, so that the chip verification platform determines at least one verification result corresponding to the at least one test point by comparing the at least one first information abstract with at least one second information abstract; the at least one second information abstract is at least one information abstract corresponding to at least one second processing result determined by processing the test data through at least one software module corresponding to the at least one hardware module.

14. An electronic device, wherein the chip of claim 13 is integrated into the electronic device.

15. A chip authentication platform, comprising:

a second memory for storing executable instructions;

a second processor for implementing the method of any one of claims 8 to 11 when executing executable instructions stored in the second memory.

16. A readable storage medium storing executable instructions for causing a first processor to perform the method of any one of claims 1 to 7; or for causing the method of any one of claims 8 to 11 to be carried out when executed by a second processor.