JP5181699B2 - Computer test method, program, and information processing apparatus - Google Patents

Description

  The present invention relates to a technology for performing a system test of an information processing apparatus using a test instruction sequence (test program), and in particular, an instruction sequence including an instruction that causes a failure when a failure is detected in the test. The present invention relates to a computer test method, a program, and an information processing apparatus for automatically narrowing down the scope of information.

  As a test method for an information processing system, there is a method for performing a test by causing a test instruction sequence (test program) to be executed by an information processing apparatus to be tested. Hereinafter, a test instruction sequence generated using random numbers is referred to as a random instruction sequence, and an information processing system test using the random instruction sequence is referred to as a random instruction sequence test.

  Conventionally, for example, the following methods (i) and (ii) have been conceived as methods for narrowing down the failure location by a program that executes a random instruction sequence test.

  (I) When a failure is detected in the random instruction sequence test, a plurality of instructions are deleted from the top of the random instruction sequence. Instructions to be deleted may be from tens to hundreds or thousands of instructions. The instruction sequence of the deleted part is executed in advance by the software simulator. The environment of the execution result by the software simulator, that is, the contents of all control registers and test target memory are set as initialization data, and the remaining instruction sequence after deletion is executed by the information processing system to be tested. Theoretically, the same operation as the random instruction sequence before partial deletion is performed. Such an operation is repeated while changing the number of instructions to be deleted, and the trouble spots are narrowed down.

  (Ii) When a failure is detected in the random instruction sequence test, the instruction at a location not far from the location where the failure of the random instruction sequence is considered to have occurred is rewritten as a trap instruction. The rewritten random instruction sequence is executed in the information processing system to be tested, and logs of all control registers and test target memory are collected at the rewritten trap instruction portion. The log collected in this way is compared with a log collected by executing a rewritten random instruction sequence in advance with a software simulator. Alternatively, the rewritten random instruction sequence is executed twice by the information processing apparatus to be tested, and the logs collected as the results of the two tests are compared. Such work is repeated by changing the place of rewriting to the trap instruction by OK / NG of the log comparison result, and narrowing down the faulty part.

As a prior art document describing a technique for testing an information processing system using a random instruction sequence test, there is, for example, Patent Document 1. In Patent Document 1, a test instruction sequence generated using a random value is generated, and the generated test instruction sequence is executed by a software simulator and a test target device. A technique for detecting an abnormality by comparing the above is described.
Japanese Unexamined Patent Publication No. 64-23344

  The problem with the random instruction sequence test shown in (i) and (ii) above is that the instruction sequence is rewritten.

  The processor hardware has various mechanisms such as cache control, instruction pipeline control, advance control, branch prediction control, simultaneous execution control of multiple instructions, and RAS control in order to improve its performance. , If the environment changes even a little, the internal state of the hardware will change significantly. As a result, there is a possibility that the failure occurrence timing is shifted due to rewriting of the instruction sequence and the failure is not reproduced.

  In the methods shown in (i) and (ii) above, the instruction sequence is clearly changed, so the hardware internal state is likely to deviate from the failure occurrence timing, and the failure may be reproduced. Will also be low. For this reason, in order to realize the narrowing down of the fault location while reproducing the fault, it is necessary to narrow down the fault location with the same instruction sequence without changing the instruction sequence in which the fault is detected.

  It is an object of the present invention to provide a technique for narrowing down fault locations without changing a test instruction sequence.

  Two types of traps, software traps and hardware traps, are prepared as triggers for collecting logs in information processing system tests using test instruction sequences. A software trap is an interrupt generated by a trap instruction embedded in a test instruction sequence. A hardware trap is an interrupt generated as a result of executing an instruction in the test instruction sequence.

  In addition, two log types, a full log and a simple log, are prepared as log types to be collected when a trap occurs. Full log collection collects a wide range of computer states, such as registers and memory data. In simple log collection, only the state of a computer in a narrower range than the full log, for example, register data is collected.

  By using these software traps / hardware traps and full log / simple log, it is possible to detect failures due to execution of test instruction sequences and narrow down the range of instruction sequences including instructions that cause failures. .

Specifically, a failure detection unit for detecting failures by executing the test program, the computer test method information processing apparatus performs and a failure source refining unit to narrow the fault location of the test program failure is detected, failure The detection unit executes the test program in which the trap instruction is embedded multiple times, collects the first log, which is a log of register and memory data, at the time of software trap by the trap instruction in the execution of the test program, and at the time of hardware trap The second log, which is the register log, is collected. The first and second logs collected during the execution of one test program, the first log collected during the execution of another test program, and Compared to the second log, the software immediately before the log collection location that did not match The process of detecting the instruction sequence from the location where the trap occurred to the log collection location where there was a mismatch as the fault instruction sequence, and the fault source narrowing section execute the test program multiple times, The first log is collected at one hardware trap, and the first log collected during the execution of a test program matches the first log collected during the execution of another test program. If they match, it is assumed that the instruction sequence behind the matched log collection location is the failure instruction sequence. If there is a mismatch, the command sequence before the matched log collection location is And a process of narrowing down the failure source as a failure occurrence instruction sequence.

In the computer test method described above, the second failure source narrowing unit further provided in the information processing apparatus includes a hardware function unit that generates a hardware trap when an instruction at a set address is executed. The address of one of the instructions is set, the test program is executed multiple times, the first log is collected at the time of hardware trap by the hardware function part in executing the faulty instruction sequence, and the test program is executed once The first log collected in step 1 is compared with the first log collected in the other test program executions. If the instruction sequence is a failure instruction sequence, and there is a mismatch, the instruction sequence before the matched log collection location is the failure instruction sequence It may have a process to narrow down the failure source is.

In the above computer test method, even if the first log is a log of all registers that can be referred to and the data in the memory area to be tested, and the second log is a log of data in the registers of the current window. Good.

Further, the computer test program includes an information processing apparatus including a failure detection unit that detects a failure by executing the test program and a failure source narrowing unit that narrows down a failure location of the test program in which the failure is detected. , The test program with embedded trap instructions is executed multiple times, the first log, which is the register and memory data log, is collected at the time of software trap by the trap instruction in the execution of the test program, and the register log at the time of hardware trap The first log and the second log collected in the execution of one test program, the first log and the second log collected in the other test program execution. Compared with the log, the software immediately before the log collection location that was inconsistent The process of detecting the instruction sequence from the trap occurrence location to the log collection location where there was a mismatch as a fault occurrence instruction sequence, and the failure source narrowing down section execute the test program multiple times, and at least in the execution of the fault occurrence instruction sequence The first log is collected at one hardware trap, and the first log collected during the execution of a test program matches the first log collected during the execution of another test program. If they match, it is assumed that the instruction sequence behind the matched log collection location is the failure instruction sequence. If there is a mismatch, the command sequence before the matched log collection location is A process for narrowing down the failure source is executed as a failure occurrence instruction sequence.

In addition, the information processing apparatus executes a test program in which a trap instruction is embedded a plurality of times, collects a first log that is a log of register and memory data at the time of software trap by the trap instruction in the execution of the test program, The second log, which is the register log, is collected at the time of the wear trap, and the first log and the second log collected in the execution of one test program and the first log collected in the execution of the other test program. Failure detection by comparing the previous log and the second log and detecting the instruction sequence from the location where the software trap occurred immediately before the location where the mismatched log was collected to the location where the mismatched log was collected as the failure instruction sequence And at least one test program in the execution of the faulty instruction sequence. The first log is collected at the time of the hardware trap, and the first log collected during the execution of one test program matches the first log collected during the execution of another test program. If they match, it is assumed that the instruction sequence behind the matched log collection location is the fault occurrence command sequence. If there is a mismatch, the failure occurs in the instruction sequence before the matched log collection location. And a failure occurrence narrowing unit that narrows down the failure occurrence source as an instruction sequence.

  In testing information processing systems using test instruction sequences, using the features of software traps / hardware traps and full logs / simple logs, and using them properly, it is possible to detect a failure from detecting a failure without changing the test instruction sequence to be executed. It is possible to narrow down the range of the instruction sequence including the instruction that becomes the factor. Since the test instruction sequence to be executed is not changed, it is possible to narrow down the range of the instruction sequence including the instruction that causes the failure in a situation where the hardware state is not substantially different from that at the time of failure detection.

  Hereinafter, the present embodiment will be described with reference to the drawings.

  In this embodiment, the information processing apparatuses such as servers and PCs to be tested have already completed basic operation tests such as function tests and architecture tests, that is, at a level at which ordinary applications can operate. Is the premise. Hereinafter, the information processing apparatus to be tested is referred to as a device under test.

  In this embodiment, a random instruction sequence is used as a test instruction sequence, and a random instruction sequence test program, which is a program for performing a system test using a random instruction sequence, is developed in the memory of the device under test. By testing its own CPU, a logical failure that depends on the timing of its own CPU, a physical failure that depends on a critical path, and the like are detected.

  FIG. 1 is a diagram showing a configuration example of a device under test according to the present embodiment. The device under test 1 includes a random instruction sequence test unit 10. The random instruction sequence test unit 10 is a means for executing a system test using a random instruction sequence for the device under test 1 and is realized by hardware such as a CPU and a memory provided in the computer of the device under test 1 and a software program. Is done. The random instruction sequence test unit 10 includes a random instruction sequence generation unit 11, a failure detection unit 12, a first failure source narrowing unit 13, a second failure source narrowing unit 14, and a log information holding unit 15.

  The random instruction sequence generation unit 11 generates a random instruction sequence used for the random instruction sequence test. A technique for generating a random instruction sequence is a well-known technique, and is described in, for example, Japanese Patent No. 3954248.

  FIG. 2 is a diagram illustrating an example of random instruction sequence generation according to the present embodiment. Hereinafter, an example of generating a random instruction sequence will be described with reference to FIG. In FIG. 2, a seed value table 110, a plurality of test script tables 111, and an instruction conversion table 112 are information prepared in advance.

  In the seed value table 110, seed values for generating random numbers are recorded. The seed value is data of several bytes that is a basis for generating a random instruction sequence. Random data is generated by an algorithm determined based on the seed value, and an instruction is generated according to the instruction generation definition file of the test script table 111. If the seed value and the test script table 111 are determined, the same random instruction sequence can always be generated.

  Each test script table 111 records information such as the frequency of generation of each instruction, the number of instructions generated, and the interval between check points. The test script table 111 is a table in which information for creating a random instruction sequence is stored, and the random instruction sequence generation generator arranges instructions of each category while analyzing the information of the test script table 111. To do. When generating a random instruction sequence, an interrupt is intentionally generated at every fixed instruction step. A point that intentionally causes an interrupt is called a checkpoint, and a trap instruction is used as an instruction that intentionally causes an interrupt.

  In the instruction conversion table 112, correspondence information among instruction identification codes, AND data, and OR data is recorded. An instruction is generated by multiplying AND data / OR data of the instruction conversion table 112 by random data.

  A flow of processing for generating a random instruction sequence will be described. First, one test script table 111 is selected (step (s1)). Random data is generated by a predetermined algorithm using the seed value of the seed value table 110, and the generated random data is written in the test instruction sequence space (step (s2)). The instruction generation pointer is set at the head of the test instruction sequence space (step (s3)).

  Using the 4-byte random data read from the instruction generation pointer as an index, one instruction is extracted according to the instruction generation frequency of the selected test script table 111 (step (s4)).

  AND data / OR data corresponding to the extracted instruction is acquired from the instruction conversion table 112, the 4-byte random data is multiplied with the acquired AND data under the AND condition, and the acquired OR data is acquired under the OR condition. An instruction is generated by multiplication, and the generated instruction is replaced with the 4-byte random data (step (s5)).

  The instruction generation pointer is updated by 4 bytes, and step (s5) is repeated (step (s6)).

  When test instructions are generated for the number of instructions specified by the checkpoint interval in the test script table 111, a trap instruction ("tr" in the instruction in the figure) is unconditionally embedded as the next instruction (step (S7)).

  Thereafter, steps (s4) to (s7) are repeated until the number of instructions generated in the test instruction sequence space reaches the number of instructions generated in the test script table 111.

  A random instruction sequence can be generated by such processing. It should be noted that another random instruction sequence can be generated by updating the seed value in the seed value table 110 or selecting another test script table 111 in step (s1).

  In FIG. 1, a failure detection unit 12 executes a process of collecting a log by executing a random instruction sequence twice, and detects a failure by comparing the collected log information for two times. The failure detection unit 12 includes a log collection unit 120 and a log comparison unit 121.

  The log collecting unit 120 executes a random instruction sequence, collects a log when a trap occurs, and holds the obtained log information in the log information holding unit 15. Hereinafter, the log information collected by the log collecting unit 120 and held in the log information holding unit 15 is referred to as an “expected value log”.

  The log comparison unit 121 executes the same random instruction sequence again after obtaining the expected value log by the log collection unit 120, collects the log when the trap occurs, and the obtained log information is held in the log information holding unit 15 Compare with expected value log. Hereinafter, the log information collected by the log comparison unit 121 is referred to as “result value log”.

  Since the log collection unit 120 and the log comparison unit 121 execute the same random instruction sequence, the expected value log and the result value log obtained should match each other. However, different logs may be collected for the expected value log and the result value log due to some kind of hardware abnormality, such as timing abnormality, data corruption, or a critical path due to high load. The failure detection unit 12 determines that a failure has been detected if there is a trap occurrence point with a different log in the comparison between the expected value log and the result value log.

  Here, an outline of the random instruction sequence test according to the present embodiment will be described. In the random instruction sequence test according to the present embodiment, two types of traps, software traps and hardware traps, are prepared as triggers for collecting logs.

  A software trap is an interrupt intentionally generated by a program. By trapping a trap instruction, which is an instruction for generating a trap unconditionally, in a random instruction sequence at fixed intervals, a trap can be generated reliably. The trap instruction is effective as a check point for specifying whether or not a failure has been detected. In the following, the software trap is called a soft trap.

  A hardware trap is an interrupt that occurs as a result of executing an instruction. Examples of hardware traps include division by zero and floating operations using denormalized numbers. Hardware traps cannot be intentionally generated by a program. Therefore, a hardware trap cannot be generated at an arbitrary location. Hereinafter, the hardware trap is referred to as a hard trap.

  When such a soft trap or hard trap interrupt occurs, the hardware status (status of general-purpose registers, control registers, memory, etc.) is collected. In the random instruction sequence test according to the present embodiment, two types of logs, a full log and a simple log, are prepared as logs to be collected.

  The full log is a log in which the state of the computer hardware is collected in a wide range. For example, all hardware control information and all memory data used in the test are collected. Data collected as a full log includes general-purpose registers, floating registers, control registers (control / status reg + asi register) for all windows, and data for all memory areas to be tested.

  In the full log, all control registers that can be referenced by the program and all memory areas to be tested are collected. If the comparison between the expected value log and the result value log passes the full log comparison, the normality of the test instruction sequence before the trap occurrence point of the full log collection, that is, the test instruction sequence before the trap occurrence point of the full log collection Is guaranteed to work correctly. In other words, when a failure is detected in the full log at a certain trap occurrence point during the execution of a test instruction sequence, the range of influence of the failure instruction sequence is from the trap occurrence point of the full log collection immediately before the trap occurrence point where the failure was detected. , It can be narrowed down to the point where the trap of full log collection where the failure was detected.

  However, since a large amount of data is collected in the full log, the state held in the hardware that cannot be controlled by the program may change. For example, when logging the memory contents, cache rewriting may occur and the hardware state may change. For this reason, in the case where the fault is hidden in the instruction sequence across the trap occurrence point of full log collection, there is a possibility that the fault cannot be detected due to an adverse effect of changing the hardware environment.

  The simple log is a log in which the state of the computer hardware is collected in a narrower range than the full log. For example, only the register data used when a trap occurs is collected. The data collected as a simple log includes data of general-purpose registers and floating registers in the current window being used.

  In the simple log, data collection is limited to the general-purpose registers and floating registers of the current window that was operating when the trap occurred, so that changes in the state held in the hardware are minimized. Can do. Therefore, there is a high possibility that a failure is detected even in the case where the failure is hidden in the instruction sequence across the trap occurrence points of the simple log.

  However, when comparing the expected value log and the result value log, only a part of the hardware control register is compared in the simple log, so if the simple log comparison passes, the test before the trap occurrence point of the simple log collection The normality of the instruction sequence is not guaranteed. In other words, if a failure is detected at a certain trap occurrence point during execution of the test instruction sequence, the affected range of the failure instruction sequence is that the trap occurrence point of simple log collection is just before the trap occurrence point where the failure is detected. Even if there is, it is from the trap occurrence point of the full log immediately before the trap occurrence point where the failure is detected to the trap occurrence point where the failure is detected.

  In this way, at the trap point where a full log is collected, an accurate check is performed for the occurrence of a failure due to the execution of a random instruction sequence up to the trap point. At the trap point where a simple log is collected, the hardware status is changed. There is no minimum failure inspection.

  In the present embodiment, by utilizing these soft trap / hard trap and full log / simple log features, it is possible to detect a failure and narrow down the range of influence of a failure instruction sequence.

  In the random instruction sequence test, in order to verify the normality of the hardware state, in the process of creating a random instruction sequence by the random instruction sequence generation unit 11, the hardware state such as registers and memory called a checkpoint is logged. A mechanism to do this is provided. For the checkpoint, a trap instruction which is an instruction for generating a trap unconditionally is used. When a trap occurs, the hardware state is logged on the first round of execution of the random instruction sequence, and the hardware state is logged on the second round of execution of the random instruction sequence in the same manner as in the first week. The logged result is compared with the log of the second lap as an expected value log.

  In addition to soft traps such as checkpoints, there are cases called hard traps where traps occur as a result of executing instructions (for example, when an operation exception occurs). Even if a hard trap occurs, the hardware status is logged. However, if the log equivalent to the checkpoint is taken for all the hard traps, the pre-action of the μ-archy level of the random instruction is interrupted, and this test aims There is a high possibility that the detection rate of malfunction due to timing deviation at the μ arche level will be lowered. In order to avoid this, the hard trap only logs a minimum register such as a register whose state changes due to the occurrence of the trap.

  As described above, in the random instruction sequence test according to the present embodiment, an effect of increasing the failure detection rate can be obtained by changing the log amounts of the two types of traps of soft trap / hard trap.

  FIG. 3 is a diagram for explaining an example of failure detection according to this embodiment. Hereinafter, an example in which the occurrence of a failure is detected and a failure occurrence instruction sequence that is an instruction sequence that is considered to have occurred will be described with reference to FIG.

  In the random instruction sequence shown in FIG. 3, the trap instruction is an instruction for generating a soft trap serving as a checkpoint. At a checkpoint by a trap instruction, a full log that is a log of data of all registers and all memory under test is collected.

  In the random instruction sequence shown in FIG. 3, the random instruction indicates one instruction in the random instruction string, and particularly indicates an instruction in which a hard trap occurs after execution of the instruction. An instruction that generates a hard trap after execution of the instruction is, for example, an operation instruction, and an instruction that generates an overflow trap as an operation result. When a hard trap occurs, a simple log that is a log of register data related to the hard trap factor is collected.

  In the first week of execution of the random instruction sequence, as shown in FIG. 3, a full log is collected when a soft trap occurs, and a simple log is collected when a hard trap occurs. The collected log information is held in the log information holding unit 15 as an expected value log.

  FIG. 4 is a diagram illustrating an example of the log control table. The log control table 150 illustrated in FIG. 4 is an example of log information held in the log information holding unit 15. The log control table 150 shown in FIG. 4 has information on log number, trap type, log type, log type change, trap address, and compressed log data.

  The log number is a log identification number. Each time a trap occurs and a log is collected, numbers are assigned in order from the first. In the example of the log control table 150 shown in FIG. 4, since the last log number is N, by executing a random instruction sequence for one week, N traps including soft traps and hard traps are combined. Occurs and N logs are collected.

  The trap type is information indicating whether the log is collected when a soft trap occurs or a hard trap occurs. The log type is information indicating whether the log is a full log or a simple log. The log type change is information set when the log type is changed and logs are collected by executing a random instruction sequence. The change of the log type will be described later.

  The trap address is the address of the instruction at which the trap that triggers the collection of the log occurs. In the example of the log control table 150 shown in FIG. 4, the trap addresses (address A), (address B), (address C), (address D), and (address E) are the traps in which the trap occurred in FIG. The addresses of instruction A, random instruction B, random instruction C, random instruction D, and random instruction E are shown.

  The compressed log data is obtained by compressing and storing data collected as a log. Here, the collected data is compressed into an 8-byte checksum and stored. The checksum is a result obtained by dividing and adding the data collected from the register or the memory for each fixed byte (here, 8 bytes). In the example of the log control table 150 shown in FIG. 4, this compressed log data is log information held as an expected value log.

  In FIG. 3, in the second week of execution of the random instruction sequence, as in the first week, a full log is collected when a soft trap occurs, and a simple log is collected when a hard trap occurs. The collected log is compared with the expected value log as a result value log.

  If the hardware operation is normal, the expected value log matches the result value log at each trap occurrence point. If there is a trap occurrence point where the expected value log and the result value log do not match due to some hardware error such as timing error, data corruption, or critical path due to high load, it is determined that a failure has been detected. At this time, an error display indicating the occurrence of a failure may be output.

  At the checkpoint, the results of all registers that can be referenced by software are logged, so if the comparison results at the checkpoint match, it is guaranteed that the processing of the previous instruction sequence is operating normally. The Therefore, the range of instruction sequences that can cause a failure is from the checkpoint immediately before the trap occurrence point where the failure is detected to the instruction at the trap occurrence point where the failure is detected.

  In the example shown in FIG. 3, at the trap occurrence point of the trap instruction A, random instruction B, random instruction C, and random instruction D, the comparison result between the expected value log and the result value log is “OK”. . However, at the trap occurrence point of the random instruction E, the comparison result between the expected value log and the result value log is “NG” indicating a mismatch, and it is determined that a failure is detected here. A failure occurrence instruction sequence, which is an instruction sequence that is considered to include an instruction that causes a failure occurrence, is the occurrence of a trap in which a failure is detected from a checkpoint instruction immediately before the trap occurrence point where the failure is detected, that is, trap instruction A It becomes an instruction sequence up to a point instruction, that is, a random instruction E.

  Note that the instruction at the trap occurrence point for which the correctness is guaranteed by the full log need not be included in the fault occurrence instruction sequence. In the present embodiment, the failure occurrence instruction sequence is an instruction sequence from the instruction at the trap occurrence point immediately before the trap occurrence point where the failure is detected to the instruction at the trap occurrence point where the failure is detected. However, it may be considered that the instruction at the trap generation point where the correctness is guaranteed by the full log at the top of the failure instruction sequence is not the instruction that causes the failure. In this case, it is considered that the instruction may cause a failure from the instruction next to the instruction at the trap generation point where the correctness is guaranteed by the full log at the top of the failure occurrence instruction sequence.

  In FIG. 1, the first failure source narrowing-down unit 13 sequentially changes the type of log collected at a hard trap occurrence point within the range defined as the failure occurrence command sequence by the failure detection unit 12 to a full log, and generates a random command sequence. Is executed to narrow down the range of the faulty instruction sequence obtained by the fault detection unit 12. The same random instruction sequence executed at this time is used without changing the random instruction sequence executed by the failure detection unit 12. The first failure source narrowing-down unit 13 includes a log type changing unit 130, a log collecting unit 131, and a log comparing unit 132.

  The log type changing unit 130 changes the log type collected at the hard trap occurrence point within the range defined as the failure occurrence instruction sequence by the failure detection unit 12 to a full log in a predetermined order. The order of changing to the full log may be any order, such as selecting a higher order or lower order of the hard trap occurrence points in the fault instruction sequence, or a point that is almost in the middle. In the present embodiment, the type of log collected at the hard trap occurrence point is changed using the log type change information in the log control table 150 shown in FIG.

  The log collection unit 131 executes the same random instruction sequence as the random instruction sequence executed by the failure detection unit 12, collects a log when a trap occurs, sets the obtained log information as an expected value log, and uses the log information holding unit 15 Hold on. In the present embodiment, the expected value log is held by updating the compressed log data of the log control table 150 shown in FIG. 4 with the log information collected here.

  After acquiring the expected value log by the log collecting unit 131, the log comparing unit 132 executes the same random instruction sequence again, collects a log when a trap occurs, and uses the obtained log information as a result value log as a log information holding unit. Compared with the expected value log held in FIG.

  If the expected log and the result log match at the hard trap occurrence point when the collected log is changed from the simple log to the full log, the failure instruction sequence after the hard trap occurrence point when the log type is changed to the full log Is narrowed down. If the expected log and result log do not match at the hard trap occurrence point when the collected log is changed from simple log to full log, the failure instruction sequence before the hard trap occurrence point when the log type is changed to full log Is narrowed down. Until the failure instruction sequence becomes an instruction sequence between trap generation points that do not include a hard trap occurrence point in the middle, the log type change, expected value log collection, and comparison between the expected value log and the result value log are repeated, Narrow down the generated instruction sequence.

  FIG. 5 is a diagram illustrating an example of first failure source narrowing according to the present embodiment. Hereinafter, an example of narrowing down the failure instruction sequence shown in FIG. 3 will be described with reference to FIG. The random instruction sequence shown in FIG. 5 is the same as the random instruction sequence shown in FIG. The fault occurrence instruction sequence from the trap instruction A to the random instruction E is obtained by the fault detection process described with reference to FIG.

  In the example of narrowing down the failure source shown in Fig. 5, the log type collected at the hard trap occurrence point within the range of the failure instruction sequence is changed from the simple log to the full log in order from the upper hard trap occurrence point in the failure instruction sequence. Change, execute the random instruction sequence, collect the expected value log and the result value log, compare them, and narrow down the range of the faulty instruction sequence.

  First, the log type change information in the log control table 150 shown in FIG. 4 is updated for the point of the random instruction B, which is the highest hard trap generation point in the range of the failure instruction sequence. Change the type to full log.

  In the third week of execution of the random instruction sequence, as shown in FIG. 5, a full log is collected when a soft trap occurs and when a hard trap due to random instruction B occurs, and a simple log is collected when a hard trap other than random instruction B occurs. . The collected log information is held in the log information holding unit 15 as an expected value log.

  In the fourth week of random instruction execution, as in the third week, a full log is collected when a soft trap occurs and a hard trap due to random instruction B occurs, and a simple log is collected when a hard trap other than random instruction B occurs. . The collected log is compared with the expected value log as a result value log.

  If an error is detected at the position of the random instruction B, the failure instruction sequence can be narrowed down to the random instruction B or earlier, and if no error is detected at the position of the random instruction B, the failure instruction sequence is changed to the random instruction B or later. Can be narrowed down to. In the example shown in FIG. 5, since the comparison result between the expected value log and the result value log is “OK” at the hard trap occurrence point of the random instruction B, no failure is detected at the position of the random instruction B. , The fault occurrence instruction sequence is narrowed down to the instruction sequence from the random instruction B to the random instruction E. When a failure is detected at the position of the random instruction B, the failure instruction sequence is narrowed down to the instruction sequence from the trap instruction A to the random instruction B.

  In the example shown in FIG. 5, when the execution of the random instruction sequence in the fourth week and the narrowing down of the failure instruction sequence are completed, between the random instruction B and the random instruction E that are both ends of the failure instruction sequence, There are still two hard trap generation points, random instruction C and random instruction D. Therefore, the process for narrowing down the scope of the failure instruction sequence is performed again by changing the hard trap occurrence point to be changed to the full log.

  The log type change information of the log control table 150 shown in FIG. 4 for the point of the random instruction C that is the highest hard trap generation point that has not been verified by the full log within the range of the failure instruction sequence. Change the type of log to be collected to full log by updating. At this time, the change to the full log for the random instruction B whose log type was previously changed is canceled.

  In the fifth week of execution of the random instruction sequence, as shown in FIG. 5, a full log is collected when a soft trap occurs and when a hard trap due to random instruction C occurs, and a simple log is collected when a hard trap other than random instruction C occurs. . The collected log information is held in the log information holding unit 15 as an expected value log.

  In the sixth week of execution of the random instruction sequence, as in the fifth week, a full log is collected when a soft trap occurs and a hard trap due to the random instruction C occurs, and a simple log is collected when a hard trap other than the random instruction C occurs. . The collected log is compared with the expected value log as a result value log.

  As shown in FIG. 5, since the comparison result between the expected value log and the result value log is “OK” at the hard trap occurrence point of the random instruction C, no failure is detected at the position of the random instruction C. , The failure occurrence instruction sequence is narrowed down to the instruction sequence from the random instruction C to the random instruction E. When a failure is detected at the position of the random instruction C, the failure instruction sequence is narrowed down to the instruction sequence from the random instruction B to the random instruction C.

In the example shown in FIG. 5, when the execution of the random instruction sequence in the sixth week and the narrowing down of the failure instruction sequence are completed, the random instruction C and the random instruction E, which are both ends of the failure instruction sequence, are still it contains Ha Dotorappu generation point of random instruction D. Therefore, the process for narrowing down the scope of the failure instruction sequence is performed again by changing the hard trap occurrence point to be changed to the full log.

  The log type change information of the log control table 150 shown in FIG. 4 for the point of the random instruction D that is the highest hard trap generation point that has not been verified by the full log within the range of the failure instruction sequence. Change the type of log to be collected to full log by updating. At this time, the change to the full log for the random instruction C whose log type was previously changed is canceled.

  In the seventh week of execution of the random instruction sequence, as shown in FIG. 5, a full log is collected when a soft trap occurs and when a hard trap due to a random instruction D occurs, and a simple log is collected when a hard trap other than the random instruction D occurs. . The collected log information is held in the log information holding unit 15 as an expected value log.

  At the 8th week of execution of the random instruction sequence, as in the 7th week, a full log is collected when a soft trap occurs and a hard trap due to a random instruction D occurs, and a simple log is collected when a hard trap other than the random instruction D occurs. . The collected log is compared with the expected value log as a result value log.

  As shown in FIG. 5, since the comparison result between the expected value log and the result value log is “OK” at the hard trap occurrence point of the random instruction D, no failure is detected at the position of the random instruction D. , The fault occurrence instruction sequence is narrowed down to the instruction sequence from the random instruction D to the random instruction E. When a failure is detected at the position of the random instruction D, the failure instruction sequence is narrowed down to the instruction sequence from the random instruction C to the random instruction D.

  In the example shown in FIG. 5, when the execution of the random instruction sequence in the eighth week and the narrowing down of the failure instruction sequence are completed, between the random instruction D and the random instruction E that are both ends of the failure instruction sequence, Does not include hard trap origin. Therefore, the failure instruction sequence that is the minimum range is finally narrowed down to the instruction sequence from the random instruction D to the random instruction E. At this time, error information indicating that a failure has occurred between the random instruction D and the random instruction E may be output.

  In this way, since there is no hard trap generation point between the trap generation points that are both ends of the failure generation instruction sequence narrowed down by the first failure generation source narrowing unit 13, the first failure generation source narrowing unit In the processing by 13, it is not possible to narrow down the faulty instruction sequence without changing the random instruction sequence. In order to further narrow down the faulty instruction sequence without changing the random instruction sequence, another mechanism must be provided.

  In FIG. 1, the second failure source narrowing unit 14 performs a process of further narrowing down the failure occurrence instruction sequence narrowed down by the first failure source narrowing unit 13.

  A new hardware function called an address fetch trap register 20 is provided in the device under test 1 in order to execute processing by the second failure occurrence source narrowing unit 14. The address fetch trap register 20 is a hardware function that generates an interrupt when the address registered in this register matches the address of the program counter, that is, the address of the instruction to be executed.

  The second failure source narrowing-down unit 14 sequentially sets the addresses of random instructions in the failure-occurring instruction sequence narrowed down by the first failure source narrowing-down unit 13 in the address fetch trap register 20, and selects the random instruction sequence. By executing this, the range of the failure instruction sequence narrowed down by the first failure source narrowing-down unit 13 is further narrowed down. The same random instruction sequence executed at this time is used without changing the random instruction sequence executed by the failure detection unit 12 and the first failure occurrence source narrowing unit 13. When a hard trap occurs due to execution of an instruction at the address set in the address fetch trap register 20, a full log is collected. The second failure source narrowing-down unit 14 includes an address fetch trap register setting unit 140, a log collection unit 141, and a log comparison unit 142.

  The address fetch trap register setting unit 140 sets the addresses of random instructions in the failure instruction sequence narrowed down by the first failure occurrence source narrowing unit 13 in the address fetch trap register 20 in a predetermined order. The order of the addresses set in the address fetch trap register 20 is a predetermined number of addresses from the instruction address at the lower end of the failure instruction sequence in order while skipping a predetermined number of instructions from the instruction address at the upper end of the failure instruction sequence. Any order may be used, such as selecting the addresses of instructions that are intermediate in the faulty instruction sequence in order while skipping instructions one by one. In addition, the number of instructions to be skipped and the number of instructions that are finally used as the range of the instruction sequence causing the failure are also arbitrary numbers of 1 or more, respectively.

  The log collection unit 141 executes the same random instruction sequence as that executed by the failure detection unit 12 or the first failure source narrowing unit 13, collects a log when a trap occurs, and obtains the obtained log information. The expected value log is held in the log information holding unit 15.

  The log comparison unit 142, after obtaining the expected value log by the log collection unit 141, executes the same random instruction sequence again, collects the log when the trap occurs, and uses the obtained log information as a result value log as a log information holding unit Compared with the expected value log held in FIG.

  When the expected value log and the result value log match at the hard trap occurrence point by the address fetch trap register 20, the failure instruction sequence is narrowed down after the hard trap occurrence point by the address fetch trap register 20. If the expected value log and the result value log do not match at the hard trap occurrence point by the address fetch trap register 20, the failure instruction sequence is narrowed down before the hard trap occurrence point by the address fetch trap register 20. Until the range of the failure instruction sequence is equal to or less than the predetermined number of instructions, the setting / updating of the address fetch trap register 20, the collection of the expected value log, and the comparison between the expected value log and the result value log are repeated, Narrow down.

  FIG. 6 is a diagram illustrating an example of second failure source narrowing according to the present embodiment. Hereinafter, an example of further narrowing down the fault occurrence instruction sequence finally narrowed down in the example of FIG. 5 will be described with reference to FIG. The random instruction sequence shown in FIG. 6 is the same as the random instruction sequence shown in FIG. 5. In particular, the range from the random instruction D to the random instruction E finally narrowed down as the failure instruction sequence in FIG. It is shown.

  In the example of narrowing down the failure occurrence source shown in FIG. 6, the addresses of random instructions within the range of the failure occurrence instruction sequence are set in the address fetch trap register 20 in order from the top while skipping by a predetermined number of instruction units, and the random instruction sequence is set. Execute to collect the expected value log and result value log, compare them, and narrow down the range of the instruction sequence where the error occurred.

  First, by setting in the address fetch trap register 20 the address of a random instruction X that is a predetermined number of instructions ahead of the random instruction D, which is the highest instruction in the range of the failure instruction sequence, a hard trap is executed when the random instruction X is executed. And collect the full log. In FIG. 6, (address X) set in the address fetch register 20 indicates the address of the random instruction X.

  In the ninth week of execution of the random instruction sequence, as shown in FIG. 6, a full log is collected when a soft trap occurs and when a hard trap is generated by the address fetch trap register 20, that is, when a random instruction X is executed. A simple log is collected when a hard trap occurs except when a hard trap occurs due to. The collected log information is held in the log information holding unit 15 as an expected value log.

  In the 10th week of execution of the random instruction sequence, as in the 9th week, a full log is collected when a soft trap occurs and when a hard trap is generated by the address fetch trap register 20, that is, when a random instruction X is executed, and the address fetch trap register 20 A simple log is collected when a hard trap occurs except when a hard trap occurs due to. The collected log is compared with the expected value log as a result value log.

  If an error is detected at the position of the random instruction X, the failure instruction sequence can be narrowed down to the random instruction X or earlier, and if no error is detected at the position of the random instruction X, the failure instruction sequence is placed after the random instruction X. Can be narrowed down to. In the example shown in FIG. 6, since the comparison result between the expected value log and the result value log is “OK” at the hard trap occurrence point of the random instruction X, no failure is detected at the position of the random instruction X. , The failure occurrence instruction sequence is narrowed down to the instruction sequence from the random instruction X to the random instruction E. When a failure is detected at the position of the random instruction X, the failure instruction sequence is narrowed down to the instruction sequence from the random instruction D to the random instruction X.

  In the example illustrated in FIG. 6, it is assumed that the failure instruction sequence range has not yet reached the predetermined number of instructions when the execution of the random instruction sequence in the 10th week and the narrowing down of the failure instruction sequence are completed. Therefore, the address of the random instruction set in the address fetch trap register 20 is changed, and processing for narrowing down the range of the faulty instruction sequence is performed again.

  When the random instruction Y is executed by updating the set address of the address fetch trap register 20 with the address of the random instruction Y advanced by a predetermined number of instructions from the random instruction X which is the highest order instruction within the range of the failure instruction sequence Generate a trap and collect a full log. In FIG. 6, (address Y) set in the address fetch register 20 indicates the address of the random instruction Y.

  In the eleventh week of execution of the random instruction sequence, as shown in FIG. 6, a full log is collected when a soft trap occurs and when a hard trap occurs by the address fetch trap register 20, that is, when a random instruction Y is executed. A simple log is collected when a hard trap occurs except when a hard trap occurs due to. The collected log information is held in the log information holding unit 15 as an expected value log.

  In the 12th week of execution of the random instruction sequence, as in the 11th week, a full log is collected when a soft trap occurs and when a hard trap is generated by the address fetch trap register 20, that is, when a random instruction Y is executed, and the address fetch trap register 20 A simple log is collected when a hard trap occurs except when a hard trap occurs due to. The collected log is compared with the expected value log as a result value log.

  In the example shown in FIG. 6, since the comparison result between the expected value log and the result value log is “OK” at the hard trap occurrence point of the random instruction Y, no failure is detected at the position of the random instruction Y. , The failure occurrence instruction sequence is narrowed down to the instruction sequence from the random instruction Y to the random instruction E. When a failure is detected at the position of the random instruction Y, the failure instruction sequence is narrowed down to the instruction sequence from the random instruction X to the random instruction Y.

  In the example illustrated in FIG. 6, it is assumed that the failure instruction sequence range has not yet reached the predetermined number of instructions when the random instruction sequence and the failure instruction sequence narrowing down in the 12th week are completed. Therefore, the address of the random instruction set in the address fetch trap register 20 is changed, and processing for narrowing down the range of the faulty instruction sequence is performed again.

  By updating the set address of the address fetch trap register 20 with the address of the random instruction Z that is a predetermined number of instructions ahead of the random instruction Y, which is the highest order instruction in the range of the fault occurrence instruction sequence, Generate a trap and collect a full log. In FIG. 6, (address Z) set in the address fetch register 20 indicates the address of the random instruction Z.

  At the 13th week of execution of the random instruction sequence, as shown in FIG. 6, when a soft trap occurs and when a hard trap is generated by the address fetch trap register 20, that is, when a random instruction Z is executed, a full log is collected and the address fetch trap register 20 A simple log is collected when a hard trap occurs except when a hard trap occurs due to. The collected log information is held in the log information holding unit 15 as an expected value log.

  In the 14th week of execution of the random instruction sequence, as in the 13th week, a full log is collected when a soft trap occurs and when a hard trap is generated by the address fetch trap register 20, that is, when a random instruction Z is executed, and the address fetch trap register 20 A simple log is collected when a hard trap occurs except when a hard trap occurs due to. The collected log is compared with the expected value log as a result value log.

  In the example shown in FIG. 6, since the comparison result between the expected value log and the result value log is “NG” at the hard trap occurrence point of the random instruction Z, a failure is detected at the position of the random instruction Z. The failure occurrence instruction sequence is narrowed down to the instruction sequence from the random instruction Y to the random instruction Z. If a failure is detected at the position of the random instruction Z, the failure instruction sequence is narrowed down to the instruction sequence from the random instruction Z to the random instruction E.

  In the example illustrated in FIG. 6, it is assumed that the range of the failure instruction sequence is equal to or less than the predetermined number of instructions when the execution of the random instruction sequence and narrowing down of the failure instruction sequence in the 14th week are completed. Therefore, the failure instruction sequence that is the minimum range is finally narrowed down to the instruction sequence from the random instruction Y to the random instruction Z. At this time, error information indicating that a failure has occurred between the random instruction Y and the random instruction Z may be output.

  In this way, by using the address fetch trap register 20, the range of the fault instruction sequence can be narrowed down to an arbitrary number of instructions. If the predetermined number of instructions is 1, it is possible to narrow down the range of the failure instruction sequence to one instruction.

  Hereinafter, an example of the flow of processing of the random instruction sequence test according to the present embodiment will be described using a flowchart. In addition, the example of a process demonstrated below is an example of the process along the flow of the procedure demonstrated in FIG.3, FIG.5, FIG.6 etc. FIG.

  FIG. 7 is a failure detection processing flowchart according to the present embodiment. The initial value of the seed value set in the seed value table 110 is selected as the seed value, and one test script table 111 is selected (step S10).

  A random instruction sequence is generated from the combination of the seed value and the test script table 111 by a predetermined algorithm (step S11).

  The generated random instruction sequence is executed, a log is collected when a trap occurs, and the collected log information is held as an expected value log (step S12). At this time, a full log is collected when a soft trap is generated by a trap instruction, and a simple log is collected when a hard trap occurs. For example, when a hard trap occurs, a simple log is collected, compressed with a checksum and stored in the log control table 150 as shown in FIG. 4, and when a soft trap occurs, a full log is collected and compressed with a checksum. Stored in the log control table 150 as shown in FIG. The same random instruction sequence is executed again, a log is collected when a trap occurs, and the collected log information is compared with an expected value log held as a result value log (step S13).

  If an error is detected by comparing the expected value log and the result value log (step S14), the error information is held (step S15), and the process proceeds to the first failure source narrowing process. Here, the expected value log and the result value log are compared for each trap occurrence point, and it is determined that an error has been detected when there is a trap occurrence point whose logs do not match. At this time, error information such as a failure instruction sequence that is an instruction sequence including an instruction that causes a failure is stored. The fault occurrence instruction sequence at this point is an instruction sequence from the soft trap occurrence point immediately before the trap occurrence point where the error is detected to the trap occurrence point where the error is detected. The first failure source narrowing process will be described later with reference to FIG.

  If no error is detected (step S14), the test script table and the seed value are updated (step S10, step S17), and the test is completed for the specified M times (step S16) and all the test script tables 111 with different seed values. Until (step S18), a test using a random instruction sequence is performed. The seed value is updated by incrementing the current seed value, for example.

  By the failure detection process shown in FIG. 7, a failure instruction sequence from the soft trap occurrence point immediately before the trap occurrence point where the error is detected to the trap occurrence point where the error is detected is obtained.

  FIG. 8 is a flowchart of a first failure source narrowing-down process according to this embodiment. If the full log is collected at the trap occurrence point immediately before the trap occurrence point where the error is detected (step S20), the process proceeds to the second failure occurrence source narrowing process. If the full log is collected at the trap occurrence point immediately before the trap occurrence point where the error was detected, the failure instruction sequence is changed to an instruction sequence between two trap occurrence points that do not include the trap occurrence point in between. Since the state has been narrowed down, no further failure instruction sequence can be narrowed down in the first failure source narrowing process. The second failure source narrowing process will be described later with reference to FIG.

  The log type of the trap occurrence point of the youngest address in the failure occurrence instruction sequence is changed to a full log (step S21). If a hard trap occurrence point is included between the trap occurrence points at both ends of the fault occurrence instruction sequence, the fault occurrence instruction sequence can still be narrowed down. Change the type of log collected at the hard trap occurrence point of address No. to full log. For example, in the log control table 150 shown in FIG. 4, the log type change information of the hard trap occurrence point of the youngest address in the failure instruction sequence is made a full log.

  The random instruction sequence executed in the failure detection process is executed again, a log is collected when a trap occurs, and the collected log information is held as an expected value log (step S22). At this time, a full log is collected when a soft trap occurs and when a hard trap changed to full log collection occurs, and a simple log is collected when any other hard trap occurs. The collected log information is stored in a log control table 150 as shown in FIG. 4, for example. The same random instruction sequence is executed again, a log is collected when a trap occurs, and the collected log information is compared with an expected value log held as a result value log (step S23).

  If an error is detected at the hard trap occurrence point changed to full log collection by comparing the expected value log with the result value log (step S24), the error information is updated (step S25), and the second failure source Proceed to the narrowing process. Since the hard trap occurrence point changed to full log collection is the hard trap occurrence point of the lowest address in the failure instruction sequence, if an error is detected here, the updated failure occurrence sequence is In this state, the instruction sequence between two trap generation points that do not include the trap generation point is narrowed down, and no further failure instruction sequence can be narrowed down in the first failure source narrowing process. The failure instruction sequence updated at this time is from the trap occurrence point instruction at the top of the failure occurrence instruction sequence to the hard trap occurrence point instruction changed to full log collection.

  If an error is not detected at the hard trap occurrence point changed to full log collection by comparing the expected value log and the result value log (step S24), and an error is detected at the last trap occurrence point of the failure instruction sequence (Step S26), the error information is updated (Step S27), and the process returns to Step 20. The fault occurrence instruction sequence updated at this time is from the instruction at the hard trap occurrence point changed to full log collection to the instruction at the last trap occurrence point of the fault occurrence instruction series in which an error is detected.

  When no error is detected at the hard trap occurrence point changed to the full log collection or the last trap occurrence point of the failure instruction sequence by comparing the expected value log and the result value log (step S24, step S26), The previous error information is displayed (step S28), and the process is terminated. In the process of narrowing down the faulty instruction sequence, if a change in the state held in the hardware between the execution of two random instruction sequences is no longer detected, the minimum range of faults occurs at that time Output instruction sequence as error information.

  The first failure source narrowing process shown in FIG. 8 does not change the random instruction sequence to be executed, but the failure instruction sequence is in the minimum range between two trap generation points that do not include a trap generation point in between. Narrow down to instruction sequence.

  FIG. 9 is a flowchart of a second failure source narrowing-down process according to this embodiment. The address of the instruction in the failure instruction sequence is set in the address fetch trap register 20 (step S30). The address set here is the address of a random instruction that is a predetermined number of instructions ahead of the instruction at the trap occurrence point, which is the highest order in the failure instruction sequence.

  The random instruction sequence executed in the failure detection process and the first failure source narrowing process is executed again, a log is collected when a trap occurs, and the collected log information is held as an expected value log (step S31). At this time, a full log is collected when a soft trap occurs and when a hard trap is generated by the address fetch trap register 20, and a simple log is collected when any other hard trap occurs. The same random instruction sequence is executed again, a log is collected when a trap occurs, and the collected log information is compared with an expected value log held as a result value log (step S32).

  If an error is detected at the hard trap occurrence point by the address fetch trap register 20 by comparing the expected value log and the result value log (step S33), the error information is updated (step S34), and the error information is displayed (step S34). Step S35). Since the hard trap occurrence point by the address fetch trap register 20 is the address of a random instruction that is a predetermined number of instructions ahead of the highest instruction in the failure instruction sequence, if an error is detected here, the updated failure occurrence Since the instruction sequence falls within the predetermined number of instructions, the updated failure instruction sequence is output as error information. The updated failure instruction sequence is from the highest order instruction of the immediately preceding failure occurrence instruction sequence to the instruction at the hard trap occurrence point by the address fetch trap register 20.

  When an error is not detected at the hard trap occurrence point by the address fetch trap register 20 by comparison between the expected value log and the result value log (step S33), but an error is detected at the last trap occurrence point of the failure instruction sequence (Step S36), the error information is updated (Step S37). The fault occurrence instruction sequence updated at this time is from the instruction at the hard trap occurrence point by the address fetch trap register 20 to the instruction at the last trap occurrence point of the fault occurrence instruction series in which the error is detected.

  If the failure instruction sequence updated in the process of step S37 is not within the predetermined number of instructions (step S38), the set address of the address fetch trap register 20 is updated (step S39), and the process returns to the process of step S31. . Here, the set address of the address fetch trap register 20 is updated to the address of a random instruction advanced by a predetermined number of instructions from the instruction of the address set immediately before.

  If the fault occurrence instruction sequence updated in the process of step S37 is within the predetermined number of instructions (step S38), error information is displayed (step S40). Here, the fault occurrence instruction sequence updated in the process of step S37 is output as error information.

  When an error is not detected at the hard trap occurrence point by the address fetch trap register 20 or at the last trap occurrence point of the failure instruction sequence by comparing the expected value log and the result value log (step S33, step S36), The previous error information is displayed (step S41), and the process is terminated. In the process of narrowing down the faulty instruction sequence, if a change in the state held in the hardware between the execution of two random instruction sequences is no longer detected, the minimum range of faults occurs at that time Output instruction sequence as error information.

  By the second failure source narrowing process shown in FIG. 9, the failure instruction sequence is narrowed down to a predetermined number of instructions as a minimum range without changing the executed random instruction sequence.

  FIG. 10 is a diagram for explaining an example of a random instruction sequence test according to this embodiment. Here, the random instruction sequence test according to the present embodiment will be described using a specific example of a random instruction sequence. In FIG. 10, (1) and (7) are soft trap occurrence points due to a trap instruction, and (2) to (6) are hard trap occurrence points.

  When the random instruction sequence shown in FIG. 10 is executed, the register (% i7) stored by the random instruction (★) is stored before being determined by the random instruction (a), and the data is garbled. Assume the case. However, it is assumed that the operation is correct in the first round of execution of the random instruction sequence, this phenomenon occurs in the second execution of the random instruction sequence, and an error is detected in the trap instruction of (7).

  First, since an error is detected in the trap instruction (7) by the fault detection process, the range of the fault instruction sequence is the soft trap generation point immediately before the trap instruction (7) where the error is detected (1). ) From the trap instruction to the trap instruction (7) in which an error is detected.

  Next, a first failure source narrowing process is performed to narrow down the failure occurrence instruction sequence to an instruction sequence between two trap occurrence points that do not include a trap occurrence point in between.

  The log type collected at the hard trap occurrence point in (2) is changed from the simple log to the full log, and the random instruction sequence is executed twice and the log information is compared. As a result of the log information comparison, an error is detected at the soft trap occurrence point (7). The range of the fault occurrence instruction sequence is an instruction sequence from the random instruction (2) to the trap instruction (7).

  The log type collected at the hard trap occurrence point in (2) is changed from the full log to the simple log, the log type collected at the hard trap occurrence point in (3) is changed from the simple log to the full log, and the random instruction string is set to 2. Lap and compare log information. As a result of the log information comparison, an error is detected at the soft trap occurrence point (7). The range of the fault occurrence instruction sequence is an instruction sequence from the random instruction (3) to the trap instruction (7).

  The log type collected at the hard trap occurrence point in (3) is changed from the full log to the simple log, the log type collected at the hard trap occurrence point in (4) is changed from the simple log to the full log, and the random instruction string is set to 2. Lap and compare log information. As a result of the log information comparison, an error is detected at the hard trap occurrence point (4). The range of the fault occurrence instruction sequence is an instruction sequence from the random instruction (3) to the random instruction (4).

  At this time, since the range of the fault instruction sequence is narrowed down to the instruction sequence from the hard trap generation point (3) to the hard trap generation point (4) that does not include a trap generation point in between, the first The process of narrowing down the failure source is terminated.

  Next, a second failure source narrowing process is performed in order to narrow down the failure occurrence instruction sequence within a predetermined number of instructions. Here, it is assumed that the predetermined number of instructions is three.

  In the address fetch trap register 20, the address of a random instruction that is advanced by three instructions from the random instruction of (3) is set, and the random instruction sequence is executed twice and the log information is compared. As a result of the log information comparison, an error is detected at the hard trap occurrence point (4). The range of the failure instruction sequence is an instruction sequence from a random instruction advanced by 3 instructions from the random instruction of (3) to a random instruction of (4).

  The set address of the address fetch trap register 20 is updated to the address of the random instruction that is further advanced by 3 instructions from the random instruction of the address set in the previous address fetch trap register 20, that is, the address of the random instruction that is advanced by 6 instructions from the random instruction of (3) Then, the random instruction sequence is executed twice and the log information is compared. As a result of the log information comparison, an error is detected at the hard trap occurrence point of the set address of the address fetch trap register 20. The range of the fault occurrence instruction sequence is an instruction sequence from a random instruction advanced by 3 instructions from the random instruction of (3) to a random instruction advanced by 6 instructions from the random instruction of (3).

  At this time, since the range of the failure instruction sequence is narrowed down to a predetermined number of instructions, that is, a range of 3 instructions, the second failure occurrence source narrowing process is terminated.

  In the example shown in FIG. 10, the failure instruction sequence from the random instruction advanced by 3 instructions from the random instruction of (3) to the random instruction advanced by 6 instructions from the random instruction of (3) is output as error information of the final result. The

  The processing by the random instruction sequence test unit 10 described above can be realized by a computer and a software program, and the program can be recorded on a computer-readable recording medium or provided through a network.

  Although the embodiment of the present invention has been described above, the present invention is not limited to this embodiment.

For example, in the embodiment described above, although collected only data register of the current window by a simple log, data of the register window other than the control register and current window also may be collected. However, collecting memory data like a full log increases the possibility of changing the hardware status, so it is better not to collect memory data.

  Further, for example, in the above-described embodiment, in order to detect a failure occurrence and narrow down a failure occurrence instruction sequence, the log information collected by executing the test instruction sequence twice is compared. Log information may be collected by executing test instruction sequences two or more times, and the log information may be compared.

It is a figure which shows the structural example of the to-be-tested apparatus by this Embodiment. It is a figure explaining the example of the random command sequence generation by this Embodiment. It is a figure explaining the example of the failure detection by this Embodiment. It is a figure which shows the example of a log control table. It is a figure explaining the example of the 1st failure generation source narrowing down by this Embodiment. It is a figure explaining the example of the 2nd failure origin narrowing down by this Embodiment. It is a failure detection process flowchart by this Embodiment. It is a 1st failure occurrence source narrowing-down process flowchart by this Embodiment. It is a 2nd failure generation source narrowing-down process flowchart by this Embodiment. It is a figure explaining the example of the random instruction sequence test by this Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Device under test 10 Random command sequence test unit 11 Random command sequence generation unit 12 Fault detection unit 120 Log collection unit 121 Log comparison unit 13 First failure source narrowing unit 130 Log type change unit 131 Log collection unit 132 Log comparison unit 14 Second failure source narrowing-down unit 140 Address fetch trap register setting unit 141 Log collection unit 142 Log comparison unit 20 Address fetch trap register

Claims (5)

A computer test method performed by an information processing apparatus including a failure detection unit that detects a failure by executing a test program and a failure source narrowing-down unit that narrows down a failure location of the test program in which the failure is detected,
The failure detection unit executes a test program in which a trap instruction is embedded a plurality of times, and collects a first log that is a log of register and memory data at the time of software trap by the trap instruction in the execution of the test program, At the time of hardware trap, the second log, which is the register log, is collected. The first and second logs collected during the execution of one test program and the second log collected during the execution of another test program are collected. The process of comparing the first log and the second log and detecting the sequence of instructions from the location where the software trap occurred immediately before the location where the mismatched log was collected to the location where the mismatched log was collected as the failure sequence When,
The failure source narrowing down section executes the test program a plurality of times, collects the first log at the time of at least one hardware trap in the execution of the failure occurrence instruction sequence, The collected first log is compared with the first log collected in another test program execution to determine whether it matches or does not match. If the instruction sequence is a failure instruction sequence, and there is a mismatch, there is a process of narrowing down the failure source by assuming that the instruction sequence before the matched log collection location is the failure instruction sequence
A computer test method. The information processing apparatus further includes a second failure source narrowing-down unit,
The second failure source narrowing-down unit sets the address of any instruction in the failure instruction sequence in the hardware function unit that generates a hardware trap when the instruction at the set address is executed, and the test The program is executed a plurality of times, the first log is collected at the time of hardware trap by the hardware function unit in the execution of the fault occurrence instruction sequence, and the first log collected in the execution of the test program of a certain time , Compare whether the first log collected in the execution of the test program of the other times matches or does not match, and if they match, the instruction sequence behind the matched log collection location is the fault instruction sequence If there is a mismatch, the process of narrowing down the failure source by assuming that the instruction sequence before the matching log collection location is the failure occurrence instruction sequence With
The computer test method according to claim 1. The first log is a log of all registers that can be referred to and data in the memory area to be tested,
The second log is a log of register data in the current window
The computer test method according to claim 1, wherein the computer test method is a computer test method. An information processing apparatus including a failure detection unit that detects a failure by executing a test program, and a failure source narrowing-down unit that narrows down the failure location of the test program in which the failure is detected.
The failure detection unit executes a test program in which a trap instruction is embedded a plurality of times, and collects a first log that is a log of register and memory data at the time of software trap by the trap instruction in the execution of the test program, At the time of hardware trap, the second log, which is the register log, is collected. The first and second logs collected during the execution of one test program and the second log collected during the execution of another test program are collected. Processing that compares the first log and the second log and detects the sequence of instructions from the location where the software trap occurred immediately before the location where the mismatched log was collected to the location where the mismatched log was collected as the faulted sequence When,
The failure source narrowing down section executes the test program a plurality of times, collects the first log at the time of at least one hardware trap in the execution of the failure occurrence instruction sequence, The collected first log is compared with the first log collected in another test program execution to determine whether it matches or does not match. If the instruction sequence is a failure instruction sequence, and if there is a mismatch, the processing that narrows down the failure source by assuming that the instruction sequence before the matching log collection location is the failure instruction sequence
Computer test program for execution. A test program in which a trap instruction is embedded is executed a plurality of times, and a first log that is a log of register and memory data is collected at the time of software trap by the trap instruction in the execution of the test program. The second log, which is a log, is collected, and the first log and the second log collected in one execution of the test program, and the first log and the second log collected in another execution of the test program A fault detection unit that detects a sequence of instructions from the location where the software trap occurred immediately before the location where the mismatched log was collected to the location where the mismatch was collected as a faulty command sequence.
The test program is executed a plurality of times, the first log is collected at the time of at least one hardware trap in the execution of the fault occurrence instruction sequence, and the first log collected in a certain test program execution , Compare whether the first log collected in the execution of the test program of the other times matches or does not match, and if they match, the instruction sequence behind the matched log collection location is the fault instruction sequence And a failure occurrence narrowing unit that narrows down the failure source as the instruction sequence before the matched log collection location is a failure occurrence instruction sequence.
An information processing apparatus characterized by that.

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