JPS63163639A - Two-input contending circuit - Google Patents

Abstract

PURPOSE:To generate a clear pulse which is inputted to the clear terminals of a D flip-flop (DFF) and resets it surely, by connecting the negative output terminal of a first DFF to the clear terminal of a second DFF, and connecting the negative output terminal of the second DFF to the clear terminal of the first DFF. CONSTITUTION:In the titled circuit, the DFF 2 to which a clock signal is inputted, the DFF 1 to which the clock signal with a phase opposite to that of the DFF 2 is inputted via an inverter 3, and a NAND circuit are provided. For the reason, by inputting signals A and B to input terminals D1 and D2 respectively, it is possible to generate the clear pulse having the same width as that of the clock signal between output signals. Therefore, it is possible to generate the clear pulse with wide width by expanding the width of the lock signal, and to reset the DFF connected to a rear stage surely, and also, a whole circuit can be made into an integrated circuit, and simple circuit constitution can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-person membrane combination circuit used in computer input devices and the like.

Conventional technology A two-man power membrane combination circuit has two input terminals, and if a signal is input to one of them while the other input terminal is being input, the input terminal to which the signal was input first will be used. OV (hereinafter referred to as
It is configured to output a signal (referred to as L level).

FIG. 3 is a circuit diagram showing an example of a conventional two-person combined circuit. In FIG. 3, 5, 6, and 7 are NAND circuits, and an input terminal 5a of the NAND circuit 5 and an input terminal 6b of the NAND circuit 6 receive external signals.

The output terminal 5c of the NAND circuit 5 is connected to the input terminal 7a of the NAND circuit 7 and the output terminal 6a of the NAND circuit 6.
An output terminal 6c of the AND circuit 6 is connected to an input terminal 5b of the NAND circuit 5 and an input terminal 7b of the NAND circuit 7.

The operation of the conventional two-person membrane combination circuit configured as described above will be described below.

FIG. 4 is a timing chart of a conventional two-person capacity combining circuit.

At this point in time, no signals are input to the input terminals 5a and 6b, so signals are output from the output terminals 5c and 6c as shown in Fig. 4 (C
) and (D), a signal of +5V (hereinafter referred to as H level) is output, and the output terminal 7c outputs a signal of L level as shown in FIG. 4(E).

At time point A, a signal is input to the input terminal 6b as shown in FIG. 4(B), and the signal output from the output terminal 6c is
The signal that changes to the L level as shown in Figure (D) and is output from the output terminal 5c does not change as shown in Figure 4 (C), and the signal that is output from the output terminal 7c changes to the L level as shown in Figure 4 (E). ), it changes to H level.

At time point 1, a signal is input to the input terminal 5a as shown in FIG. 4(A), and the signals output from the output terminals 5c and 6c are at H level as shown in FIG. 4(C) and (D), respectively. , the signal output from the output terminal 7c remains at L level and does not change as shown in FIG. 4(E).

The time axis will be expanded and explained between time, o, force, and ki.

During the initial construction, the signal input to the input terminal 6b is as shown in Fig. 4 (B
), it changes to L level. Generally NANDA
Since it takes some time from when the ND circuit code is input to when the signal is output, the signal output from the output terminal 6c at time O changes to H level as shown in Fig. 4(D), and the H level The signal is input to the input terminal 5b. Then, the signal output from the output terminal 5c at the moment of force is as shown in Fig. 4 (
It changes to L level as shown in C). Moreover, between the time point O and the time point power, the signals output from the output terminals 5c and 6c are both at H level as shown in FIG. The output signal changes to L level as shown in FIG. 4(E),
The signal output from the output terminal 7c at the time point K is shown in Fig. 4 (E
), it changes to H level.

At this point, the signal input to the input terminal 5a is as shown in Fig. 4 (A
), the signal output from the output terminal 5c changes to the H level as shown in FIG. 4(C), and the signal output from the output terminal 7c changes to the L level as shown in FIG. )
It changes to L level as shown in .

As described above, in the conventional two-person power combining circuit, when the signals shown in Fig. 4 (A) and (B) are input to the two input terminals, that is, the signal is input to one input terminal. When a signal is input to the other input terminal in the middle, there is a connection between the output signals so that when the signal to the input signal to which the signal was input first disappears, you can see that two signals have been input. It is possible to output an L level signal.

A D flip-flop (hereinafter abbreviated as DFF) is often connected to such a conventional two-man power combination circuit.

FIG. 5 is a circuit diagram when a DFF is connected to a conventional two-person power combination circuit. In Figure 5, 20 is DFF, D20
is an input terminal, CK2O is a clock terminal to which a clock signal is input, Q20 is an output terminal, and CLR20 is a clear terminal, which resets the DFF 20 when an L level signal is input.

The conventional two-person capacity combining circuit has two input terminals as shown in Figure 4 (A).
, when a signal like (B) is input +: NA
By taking advantage of the fact that there is a slight delay between the input of a signal to the ND circuit and the output of the signal, an L level signal (hereinafter referred to as a clear pulse) is output between the output signals. Because the width of the clear pulse was very small, D
Even if input to clear terminal CLR20 of FF20, DFF
There were times when I reset the contents of 20 and times when I didn't.

Another conventional two-person capacity combining circuit that solves the above-mentioned problems will be described below.

FIG. 6 is a circuit diagram of another conventional two-person power combining circuit. In Fig. 6, 8 is an AND circuit, and 9, 10, and 11 are falling differentiators that output a downward pulse signal when the input signal changes from H level to L level. always outputs an H level signal. Input terminals 8a, 8b of AND circuit 8
An external signal is input to the input terminal 9b of the NAND circuit 9 and the input terminal 10b of the NAND circuit 10. AN
The output terminal 8C of the D circuit 8 is connected to the input terminal 12a of the falling differentiator 12. The output terminal 12b of the falling differentiator 12 is the input terminal 9a of the NAND circuits 9 and 10.
, 10c. The output terminal 9d of the NAND circuit 9 is connected to the input terminal 11a of the NAND circuit 11.
It is connected to the input terminal 10a of the ND circuit 10. NA
An output terminal 10d of the ND circuit 10 is connected to an input terminal 11b of the NAND circuit 11 and an input terminal 9c of the NAND circuit 9.

The operation of this circuit will be explained below.

FIG. 7 is a timing chart showing the operation.

At this point in time, no signal is input to the input terminals 9b, 8a, 10b, 8b, so an H level signal is output from the output terminal 12b as shown in FIG. The output signals are shown in Figure 7 (D), (
As shown in FIG. 7(F), both signals are at H level, and the signals outputted from the output terminal 11C are at L level as shown in FIG. 7(F).

At time point A, signals are input to the input terminals 9b and 8a as shown in FIG. 7(A), and the signal output from the output terminal 9d changes to L level as shown in FIG. The signal output from the terminal 11c changes to H level as shown in FIG. 7(F).

At point 1, signals are input to the input terminals 10b and 8b as shown in FIG. 7(B), and the signal output from the output terminal 12b remains at the H level as shown in FIG. 7(C). The signal output from terminal 9d also remains at L level as shown in Figure 7(D), and the signal output from output terminal 10d also remains at H level as shown in Figure 7(E), so the output The signal output from the terminal 11c remains at the H level as shown in FIG. 7(F).

In the instant construction, the signals input to the input terminals 9b and 8a are the seventh
As shown in FIG. 7(A), the signal input to the input terminal 12a changes from the H level to the L level, and the signal output from the output terminal 12b changes from the H level to the L level as shown in FIG.
), the signal output from the output terminal 9d changes to the H level as shown in FIG. 7(D), and the signal output from the output terminal 10d changes to the L level as shown in FIG.
), the output terminal 1 remains at H level.
The signal output from 1d is L as shown in Figure 7 (F).
Change in level.

When the signal output from the output terminal 12b changes to the H level as shown in FIG. 7(C) at time O, the signal output from the output terminal 9d remains at the H level as shown in FIG. 7<D). However, the signal output from the output terminal 10d is as shown in Fig. 7 (
As shown in FIG. 7(F), the signal changes to L level, and the signal output from the output terminal 11c changes to H level as shown in FIG. 7(F).

At the moment of input, the signals input to the input terminals 8b and 10b finish inputting as shown in FIG. 7(B), so the output terminal 1
The signal output from 2b is H as shown in Figure 7(C).
The signal output from the output terminal 9d remains at the H level as shown in FIG. 7(D), and the signal output from the output terminal 10d remains at the H level as shown in FIG. 7(E). The signal changes to H level and output from output terminal 11c changes to L level as shown in FIG. 7(F).

The conventional two-person membrane combination circuit shown in FIG. 6 also has two input terminals as shown in FIG.
) and (B), a clear pulse can be generated between the output signals so that it can be seen that two signals have been input to the output signal.

Problems to be Solved by the Invention However, in the conventional configuration described above, the width of the clear pulse is variable by changing the time constant of the falling differentiator. The circuit configuration was complicated.

The present invention solves the above-mentioned conventional problems.The width of the clear pulse can be made the same as the width of the clock signal, and the clear pulse can be input to the clear terminal of the DFF to reliably reset the DFF. It is an object of the present invention to provide a two-person competitive circuit that can generate pulses and has a simple circuit configuration.

Means for Solving the Problems To achieve this objective, the two-person competition circuit of the present invention is
a first DFF to which a clock signal is input; and a first DF.
A second DFF to which a clock signal having an opposite phase to the clock signal input to F is input, and a logic circuit that takes the logical sum of the positive signals output from the first and second DFF. Connect the negative output terminal of the DFF to the clear terminal of the second DFF, and connect the negative output terminal of the second DFF to the first DFF.
Connected to the clear terminal of the

Effect With this configuration, a clock signal is input to the first DFF, and a clock signal having an opposite phase to the clock signal input to the first DFF is input to the second DFF. Clear pulses of the same width can be generated.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a two-person competitive circuit in one embodiment of the present invention. In Fig. 1, 1 and 2 are DFF, Dl,
D2 is the input terminal of DFFI, 2, CKI, CK respectively.
2 are the clock terminals of DFFI and DFF2, respectively, and the clock terminal CKI.

A clock signal is input to CK2. CLRl, CL
R2 is a clear terminal provided in DFFl and DFF2, respectively, and Ql and Q2 are negative output terminals of DFFI and DFF2, respectively. 3 is an inverter, and 4 is a NAND circuit. External signals are input to input terminals DI and D2, and clock terminals CK1. A clock signal is input to CK2, but a clock signal having an opposite phase to the clock signal input to clock terminal CK2 is input to clock terminal CK.
A clock signal is input to the clock terminal CKI via the inverter 3 in order to input it to the clock terminal CKI. The negative output terminal Q1 of DFFI is connected to the clear terminal CLR2 of DFF2 and NA
It is connected to the input terminal 4a of the ND circuit 4. DFF2
The negative output terminal of DFF1 is the clear terminal CLRI
and is connected to the input terminal 4b of the NAND circuit 4.

The operation of the two-man competition circuit of this embodiment will be described below.

FIG. 2 is a timing chart showing the operation. At this point in time, no signals are input to the input terminals Di and D2, so the signals output from the output terminals Q1 and Q2 are as shown in Fig. 2 (
The signal outputted from the output terminal 4C at H level as shown in D) and (E) is at L level as shown in FIG. 2(F).

At time point A, a signal is input to the input terminal D1 as shown in FIG. 2(A). Then, at the point in time, the clock terminal CK
The clock signal input to I rises. That is, the clock signal input to the clock terminal CK2 is as shown in FIG.
), the signal output from the output terminal Q1 changes to the L level as shown in Figure 2 (D), and the signal output from the output terminal Q2 changes to the L level as shown in Figure 2 (E). As shown, the signal remains at the I level, and the signal output from the output terminal 4C changes to the H level.

Even if a signal as shown in FIG. 2(B) is input to the input terminal D2 at the time point, the clock signal input to the clock terminal CK2 rises as shown in FIG. 2(C) at the time point O. Since the signals output from the output terminal Q1 and the output terminal Q2 remain at L level and H level as shown in FIG. 2(D) and (E), respectively, the output terminal 4c
The signal output from the circuit remains at the H level as shown in FIG. 2(F).

At the moment of input, the signal input to the input terminal D1 has finished being input as shown in FIG. 2(A). Then, at time point K, the clock signal input to the clock terminal CKI rises, that is, the clock signal input to the clock terminal CK2 falls as shown in FIG. 2(B), so that the signal output from the output terminal DI is H as shown in Figure 2 (D).
Since the signal output from the output terminal Q2 remains at the H level as shown in Figure 2 (E), the signal output from the output terminal 4C changes as shown in Figure 2 (F). changes to L level.

At this point, the clock signal input to the clock terminal CK2 rises as shown in Figure 2 (B), so the signal output from the output terminal becomes H as shown in Figure 2 (D).
The signal output from the output terminal Q2 changes to the L level as shown in Figure 2 (E), and the signal output from the output terminal 4C changes to the L level as shown in Figure 2 (F). Changes to H level.

At this point, the input of the signal to the input terminal D2 is completed as shown in FIG. 2(B). Then, at time point C, the clock terminal C
The clock signal input to K2 rises as shown in Fig. 2 (B), and the signal output from the output terminal Q1 remains at I (level) as shown in Fig. 2 (D), and the output terminal The signal output from Q1 changes to H level as shown in FIG. 2(E), and the signal output from output terminal 4c changes to L level as shown in FIG. 2(F).

As described above, according to this embodiment, by providing the DFF 2 to which a clock signal is input, the DFFI to which a clock signal having an opposite phase to the DFF 2 is input via the inverter 3, and the NAND circuit, as shown in FIG. The signals shown in A) and (B) are respectively input to the input terminals D1. By inputting it to D2, it is possible to generate a clear pulse having the same width as the clock signal between the output signals.

Effects of the Invention The present invention provides a first DFF to which a clock signal is input, a second DFF to which a clock signal having an opposite phase to the clock signal input to the first DFF is input, and first and second DFFs. Bias the logic circuit that takes the logical sum of the positive signals output from the DFF, connect the negative output terminal of the first DFF to the clear terminal of the second DFF, and connect the negative output terminal of the first DFF to the clear terminal of the first DFF. By connecting the negative output terminal of the second DFF, a clear pulse with the same width as the clock signal input to the DFF can be output between the output signals, and the width of the clock signal can be widened. It is possible to generate a clear pulse, thereby reliably resetting the DFF connected to the subsequent stage, and also to have the advantage that the entire circuit can be integrated into an integrated circuit, resulting in a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a two-man competition circuit according to an embodiment of the present invention, Fig. 2 is a timing chart of the same, and Fig. 3 is a conventional two-man competition circuit.
A circuit diagram of a human-powered competition circuit, Figure 4 is a timing chart of the same, Figure 5 is a circuit diagram of a conventional two-manpower competition circuit with a DFF connected, and Figure 6 is a circuit diagram of another conventional two-manpower competition circuit. Figure 7 is the same timing chart. 1.2... DFF 3... Inverter 4... Name of NAND circuit agent Patent attorney Toshio Nakao and one other person Figure 1 Figure 3 Figure 4 Figure 5, to Figure 6

Claims (1)

[Claims] a first D flip-flop to which a clock signal is input; a second D flip-flop to which a clock signal having an opposite phase to the clock signal input to the first D flip-flop is input; a logic circuit that takes a logical sum of positive outputs output from the flip-flop and the second D flip-flop, and a negative output terminal of the first D flip-flop is connected to a clear terminal of the second D flip-flop. , and a negative output terminal of the second D flip-flop is connected to a clear terminal of the first D flip-flop.