JPS60127819A - Binary counter - Google Patents

Abstract

PURPOSE:To decrease the number of elements by constituting the two stages of the most significant digit of a binary counter which is made up of plural number of cascade connections of FFs having set/reset function with NAND gates 601, 602 and inverters so as to simplify the most significant digit unit stage. CONSTITUTION:The binary counter 700 is constituted by connecting the FF100- 500 having the set reset function and applying a trigger signal to the next stage in a form of a differentiation pulse and an FF600 comprising the NAND gates 601, 602 and the inverters 603, 604 in cascades. The 1st input terminal of a coincidence gate 601 of the FF600 is connected to a trigger signal terminal P of the FF500, its output is given to the 1st input terminal of a coincidence gate 602, an output of the gate 602 is given to the 2nd input terminal of the gate 601 and the 2nd input terminal of the gate 602 is connected to a reset terminal R of the FF100-500. An output of the inverter 604 is given to a feedback terminal F of an FF5. A clock signal is applied to a terminal 7 and a program value of each bit inputted to a set terminal S of each FF is applied to terminals 17-21.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a binary counter that can be used to digitally measure the period of a signal.

1. Construction of a conventional example and its problems A conventional binary counter of this type is shown in FIG. To explain this, 1, 2, 3, 4, and 5°6 each have a cent function, and each unit stage is connected in cascade with 7 lips and 70 tubes to form a binary counter 16 (in this case, a binary down counter). There is C. 7 is binary-
A clock signal input terminal connected to the clock terminal CL of the flip-flop 1 of the least significant bit (LSB) of the down counter 16, and 8 a common set signal input terminal connected to the set terminals S of each of the flip-flops 1 to 6. , 9 to 14 are program terminals connected to the data terminals of each flip-flop, to which the program value of each bit is applied.

The operation of the conventional binary counter configured as described above will be explained below. for example.

The program value is stored in the counter 16 as a binary number with the most significant bit (
Suppose that it is (000101) from the bjSB) side to the lowest bin) (LSB) side.

A down count is performed from this value. After down-counting is performed and the count value of the counter 15 becomes [1ooOO0] from the MSB to the LSB side, when a clock signal is further input from the clock signal input terminal 7, the count value of the counter 15 changes from the MSB to the LSB side. It becomes (011111) toward the LSB side. That is, the non-inverted output of the MSB flip-flop 6 of the counter 15 is
・0... to "1" and "1" to "Q"-, which means that it has been reversed twice. Therefore, the counter will pass through the same count value twice. However, for example, when measuring the period of a measurement signal using a counter, the count value of the counter and one period of the measurement signal are usually 1:1.
The counter will never reach the same count value more than once. Therefore.

Once the MSH flip 70 of the counter is inverted once from the set value, it will not be inverted any further.

As described above, the MSB flip-flop 6 of the counter 15 does not necessarily have to output an inverted output of the current output state in response to a trigger signal input, unlike the other 7 Rinopflosopts 5 of the counter 15. It is only necessary to invert the current output state once in response to the trigger signal input. Therefore, the MSB flip-flop 6 of the counter 15 does not need to have the same configuration as the other flip-flops 1 to 5 making up the counter 15, and can have a simpler configuration. Counters are often used in digital integrated circuits, and the chip area occupied by the counters is extremely large. Therefore, the configuration of the counter must be made as simple as possible, and the chip area occupied by the counter section in the integrated circuit must be minimized.

OBJECTS OF THE INVENTION An object of the present invention is to provide a binary counter in which the number of elements constituting the counter can be reduced and the chip area occupied by the counter section can be reduced by simplifying the configuration of the topmost unit stage of the counter. The goal is to provide the following.

Structure of the Invention The binary counter of the present invention includes a flip-flop having set and reset functions and means for supplying a trigger signal to the secondary stage in the form of a differential pulse, and a trigger signal terminal to the next stage of the flip-flop. connecting a first input terminal of a first match gate, and connecting a second match gate output terminal to a second input terminal of the first match gate;
a flip-flop, wherein an output terminal of the first coincidence gate is connected to a first input terminal of the second coincidence gate, and a reset terminal of the flip-flop is connected to a second input terminal of the second coincidence gate. The binary counter is configured such that the top two stages of the binary counter are the top two stages of the binary counter.This allows the top unit stage of the binary counter to have a simple configuration, and it can be integrated into an integrated circuit. This reduces the area occupied by the binary counter.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a binary counter according to one embodiment of the present invention. In FIG. 2, reference numerals 100 to 5o○ are Noritubu flops having cent and reset functions and means for supplying a trigger signal to the next stage as a differential pulse, and 600 is a NAND gate 601, 602, an inverter 603, Consisting of 604, N A N D gate eo
1. eo2 constitutes an R-S flip-flop, its set terminal is connected to the trigger signal output terminal of the flip-flop 500, and its reset terminal is connected to the counter terminal commonly connected to the reset terminals of the flip-flops 100 to 500. A reset terminal 16 is connected. Inverters 603 and 604 are for creating a feedback signal to flip 70 tube SOO. 7 lip flop 1
00 to 600 are connected in cascade to create a 6-bit binary counter. 0 (in this case, a binary down counter). 7 is the least significant bit (LSB) of the binary counter 700; 7 is a clock signal input terminal connected to the clock terminal CL of the flip-flop 100; and 16 is a common terminal connected to the reset terminal of each of the flip-flops 100-600. Signal input terminals 17-21 are program terminals connected to the set terminals S of the flip-flops 100-500, to which the program value of each bit is applied.

FIG. 3 is a specific configuration diagram of the flip-flop 100, in which the 1st bit unit stage is composed of NAND gates 101 to 106, and a differential pulse generation circuit is connected to the output side of the ordinary T flip-flop. It has the same functionality as adding .

FIG. 4 is a specific configuration diagram of flip-flops 200 to 600, in which a unit stage is configured by NAND gates 201 to 2015 and ND gate 206. 207 is a program terminal; 208 is a trigger signal output terminal that supplies a trigger signal to the next-stage 7-linop 70 block; 209 is a trigger signal input terminal to which a trigger signal from the previous stage (LSB side) flip 70 block is input; 210 A feedback signal output terminal 211 supplies a feedback signal to the flip-flop in the previous stage, and a feedback signal input terminal 211 receives a feedback signal supplied from the seven flip-flops in the rear stage (MSB side). A detailed explanation of the operation is described in Japanese Patent Application Laid-Open No. 68-84539, so a detailed description thereof will be omitted here.

The operation of the binary counter configured as described above will be explained below. For example, if the program value of the counter 700 is a binary number from the MSB side to the LSB side,
If it is [0o○101], the countdown will not be performed from this value, and the output value of the counter will be (oooooo
o) At the next clock input, the flip-flop 6
The non-inverted output of 00 is inverted by the trigger signal from the flip-flop SOO and changes from 0" to "1". Therefore, the value of the counter 700 becomes (111111).

When further clocks are input, the counter continues counting down. The count value of counter 700 is (100
000), when another clock is input, the count value of the counter 700 becomes (111111), and the counter 700 does not operate normally.

However, when measuring the cycle of a measurement signal using a counter, for example, there is usually a one-to-one correspondence between the count value of the counter and one cycle of the measurement signal.
The count value of 00 never exceeds (100000), and the clock is stopped or the program value is reset to the counter before the count value exceeds (100000). Therefore.

Since the flip-flop at the final stage of the counter only rotates once from the state of the program value, the NAND gate 6
Even if the R-S flip-flop is made up of 01.602, there is no problem in carrying out a counting operation such as measuring the period. In the above-described embodiment, since the configuration of the 7-resop flop 600 is the circuit configuration shown in FIG. 4, the flip-flop 600 includes inverters 603 and 604 to generate a feedback signal. If you use a lip flop for 7 lips 70 tubes 500, it will just be a NAND game) 601.

Only 602 is enough. Further, in order to make the delay between nine stages the same as in other seven-stage flip-flops, the trigger signal from the flip-flop 600 may be delayed and input to the flip-flop 600. Furthermore, in the embodiment of the present invention described above, a NAND gate was used as a coincidence gate to configure the R-S flip-flop of the flip-flop 600, but if the logic is converted, other coincidence gates such as a NOR gate can be used. A flip-flop can also be constructed.

Effects of the Invention As is clear from the above description, the present invention has two features: a flip-flop having cent and reset functions and means for supplying a trigger signal to the next stage in the form of a differentiated pulse;
The trigger signal terminal to the next stage of the flip-flop is connected to the first
a second match gate output terminal connected to a first input terminal of said first match gate, and a second match gate output terminal connected to a second input terminal of said first match gate; A flip-flop in which the output terminal of the first coincidence gate is connected and the reset terminal of the flip-flop is connected to the second input terminal of the second coincidence gate becomes the two most significant stages of the binary counter. Since the binary counter is configured in this way, the top unit stage of the binary counter can be configured simply and the number of elements can be reduced, which is an excellent effect. As a result, the effect of reducing the chip area of the integrated circuit can be obtained.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional binary counter.
FIG. 2 is a block configuration diagram of a binary counter according to an embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams showing specific configuration examples of a flip-flop. 100-600...Flip-flop, 700
...Binary counter.

Claims (1)

[Claims] A flip-flop has a set and reset function, and also has a means for supplying a trigger signal to the next stage with a differential pulse; a second match gate output terminal connected to an input terminal of the first match gate; a second match gate output terminal connected to a second input terminal of the first match gate; Connect the output terminal of the gate,
A binary counter characterized in that the uppermost two stages of the binary counter include a 7-resop flop in which the reset terminal of the clip 70 block is connected to the second input terminal of the second coincidence gate.