JPH0161266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a programmable frequency divider circuit configured with fewer elements or gates than conventional ones.

Figure 1 shows a logical configuration diagram of a programmable frequency divider circuit that has been widely used in the past.Terminal T is a clock pulse input terminal, terminals Q ₀ ,
Q ₁ , Q ₂ , and Q ₃ are the 1st bit count output terminal, the 2nd bit count output terminal, the 3rd bit count output terminal, and the 4th bit count output terminal, respectively, and the terminals D ₀ and D ₁ , D ₂ , and D ₃ are the 1st bit program terminal, the 2nd bit program terminal, the 3rd bit program terminal, and the 4th bit program terminal, respectively.
This is the bit-th program terminal.

In FIG. 1, a unit stage of a counter is constructed by an edge-triggered T flip-flop with six NAND gates, and two NAND gates are used to set or reset the T flip-flop when a preset signal is supplied. A programmable frequency divider circuit is constructed using eight NAND gates per stage.

Figure 2 is a circuit connection diagram in which the logical configuration of Figure 1 is realized using I ² L transistors (the injector of each transistor is omitted for convenience); in this case, a total of 45 I ² L transistors are used. transistors, 11 and a quarter I ² L transistors per stage.

The programmable frequency divider circuit of the present invention significantly reduces the number of gates or elements per stage compared to conventional ones, and by reducing the number of elements while maintaining the same functions as conventional ones, it can simplify the system and reduce power consumption. The circuit is configured to include a bistable circuit equipped with a set terminal and a reset terminal, and a trigger signal from the previous stage that is connected to the set terminal according to the output state of the bistable circuit. A unit stage constituted by a terminal and first and second coincidence gates supplied to the reset terminal, and an output of the first coincidence gate or the second coincidence gate is triggered to the next unit stage. a gate means for supplying a signal; a detection means for detecting a maximum count value or a minimum count value of the counter configured by a plurality of unit stages connected by the gate means; and a detection means for detecting an output signal. The present invention is characterized in that it includes selection preset means for supplying a reset signal or a set signal only to the bistable circuits constituting the preprogrammed unit stage after generating the reset signal.

An embodiment of the present invention will be described below based on the drawings. FIG. 3 shows a logical configuration diagram of a programmable frequency divider circuit according to an embodiment of the present invention. In FIG. 3, NAND gates 11, 12,
13, 14, 15, and 16 constitute a 1st bit unit stage 100, and the unit stage 100 is a unit stage for supplying a trigger signal to the unit stage 200.
It has the same function as adding a differential pulse generation circuit to the output side of a flip-flop.

In the unit stage 200, the first input terminals 21a and 22a of the NAND gate 21 and the NAND gate 22 are cross-coupled to their respective output terminals, and the output terminal of the NAND gate 21 is connected to the first input terminal of the NAND gate 23. The output terminal of the NAND gate 22 is connected to the first input terminal 24a of the NAND gate 24, and the second input terminals 21b and 22b of the NAND gates 21 and 22 are connected to the terminal 23a.
The output terminal of the NAND gate 25 is connected to the
A first input terminal 25a of the NAND gate 25 is connected to the output terminal of the NAND gate 11 constituting the previous unit stage 100, and a second input terminal 25b of the NAND gate 25 is connected to the output terminal of the NAND gate 21. The third input terminal 21c of the NAND gate 21 is connected to the NAND gate 21.
connected to the output terminal of the gate 24, and connected to the output terminal of the gate 24;
The third input terminal 22c of the gate 22 is
connected to the output terminal of the NAND gate 23;
A fourth input terminal 22d and a fifth input terminal 22e of the NAND gate 22 are respectively connected to the output terminals of a NAND gate 31 and a NAND gate 32 that constitute the next unit stage 300,
The second input terminal 23b of the NAND gate 23
Also, the second input terminal 24b of the NAND gate 24 and each output terminal are cross-coupled connected, and the third input terminal 23c of the NAND gate 23 is connected to the output terminal of the NAND gate 26. In addition, the NAND gate 26
The first input terminal 26a of is connected to the program terminal _D1 .

NAND gates 31, 32, 33, 34, 35
The next unit stage 300 configured by NSB has the same configuration as the unit stage 200. In the NSB unit stage 400, an inverter 45 is used in place of the NAND gate 35 of the previous unit stage, The fourth and fifth input terminals of gate 42 are omitted.

Furthermore, the unit stage 100 is configured
A first input terminal 50a of a NAND gate 50 is connected to the output terminal of the NAND gate 14, and the NAND gate 24 constituting the unit stage 200
The second input terminal 50b of the NAND gate 50 is connected to the output terminal of the unit stage 3.
The output terminal of the NAND gate 34 constituting 00 is connected to the third input terminal 50 of the NAND gate 50.
c is connected to the output terminal of the NAND gate 44 constituting the unit stage 400.
A fourth input terminal 50d of the gate 50 is connected,
The output terminal of the NAND gate 50 is connected to the first input terminal 51a of the NAND gate 51.
The second input terminal 51b of the NAND gate 51 is connected to the clock pulse input terminal T.
The output terminal of the NAND gate 51 is connected to the second input terminal 52b of the NAND gate 52,
a second input terminal 17b of the NAND gate 17;
a second input terminal 26b of the NAND gate 26;
a second input terminal 36b of the NAND gate 36;
It is connected to the second input terminal 46b of the NAND gate 46.

Note that in the circuit shown in Figure 3, the NAND gate 5
0 constitutes a detection gate for detecting the minimum count value of the counter, and NAND gates 51, 52,
Reference numerals 17, 26, 36, and 46 constitute a selection preset circuit that supplies a set signal only to a preprogrammed unit stage after the detection gate generates an output signal.

Now, the clock pulse input terminal T and program terminals D ₀ , D ₁ , D ₂ , and D ₃ of the circuit in FIG. 3 are shown as Tx, D ₀ x, D ₁ x, D ₂ x, and D ₃ x in FIG. The operation when a signal waveform is applied will be explained based on FIG. 4. First, let us assume that the counter outputs [Q ₃ , Q ₂ , Q ₁ , Q ₀ ] are [0001] before time t _1. At time t ₁ , the leading edge of the clock pulse arrives and the clock pulse When the level of the input terminal T shifts from "0" to "1", the output level of the NAND gate 12 shifts from "1" to "0" because the output level of the NAND gate 13 has become "1". ,continue
The output levels of NAND gate 14 and NAND gate 15 transition from "0" to "1".

By shifting the output level of the NAND gate 14 to "1", the NAND gate 13 and the NAND
As the output level of the gate 50 shifts from "1" to "0" and the output level of the NAND gate 15 shifts to "1", the NAND gate 16
The output level of the NAND gate 12 shifts from "1" to "0", and then the output level of the NAND gate 12 shifts to "1".
Return to

Furthermore, when the output level of the NAND gate 50 shifts to "0", the output level of the NAND gate 51 shifts from "0" to "1", and then the NAND gate 51 shifts from "0" to "1".
The output level of gate 52 shifts from "1" to "0".

On the other hand, when the output level of the NAND gate 51 shifts to "1", the program terminal
Since the level of D ₀ and D ₃ is “1”,
The output levels of the NAND gate 17 and the NAND gate 46 shift from "1" to "0", and the
As the output level of the NAND gate 17 shifts to "0", the output level of the NAND gate 13 shifts to "1", and the NAND gate 12 and
Since the output level of the NAND gate 15 is clamped to "1", the output level of the NAND gate 14 subsequently shifts to "0", and the NAND
As the output level of the gate 46 shifts to "0", the output level of the NAND gate 43 shifts from "0" to "1", and then the output level of the NAND gate 44 shifts from "1" to "0". Then, the count value of the counter is preset to [1001].

When the output level of the NAND gate 14 or the NAND gate 44 shifts to "0",
The output level of the NAND gate 50 returns to "1".

At time _t2 , when the trailing edge of the clock pulse arrives, the output levels of the NAND gate 16 and the NAND gate 52 shift to "1", and as the output level of the NAND gate 52 shifts to "1", the NAND The output level of gate 51 shifts to "0", and then the output levels of NAND gate 17 and NAND gate 46 shift to "1". When the output level of the NAND gate 17 shifts to “1”, the NAND gate 15
The output level of is shifted to "0".

At time _t3 , when the leading edge of the clock pulse arrives, the output level of the NAND gate 12 shifts to "0", then the output levels of the NAND gates 14 and 15 shift to "1", and the output level of the NAND gate 14 shifts to "1". Output level “1”
, the output level of the NAND gate 13 shifts to "0" and the output level of the NAND gate 13 shifts to "0".
By shifting the output level of 5 to “1”
The output level of the NAND gate 16 shifts to "0".

The output level of the NAND gate 13 is “0”
, the output level of the NAND gate 12 returns to "1", and the arrival of the trailing edge of the clock pulse at time t4 causes the output level of the NAND gate ₁₂ to return to "1".
The output level of the NAND gate 16 returns to "1",
Subsequently, the output level of the NAND gate 15 shifts to "0", the series of output inversion operations of the unit stage 100 is completed, and the output of the counter becomes [1000].
Changes to

Note that since the output level of the NAND gate 11 does not change from time t ₃ to time t ₄ , the output level of each gate configuring the unit stage 200 does not change, and similarly, the output level of each gate configuring the unit stages 300 and 400 does not change. The output level also does not change.

At time _t5 , when the leading edge of the clock pulse arrives, NAND gate 1
Since the output level of 4 is "1",
The output level of NAND gate 11 shifts to “0”, and then NAND gate 13 and NAND gate 1
5. Furthermore, the output level of the NAND gate 25 constituting the next unit stage 200 shifts to "1".

The output level of the NAND gate 13 is “1”
, the output level of the NAND gate 14 shifts to "0" and the output level of the NAND gate 1 shifts to "0".
By shifting the output level of 5 to “1”
The output level of the NAND gate 16 shifts to "0". Further, as the output level of the NAND gate 14 shifts to "0", the output level of the NAND gate 11 returns to "1", and then, with the arrival of the trailing edge of the clock pulse, the NAND gate 16 returns to "1". The output level of the NAND gate 15 returns to "1", and the output level of the NAND gate 15 shifts to "0".

On the other hand, as the output level of the NAND gate 25 shifts to "1", the output level of the NAND gate 21 shifts to "0", and then the output level of the NAND gate 23 shifts to "1", moreover
The output level of the NAND gate 24 shifts to "0". When the output level of the NAND gate 24 shifts to "0", the output level of the NAND gate 21 returns to "1", and then the output level of the NAND gate 25 returns to "0".

On the other hand, as the output level of the NAND gate 21 shifts to "0", the output level of the NAND gate 35 constituting the unit stage 300 becomes "0".
to “1”, and then NAND gate 31
The output level of shifts to “0”, and as a result
The output level of the NAND gate 33 and the inverter 45 constituting the next unit stage 400 shifts from "0" to "1", and the NAND gate 3
By shifting the output level of 3 to “1”
The output level of NAND gate 34 changes from “1” to “0”
Then, the output level of the NAND gate 31 returns to "1", and the output level of the NAND gate 35 returns to "0".

Further, as the output level of the inverter 45 shifts to "1", the output level of the NAND gate 42 shifts from "1" to "0", and then
The output level of the NAND gate 44 shifts from "0" to "1", and the output level of the NAND gate 43 shifts from "1" to "0", and as a result, the output level of the NAND gate 42 becomes "1". At this point, the count output of the counter changes to [0111].

Note that the output level of the inverter 45 is
As the output level of the NAND gate 31 shifts to "1", it shifts to "0".

At time t ₆ , when the trailing edge of the clock pulse arrives, the same as at time t ₄ occurs.
The output level of the NAND gate 16 shifts to "1", and then the output level of the NAND gate 15 shifts to "0".

At time _t7 , when the leading edge of the clock pulse arrives, the output level of each gate making up the unit stage 100 changes in the same way as at time _t3 , and the count output of the counter becomes [0110].
becomes.

At time _t8 , when the leading edge of the clock pulse arrives, the output level of each gate constituting the unit stage 100 changes in the same way as at time _t5 , but the output level of the NAND gate 11 shifts to "0". By NAND gate 25
The output level of NAND shifts to “1”, and now NAND
Since the output level of the gate 23 is "1", the output level of the NAND gate 22 subsequently shifts from "1" to "0", and as a result, the output level of the NAND gate 24 shifts to "1". Then, the output level of the NAND gate 23 shifts to "0", the output level of the NAND gate 22 returns to "1", and the count output of the counter becomes [0101].
becomes.

When the leading edge of the clock pulse arrives at time _t9 , only the output level of each gate constituting the unit stage 100 changes, and the count output of the counter becomes [0100].

When the leading edge of the clock pulse arrives at time _t10 , the output level of each gate constituting unit stage 100 and unit stage 200 changes in the same way as at time _t5 , but
As the output level of the NAND gate 21 shifts to "0", the output level of the NAND gate 35 shifts to "1", and subsequently the output level of the NAND gate 32 shifts from "1" to "0".
The output level of the NAND gate 34 shifts to "1", the output level of the NAND gate 33 shifts to "0", and the output level of the NAND gate 32 returns to "1", and the count output of the counter becomes [0011 ].

Note that the output level of the NAND gate 35 returns to "0" as the output level of the NAND gate 21 shifts to "1".

Similarly, when the leading edge of the clock pulse arrives at time _t11 , the count output of the counter becomes [0010] and becomes [0001] at time _t12 .

When the leading edge of the clock pulse arrives at time _t13 , the output level of each gate constituting the unit stage 100 changes in the same way as at time _t11 , but when the output level of the NAND gate 14 shifts to "1", time t Same as in ₁
The output level of the NAND gate 50 shifts to "0", and then the output level of the NAND gate 51 shifts to "1".

The output level of the NAND gate 51 is “1”
Program terminal D ₀ in advance before moving to
The level of the program terminal D ₁ , shifts to “0”, and
Since the level of D ₂ has shifted to “1” and the level of program terminal D ₃ remains “1”,
By shifting the output level of the NAND gate 51 to "1", the NAND gates 26, 36, 46
The output level of the counter shifts to “0”, and as a result, the count value of the counter is preset to [1110],
It is equal to the program value [D ₃ , D ₂ , D ₁ , D ₀ ].

At time _t14 , when the trailing edge of the clock pulse arrives and the output level of the NAND gate 52 shifts to "1", the output level of the NAND gate 50 has already become "1", so the output level of the NAND gate 51 changes to "1". The level returns to "0", and the counter decrements its count value by 1 each time the leading edge of the clock pulse arrives, as after time _t2 .

That is, the programmable frequency divider circuit shown in FIG. 3 has the same function as the conventional programmable frequency divider circuit shown in FIG. 1.

Now, when we compare the number of gates of the 4-bit programmable frequency divider circuit in Figure 1 and the 4-bit programmable frequency divider circuit in Figure 3, we find that the conventional frequency divider circuit
It can be seen that the frequency divider circuit of the present invention, which used to be composed of 35 NAND gates, can be composed of 27 NAND gates and one inverter. Furthermore, the rate of reduction in the number of gates compared to the conventional circuit increases as the number of bits in the counter increases.

By the way, if the programmable frequency divider circuit shown in FIG. 3 is constructed using the I ² L transistor, the fifth
As shown in the figure, whereas the conventional frequency divider circuit shown in Figure 2 required 45 I ² L transistors,
The frequency divider circuit shown in FIG. 5 can be configured with 31 I ² L transistors, and the number of elements can be significantly reduced.

As described above, the programmable frequency divider circuit of the present invention can obtain the same function as the conventional programmable frequency divider circuit with a smaller number of gates or elements than the conventional one, but its logical configuration is not necessarily limited to the configuration shown in FIG. That doesn't mean it's true.

For example, if a differential pulse-like clock pulse is obtained in advance, the first stage (LSB) unit stage 100 can have the same configuration as the unit stage 200 or the unit stage 300,
If the design takes into consideration the propagation delay of the propagation pulse, it is possible to simplify the structure of each unit stage as shown in FIG. 6. In FIG. 6, the configurations of unit stages 200, 300, and 400 are the same as the configuration of unit stage 400 in FIG. 3.

By the way, in the embodiments of the present invention shown in FIGS. 3 and 6, each unit stage is constructed using a NAND gate, and a down counter is constructed by these unit stages.
Other coincidence gates may be used in place of the NAND gate, or a bistable circuit (for example, in the unit stage 200, the bistable circuit is ) is not dependent on the combination of match gates, e.g.
It may be constructed from a clocked inverter, which is often used in CMOS counter circuits, or the counter constructed by combining unit stages may be an up counter.

In the embodiment shown in FIG. 3, since the counter is in the form of a down counter, the NAND gate 50 detects the final count value of the counter.
detects the minimum count value [0000] of the counter, and also detects the NAND gates 51, 52, 17, 2
The selection preset circuit constituted by 6, 36, and 46 supplies a set signal to the bistable circuit constituting each unit stage after the detection gate constituted by NAND gate 50 generates an output signal. However, when the counter is in an up-counter format, the NAND gate 50 constituting the detection gate detects the maximum count value of the counter, and the selection preset circuit supplies a reset signal. It should be configured as follows.

As described above, the programmable frequency divider circuit of the present invention includes a bistable circuit equipped with a set terminal and a reset terminal,
A unit stage is constituted by first and second coincidence gates that supply a trigger signal from the previous stage to the set terminal and the reset terminal according to the output state of the bistable circuit, and the first coincidence gate Alternatively, a counter is configured by connecting each unit stage in series so that the output of the second coincidence gate is supplied as a trigger signal to the next unit stage, and detection is performed to detect the maximum count value or minimum count value of the counter. and selection preset means for supplying a reset signal or a set signal only to the bistable circuit constituting the preprogrammed unit stage after the detection means generates the output signal. To explain the embodiment shown in FIG. 3, the first input terminal 23a and the first input terminal 24a of the NAND gate 23 and the NAND gate 24 constituting the bistable circuit in the unit stage 200 are connected to the set terminal. and constitute the reset terminal, and the NAND gate 21 and the NAND gate 22
constitute the first coincidence gate and the second coincidence gate, and the NAND gate 50 constitutes the detection means.

That is, in the programmable frequency divider circuit of the present invention, a unit stage is configured by a bistable circuit and first and second coincidence gates for distributing a trigger pulse to the bistable circuit, and the unit stage is connected in series. The number of gates is reduced compared to the conventional one, since it is equipped with a selection preset means that supplies a set or reset signal only to the bistable circuits constituting the preprogrammed unit stage after the final count of the connected and configured counters. Alternatively, the same function as the conventional one can be obtained with the same number of elements, and a great effect can be achieved.

[Brief explanation of drawings]

Figure 1 is a logical configuration diagram showing an example of a conventional programmable frequency divider circuit, and Figure 2 shows the logical configuration of Figure 1.
Circuit wiring diagram realized by I ² L transistor,
FIG. 3 is a logical configuration diagram of a programmable frequency divider circuit according to an embodiment of the present invention, FIG. 4 is a signal waveform diagram of each part of FIG. 3, and FIG. 5 is a logical configuration diagram of FIG. 3 according to the present invention. FIG. 6, which is a circuit wiring diagram realized by a ^2L transistor, is a logical configuration diagram showing another embodiment of the present invention. 11, 21, 31, 41...First matching gate, 12, 22, 32, 42... Second matching gate, 13, 14, 23, 24, 33, 34, 4
3, 44... Bistable circuit, 23a... Set terminal, 24a... Reset terminal, 17, 26, 3
6, 46, 51, 52...selection preset circuit,
50...Detection gate.

Claims (1)

[Claims] 1. A bistable circuit having a set terminal and a reset terminal, and first and second coincidence gates that supply a trigger signal from the previous stage to the set terminal and the reset terminal according to the output state of the bistable circuit. a unit stage configured, a gate means for supplying an output of the first coincidence gate or the second coincidence gate to a next unit stage as a trigger signal, and a plurality of units coupled by the gate means. A detection means for detecting the maximum count value or minimum count value of the counter constituted by the stage, and a reset signal only for the bistable circuit constituting the pre-programmed unit stage after the detection means generates an output signal. or a programmable frequency divider circuit with selection preset means for providing a set signal.