JPS5829222A - Binary counter - Google Patents

Abstract

PURPOSE:To decrease the number of logical gates by composing the 1st unit stage of the 1st and 2nd couples of NAND gates having input and output terminals connected on cross coupling basis, and using NOR gates for the 2nd unit stage of similar constitution instead of using the NAND gates. CONSTITUTION:When a trigger signal T has a level ''0'' at time t3, the output of a gate 2 has the level ''0''. At this time, a reset signal R is ''0''. When the trigger signal T goes up to ''1'' at time t4, the output of the gate 3 is ''0'', so the outputs of gates 2 and 6 are ''L''. Gates 1-7 are NAND gates. Then, the output of the gate 7 goes down to ''0'', so the output of the gate 3 returns to ''1'' and the output of an NOR gate 10 goes up to ''1''. Then, the output of an NOR gate 12 goes down to ''0'', the output of an NOR gate 11 goes up to ''L'', and further the output of the gate 10 returns to the ''0''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a binary system that can configure a unit stage with a smaller number of gates than conventional methods and can also operate at high speed.
It provides a counter.

As is well known, counters (including branch dividers) that have been widely used in the past have an edge-trigger type T circuit whose basic logic configuration is an interconnection of six NAND gates or six NOR gates. The unit stage is composed of flip-flops, but the second type of counter is used for all devices.

Since T flip-flops have become central to digital systems, especially digital LSIs, in recent years many attempts have been made to reduce the number of gates in T flip-flops that constitute a unit stage of a counter.

In particular, I2L and IC allow analog and digital circuits to be mixed together, so their application to fields such as cameras, watches, and micromotor control circuits is remarkable. The number of elements differs depending on whether the circuit is only used for rounding or when a resetting function is added. ) has also been announced where the unit stage was reduced to four elements.

These cases are IEEE TOURNAL 0FS
OLID'5TATE CIRCUITS, VoLS
PP of C-11° No. 6 (1976), 847-8
51 P, A.

TUCCI and L, ni, RUSSIi:L;
Anl LWatch Chip with Dir
ect LED Drive' and the same IEEE magazine's Vo.
t, 5c-14, No. 3 (1979) (7) PP65
7-660U, ABLASSMEIER;' Com
Patison of Various Binary
It is introduced in Dividetgin I2L'.

However, these 4-element flip-flops did not provide an inverted output as an output signal, or required a special structure different from conventional ones.In addition, as shown in the latter paper, these Due to its special configuration, the four-element flip-flop has a problem in that its usable limit frequency is significantly lowered.

In addition, these flip-flops have the disadvantage that they can only be applied to ICs with a 12L structure.The present invention realizes a counter configured with four coincidence gates per unit stage, and the above-mentioned This solves various problems.

FIG. 1 is a logical configuration diagram of a binary counter with a reset function in one embodiment of the present invention.

In FIG. 1, NAND gates 1, 2, 3, 4, AN
D game) 5. 'NANDNOR gate 6 constitutes the first unit stage 100, and this unit stage 100K
Therefore, the signal frequency applied to the trigger signal input terminal T is counted down to one half, and a trigger signal with a narrow pulse width is generated to be supplied to the next stage.

Note that in the second unit stage 200 in which the first bit output terminal A is connected to the output terminal 6b of the NAND gate 6, the first input terminals 9a, 1 are connected to the output terminal 6b of the NAND gate 6.
0a and output terminal eb.

A first NOR gate pair 201 consisting of three human-powered NOR gates 9 and 10 to which 1ob is cross-coupled and each first input terminal 11a.

12a and the output terminals zb and t2b are cross-coupled connected to each other.
A second input terminal 11a of the OR gate 11 is connected to the output terminal 9b of the NOR gate e.
The second input terminal 120 of the NOR gate 10 is connected to the output terminal 10b of the NOR gate 10, and the second input terminal 9c, 100 of the NOR gate 9, 1o is connected to the output terminal 12b of the NOR gate 12, 11, respectively. 11b, the third input terminal θd, 1od of said NOR gate 9.10
are both connected to the output terminal 3b of the NAND gate 3.

Further, the third input terminal 11d of the NOR gate 11 is connected to the reset signal input terminal R, and the output terminal 1! of the NOR gate 11 is connected to the reset signal input terminal R. A second bit output terminal B is connected to b.

The third unit stage 300 is a 3-person NAND game) 1
3, 14, 16, and two human-powered NOR gates 16, and the third
is connected to the bit output terminal C of the NAND gate 1.
The third input terminal 1ed of the inverter 6 is the output terminal 8 of the inverter 8.
The outside of the point plate connected to b is the second unit stage 2.
00 NOR gates 9 to 12 to NAND gates 13 to 1
It has the same configuration as the one replaced with 6.

Note that the input terminal 8a of the inverter 8 is connected to the reset signal input terminal H.

Sarani, 3-person NOR Kate 1.7. 18. The fourth unit stage 400, which is composed of a NOR gate 19 and two human-powered NOR gates 20, has the same configuration as the unit stage 200, and the output terminal 19b of the NOR gate 19
A fourth bit output terminal is connected to the fourth bit output terminal.

Now, in the circuit of Fig. 1, the trigger signal input terminal T,
When signals shown as T and R in FIG. 2 are applied to the logic gates 8 and 1 to
The output signal waveforms of 7, 9-12, 13-16° and 17-2o are 8114-豐7' and e'-12 in Fig. 2, respectively.
? 1a as shown at 16' and 17 and 20'.

That is, if the level of the trigger signal input terminal T is "0" and the level of the reset signal input terminal H is "1" before time t, then the unit stage 1
Among the logic gates configuring 00, NAND gate 1
, 2, 3, 4.7 output level is I″1″, ANDN
The output level of the O-gate NAND gate 6 is 0''.

Further, among the logic gates constituting the unit stage 200, the output level of the NOR gates 9, 10, and 11 is 0'', and the output level of the NOR gate 12 is 1''.

Further, among the logic gates constituting the unit stage 300, the output level of the NAND gates 13, 14, and 16 is -1'', and the output level of the NAND gate 16 is '0''.

Similarly, among the logic gates constituting the unit stage 400, NOR gate 17. The output level of the gates 18 and 19 is o'', and the output level of the NOR gate 2o is 11''.

At time t, when the level of the trigger signal input terminal T shifts to '1', the NAND gate 1 and the NA
The output level of the NAND gate 4 shifts to "o", but as the output level of the NAND gate 1 shifts to "0", the output level of the NAND gate 4 immediately changes to '1'.
Return to

Note that the output levels of other logic gates do not change.

When the level of the reset signal input terminal H shifts to 0'' at time t2, the reset state is released and the output level of the inverter) 8 shifts to 1'', followed by ANDNO.
The gate output level shifts to 1'', but the output levels of the other logic gates do not change.

At time t3, when the level of the trigger signal input terminal T shifts to "o", the output level of NAND gate 1 shifts to "1", and further the output level of NAND gate 2 shifts to "o". \The output levels of other logic gates do not change.

- When the level of the trigger signal input terminal T shifts to 1'' at time t4 (when the leading edge of the trigger signal arrives), the output level of the NAND gate 3 changes to 0''.
As a result, the output levels of the NAND gates 2 and 6 both shift to 1''.

When the output level of the NAND gate 2 shifts to 1", the output level of the NAND gate 1 shifts to 0", and when the output level of the NAND gate 6 shifts to 1", the output level of the NAND gate 7 shifts to 0". Then, the output level of the NAND gate 3 returns to '1'.

On the other hand, when the output level of NAND gate 3 shifts to '0' by 10°, the output level of NOR gate 1o changes to '0'.
As a result, the output level of the NOR gate 12 shifts to f'0", but as the output level of the NOR gate 12 shifts to f'0", the output level of the NOR gate 11 becomes '1'. , and then the NOR gate 1
o's output level returns to 0''.

When the output level of the NOR gate 10 returns to "Ilo", the output level of the NAND gate 3 has already reached 1.
”, the output level of the NOR gate 9 does not change at this point.

Furthermore, when the output level of the NOR gate 10 shifts to "1", the output level of the NAND gate 13 subsequently shifts to "1".
As a result, the output level of the NAND gate 16' shifts to 1"; however, due to the shift of the output level of the NAND gate 16 to 1",
The output level of the NAND gate 13 shifts to 60'', and then the output level of the NAND gate 13 returns to 1''.

When the output level of the NAND gate 13 returns to "1", the output level of the NOR gate 10 has already been shifted to "o", so at this point the NAND
The output level of the D gate 14 does not change.

When the output level of the NAND gate 13 shifts to '0', the output level of the NOR gate 18 subsequently shifts to '1', and as a result, the output level of the NOR gate 20 shifts to '6'.
However, as the output level of the NOR gate 2o shifts to '0', the output level of the NOR gate 19 shifts to '1', and then the output level of the NOR gate 18 shifts to '0'. ” Return to

At time t5, the level of the trigger signal input terminal T is O”
(when the trailing edge of the trigger signal arrives), the output level of NAND gate 1 shifts to '1', and then the output level of NAND gate 2 shifts to '0', but other logic gates The output level does not change.

When the leading edge of the trigger signal arrives at time t6, the output level of NAND gate 4 becomes 0.
”, and then the ANDNO gate output level also goes to '0'.
Since the output level of the NAND gate 2.7 shifts to "1", the output level of the NAND gate 2.7 shifts to "1".

When the output level of the NAND gate 2 shifts to "1", the output level of the NAND gate 1 shifts to "0",
When the output level of the NAND gate 7 shifts to 1", the output level of the NAND gate 6 shifts to 0", so the output level of the NAND gate 4 returns to "1", and then the output level of the AND gate 6 also shifts to 0". Return to 1”.

When the trailing edge of the trigger signal arrives at time t7, only the output levels of NAND gates 1 and 2 change in the same way as at time t6.

When the leading edge of the trigger signal arrives at time t8, each logic gate making up the unit stage 100 operates in the same way as at time t4, and the output level of the NAND gate 3 shifts to "o". When the output level of NOR gate 9 shifts to '0', the output level of NOR gate 9 shifts to 1",
Subsequently, the output level of the NOR gate 11 shifts to 0'',
Further, since the output level of the NOR gate 12 shifts to 1'', the output level of the NOR gate 9 returns to '0''.

Since the output level of the NOR gate 10 does not change at this point, the output level of each logic gate constituting the unit stage 300 and 400 changes to a unit when the leading edge of the trigger signal arrives at 1 t g. The operation of each logic gate constituting stages 100 and 200 becomes the same as at time t4, and the output level of NOR gate 1o shifts to "1".

When the output level of the NOR gate) 10 shifts to 1", the output level of the NAND gate 14 shifts to @O",
Subsequently, the output level of the NAND gate 16 shifts to '1', and further the output level of the NAND gate 16 shifts to 'o'.
Therefore, the output level of the NAND gate 14 returns to 1''.

14° time t. When the leading edge of the trigger signal arrives, the operation of each logic gate constituting the unit stages 100, 200 and 300 becomes the same as at time t, and the output level of the NAND gate 13 shifts to '0'.

When the output level of the NAND gate 13 shifts to "o", the output level of the NOR gate 17 shifts to 1",
Subsequently, the output level of the NOR gate 19 shifts to '0', and the output level of the N6R gate 20 shifts to '1', so that the output level of the NOR gate 17 returns to '0'.

In this manner, the binary counter of FIG. 1 decreases the numerical value of the count output (DCBA) appearing at each bit output terminal by one each time the leading edge of the trigger signal applied to the trigger signal input terminal T arrives. Eventually, at time '11, the count output becomes (1111)
If the level of the reset signal input terminal H shifts to '1' in the state where
The output level of D gate 6 shifts to "0" and at the same time the NA
The output level of the ND gate 16 shifts to 11''.0 When the output level of the AND gate 5 shifts to 0'',
Subsequently, the output levels of NAND gate 2 and NAND gate 7 shift to 1", and as the output level of NAND gate 2 shifts to 1", the output level of NAND gate 1 shifts to "0". As the output level of the NAND gate 7 shifts to '1', the output level of the NAND gate 6 shifts to 'O'. - Also, the output level of the NOR gate 11 shifts to '0'. As a result, the output level of the NOR gate 12 shifts to 61'', which is 1'1 of the output level of the NAND gate 16.
As the output level of the NAND gate 16 shifts to "0", the output level of the NOR gate 20 shifts to "1" as the output level of the NOR gate 19 shifts to "0".

As a result, the output of the counter becomes (0000) and the reset is completed.

Incidentally, in the circuit shown in FIG. 1, the first unit stage 100 has a different configuration from the second and subsequent unit stages, but the unit stage 100 is connected to the output side of an ordinary edge trigger type T flip-flop. It has the same function as adding a differential pulse generation circuit. .

Therefore, as shown in FIG. 3, the unit stage 100 has a general edge-trigger type T flip-flop 501 with a differential pulse that generates narrow pulses at the leading edge and trailing edge of the output signal of the T flip-flop 501. It can also be configured by adding a generating circuit 602.

In addition, when a differential pulse is applied as a trigger signal, the kidney changes the configuration of the unit 3 stage 00 to the subsequent unit -''
The binary counter of the present invention can be the same as the unit stage 200. of FIG. ．． 30
It features a ``configuration of 0,400'', and its configuration is simpler than that of the conventional 6-gate Frikbouf 17-Rozzo. ``First of all, the number of gates used is reduced, especially , M.O.
In the 8IC, the NAND gate and NOR gate can be configured with the same number of elements, which has a great effect on reducing the IC chip size and power consumption.

In addition, the load on each unit stage for resetting is reduced from 2 to 3 in the conventional system to 1, and the fan-out of the reset gate is reduced, making high-speed resetting possible.

Further, in the binary counter of the present invention, if the power consumption is allowed to be the same as that of the conventional circuit, the allowable power consumption per gate is increased, so that the follow-up frequency (operating frequency) of the counter can be higher than that of the conventional circuit.

Furthermore, as is clear from FIG. 2, the signal transmission delay time between each stage is only one gate, which is half that of the conventional counter, so it can be operated at higher frequencies.

In this manner, the binary counter of the present invention includes a first gate pair consisting of first and second NAND gates whose respective first input terminals and output terminals are cross-coupled, and each first input terminal a second gate pair of third and fourth NAND gates whose terminals and output terminals are cross-coupled connected, and the third NAND gate;
an output signal of the first NAND gate is applied to a second input terminal of the fourth NAND gate, an output signal of the second NAND gate is applied to a second input terminal of the fourth NAND gate; Applying the output signals of the second pair of gates to the second input terminals of the second NAND gates, respectively;
a first unit stage connected to apply a trigger signal to the third input terminals of the first and second ONAND gates; and an NA of the first unit stage;
It is equipped with a second unit stage in which all ND gates are configured as NOR gates, and the first unit stage and the second unit stage are alternately connected in cascade, so that the number of interpolation gates constituting the unit stage can be reduced. This makes it possible to reduce the IC chip size, reduce power consumption, or increase the usable limit frequency, which is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a logical configuration diagram of a binary counter according to an embodiment of the present invention. FIG. 2 is a signal waveform diagram of each part in FIG. 1, and FIG. 3 is a logical configuration diagram showing another example of the configuration of the first unit stage. 100.200,300,400・river・unit stage. Name of agent: Patent attorney Toshio Nakao and one other person (

Claims (1)

[Claims] (1) A first gate pair consisting of first and second NAND gates whose respective first input terminals and output terminals are cross-coupled, and whose respective first input terminals and output terminals are cross-coupled. 3rd and 4th NA ring connected
a second gate pair with ND gates, and the rate 3
The second input terminal of the NAND gate of the first NAND
applying an output signal of the D gate, applying an output signal of the second NAND gate to a second input terminal of the fourth NAND gate, and applying an output signal of the second NAND gate to a second input terminal of the first and second NAND gates; a first unit connected to apply the output signal of the second gate pair to each of the gates, and apply a trigger signal to the third input terminal of the second and second NAND gates, respectively; stage, and a second unit stage in which all the NAND gates of the first unit stage are configured as NOR gates, and the first unit stage and the second unit stage are alternately connected in cascade. Features a binary counter. (2) The binary counter according to claim (1), characterized in that the NAND gate and the NOR gate are constituted by MOS transistors and stars.