JPS63211811A - Pwm converter - Google Patents

Abstract

PURPOSE:To eliminate the need for an IC for digital comparator by constituting the titled converter by counters and gate elements only. CONSTITUTION:A complementary number calculator 103 outputting a complementary parallel digital data being an complementary value in receiving a parallel digital data and an inverter 106 inverting the most significant digit outputs of binary counters 100, 101 and 102 with preset and outputting the result as a PWM (Pulse Width Modulation) pulse are provided. While the next clear pulse is inputted to the binary counter with preset after the PWM pulse changes from a high level to a low level, the count-up of the binary counter with preset is stopped and the load pulse is sent to the binary counter with preset just after the clear pulse is inputted to the binary counter with preset. Thus, the constitution is simplified and miniaturized.

Description

[Detailed Description of the Invention] A. Field of Industrial Application The present invention is directed to PWM (Pulse Width Modular
This converter is designed to have a simple and compact structure.

B. Summary of the Invention The present invention sets a complementary value of parallel digital data as a preset value in a binary counter with a preset, which is cleared at regular intervals, immediately after clearing, and counts up from this preset value to a full count. This is a PWM converter that obtains a PWM pulse by inverting the highest counter output of the counter.

C3 Conventional Technology In the fields of signal transmission and power transmission, PWM modulation is used to convert parallel digital data into PWM pulses.

Here, a conventional PWM converter that performs the above-mentioned PWM modulation will be explained.

FIG. 5 shows a conventional asynchronous PWM converter. As shown in the figure, three digital comparators 10, 11 .
12 constitutes a 12-bit digital comparator section, and three binary counters 20, 21
22 constitutes an asynchronous counter section. Note that each binary counter 20, 21゜22 has an output terminal q
and input terminal INB are connected, each functioning as a hexadecimal counter. Then, the 12-bit parallel digital data M (2 to M1□), which is the command value, is input to the digital comparators 10, 11.12. on the other hand,
The reference clock a is input to the input terminal I of the binary counter 20.
It is input to NA and counted, and the binary counter 20
, 21°22 is calculated by the digital comparator 10. It, 12 is input and compared with parallel digital data M. Also, during a certain period of time, the clear pulse b is applied to each reset terminal R8(1) of the binary counters 20, 21, 22.

It is input to R8(2).

FIG. 6 shows a conventional synchronous PWM converter. As shown in the figure, three digital comparators 13, 14, 1
5 constitutes a 12-bit digital comparator section. In addition, three synchronous binary counters 2
3, 24, and 25 constitute a synchronous counter section by connecting the lower carry terminal CARRY to the upper enable terminals ENP and ENT. Then, 12-bit parallel digital data M (to
Mt t) are digital comparators 13, 14, 15
is input. On the other hand, the reference clock a is input to the clock terminal CK of the binary counters 23, 24.25 and counted, and the count value by the binary counters 23, 24.25 is input to the digital comparators 13, 14, 1.
5 and is compared with parallel digital data M. Further, a clear pulse b is input to each clear terminal CLR of the binary counters 23, 24, and 25 at regular intervals.

Although there is a difference between the asynchronous type and the synchronous type in the above two conventional technologies, their main operations are the same, so both operations are
A summary will be explained with reference to the figures.

When the clear pulse b is input at time t, the counters 20, 21, 22, 23, 24.degree. 25 are reset to -H and then start counting the reference clock a. Time t
, and before t2, the count value is smaller than the value of the parallel digital data M, and at this time, the highest output signal P of the comparator section is at a high level H. After time t2, the count value becomes larger than the value of the parallel digital data M, and the output signal P becomes the p-level L. Thereafter, at time t3, the count value by the counter section becomes a full count, and the clear pulse b is outputted again to reset the count section. Therefore, the output signal P becomes high level H again. From then on, similar operations are repeated. In this case, since the time T during which the output signal P is at the high level H corresponds to the parallel digital data M, the output signal P becomes a PWM pulse indicating the data M which is the command value. Note that the input interval period T2 of the clear pulse b is the time from the reset state to the full count of the counter section.
This period T2 is the period of the PWM pulse P.

D. Problems to be Solved by the Invention By the way, since the above prior art is configured using a binary counter and a digital comparator, it requires not only an IC (integrated circuit) for the binary counter but also an IC for the digital comparator. be. Since two types of ICs must be used in this way, the configuration becomes large.

In view of the above-mentioned prior art, the present invention provides a simple and compact P
The present invention provides a WM converter.

E. Means for Solving the Problems The configuration of the present invention that solves the above problems is such that by inputting a reference clock and parallel digital data as a command value, a PW corresponding to the parallel digital data is generated.
A PWM converter that outputs M pulses includes a complement calculator that outputs complement parallel digital data that is the complement value when parallel digital data is input, and a complement calculator that outputs the complement parallel digital data that is the complement value when a load pulse is input. A binary counter with a preset, which is read and set as a preset value, counts up from the preset value in synchronization with a reference clock, and is further cleared by a clear pulse input at regular intervals, and a binary counter with a preset. The inverter inverts the highest output of the PWM pulse and outputs it as a PWM pulse. The present invention is characterized by having a stop section that stops the count-up operation of the binary counter, and a load pulse generation section that sends a load pulse to the binary counter with preset immediately after the clear pulse is input to the binary counter with preset. .

F. Example Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an asynchronous PWM converter according to the invention.

As shown in the figure, three preset binary counters 100, 101 and 102 constitute an asynchronous counter section. The complement calculator 103 calculates complement parallel digital data M, which is a complement value of parallel digital data M, which is a command value.

That is, ~M1° of the data M is inverted, and M and □ are made to correspond to 0 to obtain complement parallel digital data M. At this time, the counter 100. 10
1. The maximum count value of the counter section by MI
1, then M0M=M. 8 holds true.

The reference clock a is input to the clock terminal CKI of the binary counter 100 via the Nant gate 104, and the clear pulse b is input to each binary counter 100, 1.
It is input to the clear terminal CLK of 01 and 102.

The delay circuit 105 generates a load pulse C by slightly delaying the clear pulse b, and this load pulse C is input to the load terminal LOAD of each binary counter 100, 101, and 102.

A counter output d, which is the highest output of the counter unit composed of binary counters Zoo, 101, and 102, is input to an inverter 106. RS flip flop 10
7, the signal from the inverter 106 is input to the reset terminal R, the clear pulse b is input to the set terminal S, and the output terminal Q is connected to the NAND gate 104.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

(il Clear pulse b generated every fixed period T2
is input to the counters 100, 101, and 102 at time t, the count value becomes O and the counter output d
becomes low level. Further, the output signal e of the inverter 106 becomes high level H. Since the 0-de pulse C is input to the counters 100, 101, and 102 immediately after time t, the complement parallel digital data M is input to the counter 10.
0, 101, and 102, which become preset values. In other words, the count value once becomes 0 and then immediately becomes M.

(II) After that, counters 1oo, 101, 102
is counted up every time the reference clock a is input.

(l111 At time t2, counters 100, 10
1゜102 is a full count and the count value is Mma
It becomes x. This lick counter output d goes to high level H,
Further, the output signal e becomes low level L. Furthermore, since the output signal f of the flip-flop 107 becomes low level,
Nantes gate 104 with or without reference clock a
The output signal becomes high level H. Therefore, time t2
Thereafter, the count-up operations of the counters 100, 101, and 102 are stopped.

6ψ At time t3, the clear pulse b is again input to the counters 100, 101, and 102, and the counter value becomes 0. Then, as in the previous case, the complement parallel digital data M is loaded by the load pulse C. At this time, RS
Since the flip-flop 107 is set and the output signal f is H, the reference clock a is output from the Nant gate 104.
is input to the counter 100 via. Therefore, the counters 100, 101, and 102 restart the count-up operation from the value M. Thereafter, similar =11- operations are repeated.

In the above-described operation, the time T during which the output signal e is at a high level corresponds to the value of the parallel digital data M, so this output signal e becomes a PWM pulse corresponding to the command value M.

FIG. 3 shows a synchronous PWM converter according to the invention. As shown in the figure, three preset synchronous binary counters 200, 201 and 202 constitute a synchronous counter section. The complement calculator 203 calculates complement parallel digital data M from the parallel digital data M. Counter output g which is the highest output of the counter section
is input to the inverter 204, and the output signal of the inverter 204 is input to the AND gate 205.

The D flip-flop 206 and the Nant gate 207 are
Clear pulse b from reference clock a and periodic clock l
'make. Also, the D flip-flop 208 and the Nant gate 2o9 create a stomach pulse C' from the output of the D flip-flop 206 and the reference clock a.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4.

(1) Periodic clock l whose period is T2 is at time t
When the reference clock a becomes high level at 1, the clear pulse b' is output from the Nant gate 207, and when the next reference clock a is input immediately after that, the load pulse C' is output from the Nant gate 209. .

Therefore, the count values of the counters 200, 201, and 202 become M immediately after reaching 0 once.

(11) After that, counters 200, 201, 202
is counted up every time the reference clock a is input.

(2) At time t2, counters 200, 201°20
2 becomes a full count, and the count value becomes Mmax. Therefore, the counter output g becomes a high level H, and the output signal becomes a low level L. On the other hand, since the output signal becomes low level, the output of the AND gate 205 becomes low level, and the counter 202 becomes in an unenabled state (incapable of counting).

Therefore, after time t2, the counter 200°201.2
The count-up operation of 02 is stopped.

- At time t3, the periodic clock l becomes high level H and the clear pulse b' is outputted to the counters 200, 201, 2 again.
02 and the counter value becomes 0. Then, as in the previous case, the complement parallel digital data M is loaded by the load pulse C'. Therefore, counters 200, 201
, 202 restarts the count-up operation from the value M. After that, the same operation is repeated.

In the above-described operation, the time T during which the output signal is at a high level corresponds to the value of the parallel digital data M, so this output signal becomes a PWM pulse corresponding to the command value M.

G. Effects of the Invention As specifically explained in conjunction with the embodiments, according to the present invention, a PWM converter is configured only with a counter and a gate element, so that the conventionally used IC for a digital comparator becomes unnecessary. Moreover, the gate element used in the present invention is much smaller than conventionally used digital comparator ICs. Therefore, the overall structure of the present invention is simple and compact.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an asynchronous PWM converter of the present invention,
Figure 2 is an explanatory diagram of the operation of this asynchronous PWM converter, Figure 3
Figure 4 is a block diagram showing the synchronous PWM converter of the present invention, Figure 4 is an explanatory diagram of the operation of the synchronous PWM converter of B, Figure 5 is a block diagram showing the conventional asynchronous PWM converter, and Figure 6 7 is a block diagram showing a conventional synchronous PWM converter, and FIG. 7 is an explanatory diagram of the operation of the conventional technique. In the drawing, 100, 101 and 102 are binary counters with presets, 103 is a complement calculator, 104 is a Nant gate, 105 is a delay circuit, 106 is an inverter, 107 is an RS flip-flop, and 200, 201 and 202 are synchronous binaries with presets. Counter, 203 is a complement calculator, 204 is an inverter, 205 is an AND gate, 206.208 is a D flip-flop, 207.209
is a Nant gate, M is parallel digital data, and Ml is the complement parallel digital data.

Claims (1)

[Claims] In a PWM converter that outputs a PWM pulse corresponding to parallel digital data by inputting a reference clock and parallel digital data as a command value, when the parallel digital data is input, the a complement calculator that outputs complement parallel digital data that is a numerical value, and when a load pulse is input, loads the complement parallel digital data and sets this value as a preset value, and also converts the preset value from the preset value in synchronization with a reference clock. A binary counter with a preset that counts up and is cleared by a clear pulse input at regular intervals, an inverter that inverts the highest output of the binary counter with a preset and outputs it as a PWM pulse, and a PWM pulse that is high. After the level changes to low level until the next clear pulse is input to the binary counter with preset, there is a stop section that stops the count-up operation of the binary counter with preset, and a clear pulse is input to the binary counter with preset. A PWM converter comprising: a load pulse generator that sends a load pulse to a binary counter with a preset immediately after the load pulse is generated.