JPS6236407B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse train generation circuit required for data transfer between a processing device and a terminal device in an electronic computer or the like.

Conventionally, when you want to transfer data from a processing device to a terminal device and perform an output operation, the processing device first issues a request to the terminal device to transfer the data, and if the terminal device is ready for this request, Issue a permission signal. Then, using this permission signal as a trigger signal, the pulse train generation circuit is operated, and the data of the number of bits that the terminal device can receive,
If both the clocks are transferred from the processing device to the terminal device, the terminal device can receive data in synchronization with the clock. FIG. 1 explains the outline of data transfer between the two devices. First, a transfer request signal a is applied from the data processing device 1 to the terminal device 2. As shown in FIG. In response to this, when the permission signal b is issued from the terminal device 2, the data signal c is transferred from the processing device 1 to the terminal device 2 in synchronization with the clock CP.

The present invention is a circuit for generating data signals and clocks having a fixed period and number of clocks as described above, and one embodiment will be described below with reference to the drawings. Second
In the figure, OS1 and OS2 are two one-shot flip-flops connected in cascade, and the first stage flip-flop OS1 has two input terminals A1,
B1 and the set output terminal Q1, and the flip-flop OS2 in the latter stage is connected to the output terminal Q1 of the OS1.
The trigger signal Po is input to the input terminal A1 of the first-stage flip-flop OS1, and the trigger signal Po is input to the input terminal A1 of the first-stage flip-flop OS1. Each set output terminal Q
1 and Q2, a first pulse train P1 and a second pulse train P2, each having a predetermined pulse width, are output. Further, the reset output Q2 of the second-stage flip-flop OS2 is applied to the input terminal B1 of the first-stage flip-flop OS1 to reset it.

C is the first stage one-shot flip-flop OS
1 output Q1 is input and the number of outputs is counted n
The forward counter is reset by the first trigger signal P0, and when the count reaches n, it outputs an output to the output terminal N, and this signal resets the first stage flip-flop OS1. Figure 3 shows a circuit example of a one-shot flip-flop OS.
FF is a monostable flip-flop with input terminal 1 and generates a set output Q and a reset output.

2 is an inverter that inverts the signal from input terminal A; 3 is an AND gate having two inputs: the inverted output of the signal from input terminal A and the signal from input terminal B; and Rd is a reset terminal. A one-shot flip-flop with such a configuration is configured such that when the terminal B input signal is "1" and the terminal A input signal changes from "1" to "0", and when the terminal A input signal is "0" When the terminal B input signal changes from "0" to "1", a set output Q is generated.The signal "0" corresponds to "Low" and "1" corresponds to "High".

Next, the operation of the circuit having the above configuration will be explained using FIG. When the trigger pulse P0 is now input to the input terminal A1 of the one-shot flip-flop OS1, this signal P0 resets the contents of the counter C to zero, and also sets the one-shot flip-flop OS1 at its falling edge. After this set state is maintained for a certain period of time, it automatically returns to the reset state. The one-shot flip-flop OS2 at the next stage is set by the falling signal of the set output Q1.

This set state is also maintained for a preset time and then automatically returns to the reset state.

The reset output 2 of the one-shot flip-flop OS2 in the second stage is applied to the input terminal B1 of the one-shot flip-flop OS1 in the first stage, and this flip-flop OS1 is set again. In this way, the two one-shot flip-flops OS1 and OS2 are repeatedly set and reset, and generate pulse trains from the output terminals P1 and P2, respectively.

When the contents of the counter C reach n, an output N is generated, and this signal resets the one-shot flip-flop OS1 and stops the pulse generation operation. That is, the pulse train outputs P1 and P2 each having a predetermined pulse width have a period set in advance by the respective flip-flops OS1 and OS2, and generate a number of pulses determined by the counter C.

When the above pulses are applied to the example shown in FIG. 1, pulse train P1 of the two types of pulse trains is used as a data clock pulse in the processing device,
The other pulse train P2 can be used as a clock pulse for reception synchronization. In the above embodiment, the output N of the counter C is directly applied to the reset terminal Rd of the one-shot flip-flop OS1, but if a binary counter is used as the counter, the output N of the counter C is inputted to the decoder once and then
After converting into a base number, the output can be input to the reset terminal of the first stage flip-flop. moreover,
In the above embodiment, two pulse trains are output, but by increasing the number of one-shot flip-flops and taking out the output from each set output terminal, it is possible to increase the number of pulse trains in accordance with the number of flip-flops. Needless to say.

FIG. 5 shows a specific example of a pulse train generation circuit which is a feature of the present invention. In the figure, there are a plurality of trigger signals, for example three, P01, P02, and P03, and the number of pulses in each pulse train is made different depending on the respective trigger signals.

The following will be explained using FIG. 5. Reference numeral 4 denotes an OR gate to which three types of trigger signals P01, P02, and P03 are input, and the output of this OR gate 4 is the same as that of the first stage of the one-shot flip-flop in the previous embodiment.
Input to input terminal A1 of OS1. D is a decoder that decodes the binary signal of counter C into a decimal number, and generates three different count values L, M, and N.
emits an output corresponding to the For example, the decoder D is the 4LINE-T0-16 manufactured by TI, announced in 1972.
-LINE DECODERS “SN74154” (detailed in TI Bipolar Digital IC Databook) is used. This is because the output of a 4-bit binary counter is input, and among the 16 output terminals numbered 0 to 15, only the output terminal corresponding to the input value is at the "Low" level, unlike the others at "Hi" level. For example, the count value L=3, M=8, N=11
If so, each output signal line connected to the output terminals numbered 3, 8, and 11 will send out the output L, M, and N signals, respectively. FF1, FF2, and FF3 are flip-flops that are set by trigger signals P01, P02, and P03, respectively, and a reset signal is input all at once from terminal 5. Reference numerals 6, 7, and 8 designate AND gates that take the set outputs of these flip-flops FF1, FF2, and FF3 as one input, and take the output L, M, and N signals of the decoder D as the other inputs, and 9 designate these AND gates 6, 7, and This is an OR gate that takes the output of 8 as an input, and its output is input to the reset terminal Rd of the one-shot flip-flop OS1. The other configurations are the same as those of the previous embodiment.

With this configuration, when the trigger signal P01 is input, the flip-flop FF1 enters the set state, so each one-shot flip-flop OS
1, OS2...When the number of output pulses from OSn reaches L, the decoder D outputs an L signal, opens the AND gate 6, and adds a signal to the reset terminal Rd of the first-stage one-shot flip-flop OS1. Reset.

Therefore, pulse generation stops. Trigger signal P
Similarly, when inputting 02, P03,
Each output pulse train has M or N pulses.
When the number of pulses reaches 1, pulse generation stops. In this way, it is possible to obtain a desired number of pulses by switching the trigger signals P01, P02, and P03.

As explained above, the pulse train generating circuit of the present invention uses only a plurality of one-shot flip-flops connected in cascade, a counter, a decoder, and a one-shot flip-flop, and can generate a pulse train at a desired period. Not only can a pulse train of a desired pulse width be obtained, but also the number of pulses in this pulse train can be set in a plurality of ways, making it possible to selectively obtain a desired number of pulses. Therefore, it is possible to obtain a highly versatile pulse train generation circuit that is optimal for exchanging data between a processing device and a terminal device in an electronic computer or the like.

In addition, the circuit configuration is simple and flip-flop,
Since it uses a circuit that can be easily integrated into an integrated circuit, such as a counter, the cost can be kept low, and it has a great practical effect when incorporated into an electronic computer or the like.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one usage state of a pulse train generated by a pulse train generation circuit according to the present invention, and FIG.
3 is a block diagram of the same circuit, FIG. 4 is a signal waveform diagram for explaining the operation of the circuit, and FIG. 5 is a block diagram of a concrete example of the pulse train generation circuit of the present invention. It is a diagram. 1... Processing device, 2... Terminal device, OS1, OS
2...OSn...One-shot flip-flop, C
...Counter, D...Decoder.

Claims (1)

[Scope of Claims] 1. A pulse train having a predetermined pulse width determined for each one-shot flip-flop can be extracted from the set output terminal of each one-shot flip-flop whose input and output terminals are connected in cascade.
One-shot flip-flop is one in which a trigger signal is input from the input terminal of the first-stage flip-flop, and the first-stage flip-flop is set at the output of the last-stage flip-flop. and a counter that counts the applied signal and generates an output when the counted value reaches a predetermined value, and resets the first stage flip-flop with the output of the counter, the output of the counter is A decoder is provided which generates an output corresponding to each set value when the count content reaches one of a plurality of set values depending on the type of trigger signal inputted to the first stage one-shot flip-flop. 1. A pulse train generating circuit characterized in that a first stage one-shot flip-flop is reset by a specific output of said decoder corresponding to a trigger signal.