JPH0419853Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pulse train generation circuit whose pulse period decreases exponentially with time.

[Prior Art] A pulse pattern is a predetermined number of pulse trains generated according to a certain waveform rule, and the number of pulses is
There are combination patterns of width, spacing, rising (falling) point, etc. A special pulse pattern is one in which the pulse period increases exponentially with time.

As a circuit that generates such a pulse pattern, see "Patent Pulse Circuit Technology Encyclopedia" edited by Suzuki and Higuchi.
(May 20, 1980, 1st edition, 1st printing, published by Ohmsha Co., Ltd.) The pulse train generating circuit described on page 327 is publicly known.

This will be explained with reference to FIGS. 5 and 6.

1 is a decimal counter circuit in which a plurality of decimal counters 21, 22...2n are continuously connected, and when a pulse of a certain period is input, the decimal counter 2 of each stage is
The output of 1, 22...2n has an input pulse ei of 10 ¹ ,
10 ² ...obtained every time 10 ⁿ pieces are reached.

31, 32...3n are a group of monostable multivibrators driven by the outputs of the decimal counters 21, 22...2n at each stage.

41, 42...4n is the combination of the above input pulse ei and the monostable multivibrator 31, 32...3n.
This is the first AND circuit group that takes out an AND (logical product) output.

50, 51...5n are the second AND (logical product) outputs of the first AND circuit group 41, 42...4n and the outputs T0, T1...Tn of the (n+1)-adic ring counter circuit 7. This is a group of AND circuits.
6 is this second AND circuit group 50, 51...5n
This is an OR circuit 6 that takes out the OR (logical sum) output of .

Next, the operation will be briefly explained.

In the initial state, 10 of each stage of decimal counter circuit 1
Outputs 10 ¹ , 10 ² ... of decimal counters 21, 22...2n
...10 ⁿ are all reset to [0], and (n
+1) In the leading ring counter circuit 7, only the output T0 is set to [1].

When the first pulse ¹⁰⁰ (input pulse ei) is input, this pulse passes through the second AND circuit 50 and OR circuit 6, and becomes the first output pulse (output pulse
eo). With this first output pulse (n+1)
The forward ring counter circuit 7 advances by one, and only the output T1 becomes [1].

The input pulses ei arrive one after another, and when ^{the 10th} pulse enters, the decimal counter 21 generates an output,
The monostable multivibrator 31 is driven.

The output of this monostable multivibrator 31 is
The AND circuit 41 is opened for one input pulse period, and the 11th pulse of the input pulse ei applied to the other end is
It is extracted as an output pulse. This pulse is
Output pulse passes through AND circuit 51 and OR circuit 6
eo, and the (n+1)-adic ring counter circuit 7 is incremented by one.

This kind of operation is performed by the decimal counters 21, 22...
2n one after another, and input pulses ei of 1,
10 ¹ +1, 10 ² +1...th pulse is output.

Note that the intervals between the input pulses ei are constant in the pulse train, but for convenience, in FIG. 2, the number of input pulses ei is shown on a logarithmic scale. It has become constant.

[Problems to be solved by the invention] Conventional technology uses various counter circuits, logic circuits,
etc., making the circuit configuration complicated. Also,
The accuracy of the pulse pattern is dependent on the accuracy of the capacitor of the monostable multivibrator, so the accuracy is poor and it is not suitable for integrated circuits.

[Means for Solving the Problems] The present invention includes a clock pulse generation circuit 8 that generates clock pulses, and (b) shifts input data from the least significant bit (LSB) to the upper digits for each clock pulse. , its contents [O _o+1 OnO _o-1
...O ₂ O ₁ ] and outputs the bit with the largest digit.
A shift register circuit 9 that uses MSB (most significant bit) [O _o+1 ] as a reset signal, and (c) the above MSB of the shift register circuit 9.
The content [On O _o-1 …O ₂ O ₁ ] excluding [O _o+1 ] is input to preset inputs P1, P2…P _o-1 and Pn, respectively, and the corresponding preset value [O ₁ O ₂ … …O _o-1
a programmable counter circuit 11 that counts the clock pulses with the initial value set to [QnQ _o-1 ...Q2 Q1] and outputs a carry signal when the content [QnQ o-1...Q2 Q1] reaches a full count value; The content of the shift register circuit 9 is extracted by the carry signal as an output pulse whose pulse period decreases exponentially with time [O _o+1 OnO _o-1 ...O ₂ O ₁ ]
and MSB of the shifted contents
The present invention is characterized in that the programmable counter circuit 11 is preset with the contents [On O _{o-1 .} . . O ₂ O ₁ ] excluding [O o+1 ].

[Operation] (1) In the initial state, the contents of the shift register circuit 9 [O _o+1 On O _o-1 ...O ₂ O ₁ ] are [000...
00], and its output On O _o-1 …O ₂ O ₁ contains the most significant bit MSB (most significant bit MSB).
bit) excluding [OnO _o-1 …O ₂ O ₁ ] ([00…
00]) is output.

(2) The output of this shift register circuit 9 [OnO _o-1
...O ₂ O ₁ ] ([00...00]) are the preset inputs P1, P2... of the programmable counter circuit 11.
Each is input to P _o-1 and Pn. That is,
Preset inputs Pn, P _o-1 ... P2, P1 are the outputs of the shift register circuit 9 [OnO _o-1 ... O ₂
The preset value [O ₁ O ₂ ...O _o-1 On] is input in order from the LSB of O ₁ ], intersecting each other.
becomes [00…00].

This programmable counter circuit 11 counts the clock pulse fc using its preset value [00...00] as an initial value, and its contents [QnQ _o-1 ...Q2 Q1] are [00...00] [00... …01] 〓 Changes like [11…10].

Then, when the clock pulse fc is counted ²ⁿ times and reaches the full count value [11...11], the carry signal CA is output. That is,
Period ²ⁿ corresponding to ²ⁿ of the above clock pulses fc
An output pulse with T is obtained.

(3) This output pulse is transferred to the shift register circuit 9
input to the clock input 9a. By this clock input (output pulse), the shift register circuit 9 changes its contents [O _o+1 On O _o-1 ...O ₂ O ₁ ]
([000…00]) is shifted and becomes [000…00].

Of the outputs of this shift register circuit 9,
Output excluding MBS [OnO _o-1 …O ₂ O ₁ ] ([00…
01]) are input to the preset inputs P1, P2...P _o-1 and Pn of the programmable counter circuit 11, respectively, and the preset values [O ₁ O ₂ ... O _o-1
On] becomes [10...00].

This programmable counter circuit 11 counts the clock pulse fc using its preset value [10...00] as an initial value, and the contents [Qn Q _o-1 ...Q2 Q1] are [10...00] [10... …01] [10…11] 〓 Changes like [11…10].

Then, when the clock pulse fc is counted 2n ^-1 times and reaches the full count value [11...11], the carry signal CA is output. That is, an output pulse having a period of 2 ^{n- 1 T corresponding to 2 n-1} clock pulses fc is obtained.

(4) Hereafter, repeat the same operation to obtain the contents of the shift register circuit 9 [O _o+1 OnO _o-1 ……O ₂
O ₁ ] changes as [000......11] [000...111] 〓 [011...111], and the preset value of the programmable counter circuit 11 is [10...00] [11... 00] 〓 [111...10] Therefore, the count number decreases sequentially as 2 ⁿ , 2 ^n-1 ... 2 ² , 2 ¹ , 2 ⁰ , and corresponds to the count number. Output pulses are output at the specified period.

That is, pulse trains 2 ⁿ T, 2 ^n-1 T...2 ² T, 2 ¹ T, 2 ⁰ T whose pulse periods decrease exponentially with time are obtained.

(5) Repeat the above operation to change the contents of the shift register circuit 9 [O _o+1 OnO _o-1 ...O ₂ O ₁ ] from [011...11] to [111...11] A reset signal is output at the moment when the MSB [O _o+1 ] becomes [1],
As a result, the shift register circuit 9 is reset and returns to its initial state.

Thereafter, the same operation is repeated.

[Embodiments] [First Embodiment] FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention, and FIG. 2 is a signal waveform diagram of the same.

This will be explained below with reference to the figures.

8 is a clock pulse generation circuit that generates a clock pulse fc.

9 is a shift register circuit having a data input 9a and a clock input 9b;
is fixed at high level [1]. This shift register circuit 9 shifts the data input [1] from the initial value [00...0] from the least significant bit (LSB) to the upper digit for each clock input, and the contents [ O _o+1 OnO _o-1 …
...O ₂ O ₁ ] is output from O _o+1 On O _o-1 ...O ₂ O ₁ .

Also, the largest bit MSB (most
significant bit) [O _o+1 ] is inverted by the first inverter circuit 10 and then input as a reset signal to the reset input 9c.

11 are preset inputs P1, P2...P _o-1 , Pn,
and a programmable counter circuit comprising a clock input 11a to which the clock pulse fc is input.

These preset inputs P1, P2...P _o-1 , Pn are connected to the output [O _o+1 On
...O ₂ O ₁ ], excluding MBS [On...
O ₂ O ₁ ] are respectively input. That is, the preset inputs Pn, P _o-1 ... P2, P1 have the LSB of the output [OnO _o-1 ... O ₂ O ₁ ] of the shift register circuit 9 described above.
They are preset sequentially, that is, in an intersecting manner, and the preset value becomes [O ₁ O ₂ . . . O _o-1 On].

The grammable counter circuit 11 up-counts the clock pulse fc using the preset value [O ₁ O ₂ ...O _o-1 On] as the initial value, and the contents [QnQ _o-1 ...Q2Q1] become the full count value [11 ... …11]
At the point in time, the carry signal CA is output from the carry output 11b.

This carry signal CA is inputted to the load input 11c via the second inverter circuit 12, and this inverted carry signal CA is applied to the clock pulse fc.
It is also input to the NOR circuit 13.

Then, the NOR output of this NOR circuit 13 is inputted to the clock input 9a of the shift register circuit 9, and the NOR output is taken out from the first output terminal 14 as a pulse train whose pulse period decreases exponentially with time. .

Hereinafter, the shift register circuit 9 is a 5-bit shift register and a programmable counter circuit 1.
The operation of a specific example in which 1 is constituted by a 4-bit counter will be explained.

In this specific example, a pulse train whose pulse period decreases exponentially with time 2 ⁴ T, 2 ³ T, 2 ² T, 2 ¹ T, 2 ⁰ T (T is a period 1/1 corresponding to one period of the clock pulse fc) is used. fc) is obtained.

(1) In the initial state, the contents of the shift register circuit 9 [O5 O4 O3 O ₂ O ₁ ] are [00000],
The contents [O4 O3 O ₂ O ₁ ] ([0000]) excluding the MSB are output to the outputs O4, O3, O ₂ , and O ₁ .

(2) The output of this shift register circuit 9 [O4 O3
O ₂ O ₁ ] ([0000]) are input to preset inputs P1, P2, P3, and P4 of the programmable counter circuit 11, respectively. That is, the preset value [O ₁ O ₂ O 3 O 4] becomes [0000].

This programmable counter circuit 11 counts the clock pulse fc with its preset value [0000] as the initial value, and its contents [QnQ _o-1 ...Q2Q1] change as follows: [0000] [0001] 〓 [1110] do. Then, when the clock pulse fc is counted ²⁴ (16) times and reaches the full count value [1111], the carry signal CA is output.

That is, 2 ⁴ (16) of the above clock pulse fc
A first output pulse is obtained with a period 2 ⁴ T corresponding to .

(3) This output pulse is transferred to the shift register circuit 9
input to the clock input 9a. By this clock input (output pulse), the shift register circuit 9 changes its contents [O5 O4 O3 O ₂ O ₁ ]
([00000]) is shifted and becomes [00001].

Among the contents of this shift register circuit 9
Content [0001] excluding MSB is output O4, O3,
This is output from O ₂ and O ₁ , and this is output from the preset inputs P1, P2, and P2 of the programmable counter circuit 11.
Input to P3 and P4 respectively. That is, the preset value [O ₁ O ₂ O 3 O 4] is [1000].

This programmable counter circuit 11 counts the clock pulse fc with its preset value [1000] as the initial value, and its contents [QnQ _o-1 ...Q2 Q1] change as follows: [1000] [1001] 〓 [1110] do. Then, when the clock pulse fc is counted 2 ³ (8) times and reaches the full count value [1111], the carry signal CA is output.

That is, 2 ³ (8) of the above clock pulse fc
A second output pulse is obtained with a period 2 ³ T corresponding to .

(4) Hereafter, repeat the same operation to obtain the contents of the shift register circuit 9 [O5 O4 O3 O ₂ O ₁ ]
changes as [00011] [00111] 〓 [01111], and the preset value [O ₁ O ₂ O3 O4] of the programmable counter circuit 11 changes as [1100] [1110], so . The count number decreases sequentially to 2 ² , 2 ¹ , and 2 ⁰ , and output pulses are output at a period corresponding to the count number.

That is, pulse trains 2 ⁴ T, 2 ³ T, 2 ² T, 2 ¹ T, 2 ⁰ T whose pulse periods decrease exponentially with time are obtained.

(5) Repeat the above operation, and when the contents [O5 O4 O3 O ₂ O ₁ ] of the shift register circuit 9 change from [01111] to [11111], a carry signal is output, and this carry signal is It is input via the first inverter circuit 10 to the reset input 9c. As a result, the shift register circuit 9 is reset and returns to its initial state.

Thereafter, the same operation is repeated.

[Second Embodiment] FIG. 3 is a diagram showing the configuration of a second embodiment of the present invention, and FIG. 4 is a signal waveform diagram of the same.

In the figure, parts equivalent to those in the first embodiment of FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

This will be explained below with reference to the figures.

Reference numeral 11 denotes a programmable counter circuit, which outputs the carry signal CA output from the carry output 11b as an output pulse from the second output terminal 15.

This output pulse is sent to the D-flip-flop circuit 1.
6 to the data input 16a, while inputting the above clock pulse fc to the clock input 16b,
The output pulse is delayed by one cycle of the clock pulse fc, and this delayed pulse is input to the clock input 9b of the shift register circuit 9, and is also passed through the third inverter circuit 17 to the load input 11c of the programmable counter circuit 11.
Enter.

That is, in this embodiment, by delaying the shift of the shift register circuit 9 and the loading of the programmable counter circuit 11 by one period of the clock pulse fc from the output pulse, a pulse train whose pulse period decreases exponentially with time ( 2 ⁴ +1)T, (2 ³ +1)T...(2 ⁰ +1)T are obtained.

In other words, in the pulse train, a pulse train in which the low level time in one cycle decreases exponentially as 2 ⁴ T, 2 ³ T, 2 ² T, 2 ¹ T, and 2 ⁰ T is obtained. It is something.

In addition, the operation of this embodiment is as follows, except for the above points.
This is the same as the first embodiment.

[Effects of the invention] The present invention not only (1) provides a pulse train whose pulse period decreases exponentially with time;
(2) The circuit configuration is simple because it only uses a shift register circuit and a programmable counter circuit. (3) Also, since it does not use a monostable multivibrator unlike conventional technology, the accuracy of the pulse period is high. It also has the effect of being an optimal circuit for integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a first embodiment of the pulse train generation circuit of the present invention, and FIG. 2 is a signal waveform diagram of the same,
FIG. 3 is a diagram showing the configuration of the second embodiment, and FIG.
5 is a diagram showing the configuration of a conventional pulse train generation circuit, and FIG. 6 is a signal waveform diagram of the same. 8... Clock pulse generation circuit, 9... Shift register circuit, 10... First inverter circuit,
11...Programmable counter circuit, 12...
Second inverter circuit, 13...NOR circuit, 1
4...first output terminal, 15...second output terminal, 16...D-flip-flop circuit, 17...
...Third inverter circuit 18.

Claims (1)

[Scope of utility model registration request] A clock pulse generation circuit 8 generates a clock pulse, and the input data is shifted from the smallest bit LSB to the highest digit for each clock pulse, and its contents [O _o+1 On O _o-1 ...O ₂ O ₁ ]
The shift register circuit 9 outputs the bit MSB [O _o+1 ] with the largest digit as a reset signal, and the contents of the shift register circuit 9 excluding the above MSB [O _o+1 ] [On O _{o- 1} …O ₂ O ₁ ] is the preset input
The clock pulses are counted using the preset value [O ₁ O ₂ ... O _o-1 On] as the initial value, and the contents [QnQ _{o-1 ...} A programmable counter circuit 11 outputs a carry signal when Q2 Q1] reaches a full count value, and extracts the carry signal as an output pulse. _o+1 On O _o-1 ... O ₂ O ₁ ] is shifted, and _the content [On
O _o-1 ... O ₂ O ₁ ] is preset in the programmable counter circuit 11.