JPS6126255B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a codec (CODEC) in which the internally generated conversion clock signal frequency is always constant for a plurality of types of external clock signal frequencies. A codec is a combination of a signal encoder (CODEC) and a decoder (DECODER) in a PCM device, etc., and is used in the transmission of PCM signals. That is, analog signals such as audio are sampled at a constant rate and converted into PCM signals of a predetermined number of bits, and vice versa. FIG. 1 is a block diagram showing the structure of a conventional codec. In the figure, reference numeral 1 denotes a divider section which divides the frequency of an external clock signal applied from an external clock signal terminal 2 to generate a converted clock signal. The frequency division ratio in the divider section 1 is controlled by a frequency division ratio control signal given from the control logic section 3. In the control logic section 3, according to the frequency division ratio signal given from the external input pin 4 for frequency division ratio switching, a frequency division ratio control signal is generated so that the frequency division ratio in the divider section 1 becomes a predetermined value. Occur. In the case of an encoder, the D/A converter section 5 converts the analog input signal from the analog data terminal 6 into a digital signal according to the conversion clock signal to create a PCM signal with a predetermined number of bits, and stores it in the register section 7. do. The contents of the register section 7 are output as serial data to a digital data terminal 9 in response to a read clock signal applied from a read/write clock signal terminal 8. The divider section 1 and the register section 7 are returned to the initial state by a synchronization signal applied from a synchronization signal terminal 10 when one encoding is completed. When operating as a decoder, a predetermined number of bits of the PCM signal applied from the digital data terminal 9 is written into the register section 7 in response to a write clock signal applied from the read/write clock signal terminal 8. The contents of the register section 7 are inputted in parallel to the D/A converter section 5, converted in accordance with the conversion clock signal to reproduce an analog signal, and outputted to the analog data terminal 6. The repetition of encoding and decoding in the codec of FIG. 1 is determined by the repetition frequency of the synchronization signal applied from the synchronization signal terminal 10. Further, the clock signal at the external clock signal terminal 2 and the clock signal at the read/write clock signal terminal 8 are normally
The same clock signal is used, and the clock frequency is determined by multiplexing multiple channels of codecs.
Equivalent to the data transfer rate for PCM transmission.
This external clock signal is frequency-divided to create a conversion clock signal necessary for encoding and decoding operations. As described above, in the conventional codec shown in FIG. 1, a conversion clock signal is generated by frequency-dividing an external clock signal. Therefore, if the divider section has a fixed frequency division ratio, it can only be used for a specific external clock frequency, and in order to use it for multiple types of external clock signals, it must be divided by applying a frequency division ratio signal from the outside. The ratio must be determined and used, an external input pin for switching the division ratio is required, and the IC
If the number of pins required for integration is limited, there are design constraints. The present invention attempts to eliminate these drawbacks of the prior art, and its purpose is to provide a codec that is not limited by external clock frequency and does not increase the number of input pins. To achieve this objective, the codec of the present invention divides the frequency of an external clock signal to generate an internal conversion clock signal necessary for encoding and decoding operations. means for counting external clock signals for each synchronization signal; means for determining a frequency division ratio for dividing the external clock signal according to the counted value; and variable frequency division for dividing the external clock signal according to the determined frequency division ratio. The present invention is characterized in that a frequency dividing means is provided to obtain a constant internal conversion clock signal frequency for a plurality of types of external clock signal frequencies. Examples will be described below. FIG. 2 is a block diagram showing the structure of one embodiment of the codec of the present invention. In the figure, reference numeral 2,
The representations of 5, 6, 7, 8, 9, and 10 are the same as in FIG. 11 is a counter section, 1
2 is a control logic section, and 13 is a variable divider section. In FIG. 2, a counter section 11 counts external clock signals applied from an external clock signal terminal. The counter section 11 consists of an N-ary counter and generates a carry signal every N counts of the external clock signal. Further, the counter section 11 is reset by a synchronization signal applied from the synchronization signal terminal 10 and returns to the initial state. In this way, the counter section 11 generates a carry signal every N counts of the external clock signal during one period of the synchronization signal. The control logic section 12 consists of a counter that counts the carry signal from the counter section 11 and a latch circuit that latches the contents of the counter with a synchronization signal, and is reset and initialized by the synchronization signal from the synchronization signal terminal 10. Upon returning to the state, the latched contents are transferred to the variable divider section 13 as a frequency division ratio control signal. The frequency division ratio control signal transferred from the control logic section 12 to the variable divider section 13 controls the frequency division ratio in the variable divider section 13.
Therefore, if the carry signal input from the counter section 11 to the control logic section 12 is M counts during one period of the synchronization signal, the value M latched by the synchronization signal is variable as the frequency division ratio control signal. The frequency division ratio in the divider section 13 is set to 1/M. The variable divider section 13 consists of a counter-type frequency divider, and a value M determined by the frequency division ratio control signal from the control logic section 12 is set in the counter in synchronization with the synchronization signal. The counter of the variable divider section 13 counts the external clock signal, and every time it reaches a set value M, it overflows and generates a carry signal, that is, a conversion clock signal. When the variable divider section 13 generates the conversion clock signal, the value M is again set by the frequency division ratio control signal from the control logic, and the same operation is repeated. The conversion clock signal generated in this way is a signal obtained by dividing the external clock signal to a desired frequency division ratio, and is supplied to the D/A converter section 5 to perform the required encoding and decoding operations. I can do it. The operations of the D/A converter section 5 and the register section 7 are the same as in the case of FIG. As described above, according to the present invention, even if clocks of various frequencies are input as external clocks, the frequency division ratio M of the variable divider section 13 changes depending on the number of clocks present between the synchronization signals, so the frequency division ratio M is always constant. A frequency conversion clock can be supplied to the D/A converter 5. Table 1 shows the external clock signal as a specific example of the operation of the codec of the present invention.
When a signal with an integral multiple of 128KHz is input, divide the external clock signal and use it as a conversion clock signal.
This is for the case where 128KHz is generated. In Table 1, the synchronizing signal is 8 KHz, a carry signal is output every 16 counts of the external clock signal that enters one cycle, and the value M is set as the total value. For example, if a 128KHz signal is input as an external clock signal, the count value in the counter section 11 will be 16 times during the 8KHz synchronization signal, so M set as the frequency division ratio will be M = 1. Become. Based on this frequency division ratio, the variable divider section
A 128KHz conversion clock signal is generated by dividing the 128KHz external clock by 1/1. Next, if we consider the case where a 256KHz signal is input as an external clock signal, the count value in the counter section 11 will be 32 times, so from the set value M = 2,
The variable divider section divides 256KHz into 1/2.
Generates a 128KHz conversion clock. Similarly, the external clock frequency is 128KHz.
In any case, a conversion clock with a constant frequency can be obtained in any case where an arbitrary frequency that is an integer multiple of is input.

[Table] As explained above, according to the codec of the present invention, multiple types of external clock signals are counted for each synchronization signal indicating repetition of encoding or decoding,
By dividing the frequency of the external clock signal by determining the frequency division ratio based on this count value, a constant conversion clock signal can be generated at all times, thus providing versatility. Furthermore, since there is no need to apply a dividing ratio setting signal from the outside, the number of external connection pins can be reduced, which is advantageous when integrated into an IC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of a conventional codec, and FIG. 2 is a block diagram showing the structure of an embodiment of the codec of the present invention. 1... Divider section, 2... External clock signal terminal, 3... Control logic section, 4... External input pin for frequency division ratio switching, 5... D/A converter section, 6... Analog data terminal, 7...Register section, 8...Read/write clock terminal, 9...Data terminal, 10...Synchronization signal terminal, 11...Counter section, 12...Control logic section, 1
3...Variable divider section.

Claims (1)

[Claims] 1. In a codec that divides an external clock signal to generate an internal conversion clock signal necessary for encoding and decoding operations, means for counting the external clock signal for each synchronization signal indicating repetition of encoding or decoding; , a means for determining a frequency division ratio for dividing an external clock signal based on the counted value, and a variable frequency division means for dividing the frequency of an external clock signal according to the determined frequency division ratio. A codec characterized by obtaining a constant internal conversion clock signal frequency with respect to the signal frequency.