JPH01280924A - Counter circuit having test function - Google Patents

Counter circuit having test function

Info

Publication number
JPH01280924A
JPH01280924A JP63110998A JP11099888A JPH01280924A JP H01280924 A JPH01280924 A JP H01280924A JP 63110998 A JP63110998 A JP 63110998A JP 11099888 A JP11099888 A JP 11099888A JP H01280924 A JPH01280924 A JP H01280924A
Authority
JP
Japan
Prior art keywords
circuit
test
counting
counter circuit
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63110998A
Other languages
Japanese (ja)
Inventor
Minoru Kikuchi
稔 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63110998A priority Critical patent/JPH01280924A/en
Publication of JPH01280924A publication Critical patent/JPH01280924A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318527—Test of counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To reduce the time required for the test of count operation by forming a counter circuit with a few digit numbers equivalently in the test mode while the test mode and the usual count operating mode are switched to a counter circuit comprising D flip-flops without any preset function of data. CONSTITUTION:With a 1st clock CLK give, outputs Q0, Q2 of a counter circuit go to H to start the test of the counter operation. With a 2nd clock CLK given, the outputs Q0, Q2 go to L and outputs Q1, Q3 go to H. With a 3rd clock CLK given, the outputs Q0, Q2 go to also H and since outputs Q0-Q3 go to all H, a check signal CHECK goes to L and the counter circuit switches the operating mode into the usual counter operating mode while taking the operating test to be finished. In the test mode in this way, a hexadecimal counter circuit acts like two tetral counter circuits. Then the counter operation confirming time is reduced more than that acted like the hexadecimal counter circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテスト機能を有する計数回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a counting circuit with a test function.

〔従来の技術〕[Conventional technology]

従来のこの種の計数回路の一例を第５図に、またそのタ
イムチャートを第６図に示す。An example of a conventional counting circuit of this type is shown in FIG. 5, and its time chart is shown in FIG.

計数動作を確認するには、まず最初に、クリア信号ＯＬ
Ｅを“Ｈ”にして全桁の内容を全て“Ｌ　”としてから
計数を始め、全桁の内容が全て“Ｈ”となるまでクロッ
クＣＬＫに応答して計数動作をくり返し、各桁が“Ｈ”
となったら動作確認用のチエツク信号ＣＴ丁σでか“Ｌ
”になるので計数動作が正常に行われていることを確認
するようになっていた。To check the counting operation, first check the clear signal OL.
Start counting by setting E to "H" so that the contents of all digits are "L", and repeat the counting operation in response to the clock CLK until the contents of all digits become "H", and each digit becomes "H". ”
If so, the check signal for operation confirmation CT-σ is “L”.
”, so it was necessary to check that the counting operation was being performed normally.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の計数回路は、計数動作を確認するには、
全桁が“Ｌ　１１から“°Ｈ°゛になるまで計数動作を
繰り返すのを待つ必要があるため、時間がかかるという
欠点がある。To check the counting operation of the conventional counting circuit described above,
It is necessary to wait to repeat the counting operation until all the digits go from "L 11" to "°H°", so there is a drawback that it takes time.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の計数回路は、データのプリセット機能を有せず
、かつ２Ｎ進の計数回路を構成するＮ個のＤ形フリップ
フロップと、 外部から供給されるテスト信号に応答して、前記２Ｎ進
計数回路を２Ｎ＝ｍｆｉを満たすｎ個のｍ進計数回路に
置換するように、 通常動作モードにおける入力から、前記り形フリップフ
ロップの反転出力に切り換えて該り形フリップフロップ
に入力する切換回路と、該切換回路が前置されたＤ形フ
リップフロップの１つ上位の桁のＤ形フリップフロップ
は、前記テスト信号がアクティブのときには前記切換回
路が前置されたＤ形フリップフロップの出力を入力とす
るように動作するゲート回路とを設けたことを特徴とす
る。The counting circuit of the present invention has N D-type flip-flops that do not have a data presetting function and constitute a 2N-ary counting circuit, and a counter circuit that performs the 2N-ary counting circuit in response to a test signal supplied from the outside. a switching circuit that switches from the input in the normal operation mode to the inverted output of the above-mentioned flip-flop and inputs it to the inverted flip-flop so as to replace the circuit with n m-adic counting circuits satisfying 2N=mfi; When the test signal is active, the D-type flip-flop of the next higher digit than the D-type flip-flop that is preceded by the switching circuit receives the output of the D-type flip-flop that is preceded by the switching circuit. The present invention is characterized in that it is provided with a gate circuit that operates as follows.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第１の実施例であり、第２図はそのと
きのタイムチャートである。FIG. 1 shows a first embodiment of the present invention, and FIG. 2 is a time chart at that time.

１はプリセット機能のないＤ形フリップフロップ、２は
ＡＮＤ回路、３は排他的論理和回路（以下ＥＸ−ＯＲ回
路と記す）、４はインバータ、５はＮＡＮＤＡＮＤ回路
切換回路、１７はＯＲ回路である。1 is a D-type flip-flop without a preset function, 2 is an AND circuit, 3 is an exclusive OR circuit (hereinafter referred to as an EX-OR circuit), 4 is an inverter, 5 is a NAND AND circuit switching circuit, and 17 is an OR circuit. .

４つのＤ形フリップフロップ１は１６進カウンタを構成
していること、また全桁が“Ｈ＋＋になるとチエツク信
号σＷ「σＴが“Ｌ　”となることは第５図と同様であ
る。特徴的なことは、テスト信号ＴＥＳＴを外部から供
給して、最上位桁から１桁下の桁のＤ形フリップフロッ
プへの入力を切換回路６を介して行なっていること及び
最上位桁への入力をＯＲ回路１７を介して行なっている
ことである。The four D-type flip-flops 1 constitute a hexadecimal counter, and when all digits become "H++", the check signal σW and σT become "L", as in FIG. 5.Characteristic This means that the test signal TEST is supplied from the outside and input to the D-type flip-flops of the digit one digit below the most significant digit via the switching circuit 6, and that the input to the most significant digit is ORed. This is done via the circuit 17.

切換回路６は、テスト信号手ＴＥＳＴが“Ｈ”のときに
はｒｌ”Ｌ”のときには直上のＥＸ−ＯＲ回路の出力を
それぞれ受は入れる。また、ＯＲ回路１７と直前のＡＮ
Ｄ回路は、テスト信号ＴＥＳＴが“Ｈ”のときにはＱ２
１　　“Ｌ”のときにはＱＯ，Ｑｌ及びＱｌの論理積を
それぞれ受は入れる。The switching circuit 6 receives the output of the EX-OR circuit directly above it when the test signal TEST is "H" and rl is "L". Also, the OR circuit 17 and the immediately preceding AN
The D circuit outputs Q2 when the test signal TEST is “H”.
1 When "L", the logical product of QO, Ql, and Ql is accepted.

計数動作をテストする際、まず最初にクリア信号ＯＬＥ
を“Ｈ″にし、各桁のデータの内容をＬ”にする。そし
て計数動作のテストモードに入るためのテスト信号ＴＥ
ＳＴを、計数動作テストの間、“Ｈ”にする。When testing the counting operation, first the clear signal OLE
is set to "H", and the data content of each digit is set to "L".Then, the test signal TE is set to enter the test mode of counting operation.
ST is set to "H" during the counting operation test.

この状態で、１つ目のクロックＣＬＫが入力されると計
数回路の出力Ｑｏ　、Ｑｌは　“Ｈｏｏ　となり、計数
動作のテストを開始する。２つ目のクロックＣＬＫが入
力すると、前述のＱＯ，Ｑｌが“Ｌ”となり、Ｑｌ、Ｑ
３が“Ｈ”となる、そして、３つ目のクロックＣＬＫが
入力すると、ＱＯ，Ｑｌも“Ｈ”となり計数回路の出力
Ｑ。〜Ｑ３の出力が全て“Ｈ”となるのでチエツク信号
ＣＷｒｒでは“Ｌ”となり、計数回路は動作テストを終
了とし、動作モードを通常の計数動作モードに切り換え
る。In this state, when the first clock CLK is input, the outputs Qo and Ql of the counting circuit become "Hoo", and a counting operation test is started. When the second clock CLK is input, the outputs Qo and Ql of the counting circuit become "Hoo", and a test of the counting operation is started. becomes “L”, Ql, Q
3 becomes "H" and when the third clock CLK is input, QO and Ql also become "H" and the output Q of the counting circuit. Since the outputs of Q3 are all "H", the check signal CWrr becomes "L", and the counting circuit completes the operation test and switches the operation mode to the normal counting operation mode.

このように、テストモードに入ると、１６進計数回路が
４進計数回路が２個あるように動作するため、計数動作
確認時間が１６進計数回路として動作する時と比べて短
縮できる。In this manner, when the test mode is entered, the hexadecimal counting circuit operates as if there were two quaternary counting circuits, so that the counting operation confirmation time can be shortened compared to when the hexadecimal counting circuit operates as a hexadecimal counting circuit.

第３図は本発明の第２の実施例の回路図であり、第４図
はそのタイムチャートである。FIG. 3 is a circuit diagram of a second embodiment of the present invention, and FIG. 4 is a time chart thereof.

７はデータプリセット機能のないＤ形フリップフロップ
、８はＡＮＤ回路、９はＥＸ−ＯＲ回路、ｉｏはインバ
ータ、１１はＮＡＮＤＡＮＤ回路は切換回路、１８はＯ
Ｒ回路である。7 is a D-type flip-flop without data preset function, 8 is an AND circuit, 9 is an EX-OR circuit, io is an inverter, 11 is a NAND AND circuit is a switching circuit, 18 is an O
This is an R circuit.

第１図に示した第１の実施例が４つのＤ形フリップフロ
ップによって１６進カウンタを構成したのに対し、本実
施例は６つのＤ形フリップフロップで６４進カウンタを
構成している。In the first embodiment shown in FIG. 1, a hexadecimal counter is formed by four D-type flip-flops, whereas in this embodiment, a 64-decimal counter is formed by six D-type flip-flops.

計数動作をテストする際、まず最初にクリア信号ＣＬＥ
を“Ｈ”にし、各桁のデータの内容を“’　Ｌ　”にす
る。そして計数動作のテストモードに入るためのテスト
信号ＴＥＳＴを計数動作確認の間、ＩＩ　Ｈ１１にする
。When testing the counting operation, first the clear signal CLE
is set to "H", and the data content of each digit is set to "'L". Then, the test signal TEST for entering the counting operation test mode is set to II H11 during counting operation confirmation.

この状態で、１つ目のクロックＣＬＫが入力されると計
数回路の出力Ｑｏ　、Ｑ２　、Ｑ４のデータの内容が“
Ｈ１１となり、計数動作のテストを開始する。２つ目の
クロックＣＬＫが入力すると、前述のＱｏ　、Ｑ２　、
Ｑ４が１１　Ｌ　ｎとなり、ＱｌｌＱ３．Ｑ５が“Ｈ１
１となる。そして３つ目のクロックＣＬＫが入力すると
、Ｑｏ　、　Ｑ２　、　Ｑ４　　もｔｔ　ＨＩＩとなり
、計数回路の出力が全て“Ｈ′″となるのでチエツク信
号σπτｍは“Ｌ”となり、計数回路の動作テストを終
了とし、動作モードを通常の計数動作モードに切り換え
る。In this state, when the first clock CLK is input, the data contents of the outputs Qo, Q2, and Q4 of the counting circuit change to “
At H11, a counting operation test is started. When the second clock CLK is input, the above-mentioned Qo, Q2,
Q4 becomes 11 L n, and QllQ3. Q5 is “H1”
It becomes 1. When the third clock CLK is input, Qo, Q2, and Q4 also become tt HII, and the outputs of the counting circuit all become "H'", so the check signal σπτm becomes "L", and the operation test of the counting circuit ends. Then, the operation mode is switched to the normal counting operation mode.

このように、テストモードに入ると、６４進計数回路が
４進計数回路が３個あるように動作するため、計数動作
確認の時間が６４進計数回路として動作する時と比べて
短縮できる。In this way, when entering the test mode, the 64-base counting circuit operates as if there were three 4-base counting circuits, so the time required to check the counting operation can be reduced compared to when the 64-base counting circuit operates as a 64-base counting circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、データのプリセット機能
を有しないＤ形フリップフロップにより構成される計数
回路に、テストモードと通常の計数動作モードとを切り
換えてテストモード時には等価的に少ない桁数の計数回
路を構成することにより、計数動作のテストにかかる時
間を短縮できる効果がある。As explained above, the present invention has a counting circuit constituted by a D-type flip-flop that does not have a data presetting function, by switching between a test mode and a normal counting operation mode, and in the test mode, the number of digits is equivalently reduced. By configuring the counting circuit, it is possible to reduce the time required to test the counting operation.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第３図は本発明の第１の実施例、第２の実施例
をそれぞれを示す回路図、第２図、第４図はこれらの実
施例のタイムチャート、第５図は従来例の回路図、第６
図はそのタイムチャートである。 １．７．１３・・・Ｄ形フリップフロップ、２，８゜１
４・・・ＡＮＤ回路、３．９．１５・・・排他的論理和
回路（ＥＸ−ＯＲ回路）、４．１０・・・インバータ、
５．１１．１６・・・ＮＡＮＤ回路、６．１２・・・切
換回路、１７．１８・・・ＯＲ回路。1 and 3 are circuit diagrams showing a first embodiment and a second embodiment of the present invention, respectively, FIGS. 2 and 4 are time charts of these embodiments, and FIG. 5 is a conventional circuit diagram. Example circuit diagram, 6th
The figure is the time chart. 1.7.13...D type flip-flop, 2.8°1
4...AND circuit, 3.9.15...Exclusive OR circuit (EX-OR circuit), 4.10...Inverter,
5.11.16...NAND circuit, 6.12...Switching circuit, 17.18...OR circuit.

Claims (1)

【特許請求の範囲】 データのプリセット機能を有せず、かつ２＾Ｎ進の計数
回路を構成するＮ個のＤ形フリップフロップと、 外部から供給されるテスト信号に応答して、前記２＾Ｎ
進計数回路を２＾Ｎ＝ｍ＾ｎを満たすｎ個のｍ進計数回
路に置換するように、 通常動作モードにおける入力から、前記Ｄ形フリップフ
ロップの反転出力に切り換えて該Ｄ形フリップフロップ
に入力する切換回路と、 該切換回路が前置されたＤ形フリップフロップの１つ上
位の桁のＤ形フリップフロップは、前記テスト信号がア
クティブのときには前記切換回路が前置されたＤ形フリ
ップフロップの出力を入力とするように動作するゲート
回路とを設けたことを特徴とするテスト機能を有する計
数回路。 但し、ｍ、ｎは整数でｍ≧４である。[Claims] N D-type flip-flops that do not have a data presetting function and constitute a 2^N counting circuit; N
In order to replace the base counting circuit with n m-base counting circuits satisfying 2^N=m^n, the input in the normal operation mode is switched to the inverted output of the D-type flip-flop, and the D-type flip-flop is When the test signal is active, the input switching circuit and the D-type flip-flop in the next higher order of the D-type flip-flop with the switching circuit in front of the D-type flip-flop with the switching circuit in front of the D-type flip-flop are 1. A counting circuit having a test function, comprising: a gate circuit that operates so as to receive the output of the circuit as an input. However, m and n are integers and m≧4.
JP63110998A 1988-05-06 1988-05-06 Counter circuit having test function Pending JPH01280924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63110998A JPH01280924A (en) 1988-05-06 1988-05-06 Counter circuit having test function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63110998A JPH01280924A (en) 1988-05-06 1988-05-06 Counter circuit having test function

Publications (1)

Publication Number Publication Date
JPH01280924A true JPH01280924A (en) 1989-11-13

Family

ID=14549810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63110998A Pending JPH01280924A (en) 1988-05-06 1988-05-06 Counter circuit having test function

Country Status (1)

Country Link
JP (1) JPH01280924A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7289591B2 (en) * 2004-12-06 2007-10-30 Hynix Semiconductor Inc. Counter circuit for controlling off-chip driver
CN102346205A (en) * 2010-07-23 2012-02-08 飞兆半导体公司 No pin test mode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7289591B2 (en) * 2004-12-06 2007-10-30 Hynix Semiconductor Inc. Counter circuit for controlling off-chip driver
CN102346205A (en) * 2010-07-23 2012-02-08 飞兆半导体公司 No pin test mode
US8829932B2 (en) 2010-07-23 2014-09-09 Fairchild Semiconductor Corporation No pin test mode

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