JPH0467810B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention uses a single clock and can perform a counting operation that is 1 times the input clock, 1.5 times the counting operation, and 2 times the input clock with a single clock offset. The present invention relates to a binary counter that can be easily switched.

Conventional configuration and its problems Conventionally, this type of binary counter has been configured as shown in FIG. 1 has an input terminal, 3 has a reset terminal 13 and a set terminal 14, and divides the clock signal from input terminal 1 by 1/2.
A frequency divider (13 is the reset terminal, 14 is the set terminal) and gates 10 and 11 create a two-phase clock (half the frequency) from the clock signal 1, one for each unit stage of 4 to 8 flip-flops. is connected to the clock input terminal of the flip-flop 4 at the first stage of the binary counter 9 connected in cascade, and the other one is connected to an EX-NOR gate 12 which takes this as the first input and the output of the gate 11 as the second input. 2 from the lowest side of the binary counter through
It is connected to the clock input terminal of the flip-flop 5 in the second stage.

The conventional binary counter configured as described above will be explained with reference to the time charts shown in FIGS. 2 and 3. 1a, 3Q, 10
a, 11a, 12a are clock signal input terminals;
1/2 frequency divider 3, AND gate 10, 11EX-NOR
These are the waveforms of each output signal of the gate 12. Figure 2 shows
In the time chart when the 1/2 frequency divider 3 is in the reset state, the binary counter 9 is counting the clock input signal by 1 with a single active edge. On the other hand, FIG. 3 is a time chart when the 1/2 frequency divider 3 is neither set nor reset. AND gate 10,
The output of 11 is the pulse of the clock input signal 1a,
A signal with a phase difference of 180°, which is missing every other signal (half the frequency), is output, and the output of the AND gate 10 becomes the clock input of the flip-flop 4 in the first stage of the binary counter 9, while the output of the gate 11 is the non-inverting output of the flip-flop 4. When it is at a high level, it appears at the output of the inverting output gate 12, and when it is at a low level, it appears at the output of the non-inverting output gate 12. That is, during two periods of the original clock input signal, the clock signal is input once each to the flip-flop 4 at the lowest level of the binary counter 9 and the flip-flop 5 at the second stage from the lowest level, and the binary counter 9 receives the clock signal. This means that 3 counts were performed during 2 cycles. In other words, the count is 1.5 times the original clock signal.

However, in the above configuration,
Depending on the output state of the first-stage flip-flop 4 of the binary counter 9, the active edge of the second-stage clock input changes and matches the active edge of the original clock input (when 4Q is at low level, time _t7 ); There is a time when they do not match (when 4Q is at a high level, time t ₄ ), and when this counter output is decoded to perform the next series of operations, various problems occur.

The above problem is the same when the 1/2 frequency divider 3 in FIG. Depending on the output state of No. 4, the active edge of the second stage clock input may or may not match the active edge of the original clock signal, causing a problem.

OBJECTS OF THE INVENTION It is an object of the invention to use a single clock signal to
Further, it is an object of the present invention to provide a binary counter which can perform 1 times the input clock count, 1.5 times the count, and 2 times the count operation of the input clock with a single clock, and can easily switch the counting operation.

Structure of the Invention The binary counter of the present invention has at least a first stage and a second stage flip-flop (hereinafter referred to as FF).
A binary counter configured by connecting a plurality of FFs in cascade, has a set terminal and a reset terminal, and uses an inverted signal obtained by inverting the polarity of the clock signal as a clock input signal. , a 1/2 frequency divider that divides the frequency of the inverted signal by half, which is reset at the first output level of the Q output of the first stage FF and set by the clock signal.
RS・FF, and the Q output of the first stage FF is the second stage FF.
When the output level of the 1/2 frequency divider reaches the first output level, the inhibition is released and the next clock signal is output as the first signal. The first stage FF counts clock signals and inhibits clock input when the Q output of the 1/2 frequency divider is at the second output level; The second-stage FF is configured to take a signal whose output level matches the clock signal as a second signal, and performs a counting operation using both the first and second signals as clock inputs, and is a 1/2 frequency divider. This configuration allows the user to select one of the set and reset states, the set state, and the reset state, and set the clock to 1x, 1.5x, or 2x operation, thereby using a single clock signal. , and the count operation is 1 times the input clock and 1.5 times the input clock with a single clock query.
It is possible to perform twice the counting operation and also to easily switch the counting operation.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows a block diagram of a binary counter in an embodiment of the present invention.

Components that are the same as those in FIG. 1 are given the same reference numerals and their explanation will be omitted. NAND gate 14,
15 is an RS/FF whose input end and output end are cross-coupled with each other, and one input of the NAND gate 14, which is the reset input end, is connected to the first stage FF4.
is connected to the Q output of , and is the set input terminal.
One input of the NAND gate 15 receives the clock signal of the input terminal 1.

In the logic circuit composed of this RS/FF and AND gate 13, when the Q output of the first stage FF is at the first output level (low level), the operation of the AND gate 13 is prohibited and the output maintains the low level. do. Then, when the Q output of the first stage FF is at the second output level (high level), the inhibition of the AND gate 13 is released, and the AND gate 13 outputs only the next first clock signal as the first signal. Output at the end.

And the AND gate 11 is the Q of the 1/2 frequency divider 3.
When the output is at the second output level (high level), the clock signal of input terminal 1 is output as the second signal, and the OR gate 16 outputs both the first and second signals as the clock signal of the second stage FF5. The configuration is such that it is applied to the input terminal CK.

The operation of the binary counter of this embodiment configured as described above will be explained below. Figure 5 is a time chart when the 1/2 frequency divider 3 is reset, where 1a is the clock signal supplied to the clock signal input terminal 1, and 3Q is the 1/2 frequency divider 3.
Non-inverted output of frequency divider 3, 10a and 11a are AND
Output signals of gates 10 and 11, 4Q, 5Q, 6
Q, 7Q, 8Q are flip-flops 4, 5, 6,
Signals 14a of non-inverted outputs Q of 7 and 8, respectively.
15a is the output signal of each of the cross-coupled NAND gate pairs, and 13a is the output signal of the AND gate 13. binary counter 9
The clock input signal is counted by 1 with a single active edge. FIG. 6 shows a time chart when the 1/2 frequency divider 3 is neither set nor reset. In this case, the difference from the conventional example (Fig. 3) is that the clock output from the gate 11 (a waveform in which every other clock pulse is missing and the frequency is half) is changed from the lowest value of the binary counter 9 without changing its polarity. 2
The clock is supplied to the flip-flop 5 in the first stage, and the clock to the flip-flop 5 in the second stage is supplied by the generation of an active edge of the output of the flip-flop 4 in the first stage. For example, during two periods of the clock signal from time _t1 to time _t5 , a clock signal is input once each to the flip-flop 4 on the lowest side of the binary counter and the flip-flop 5 on the second stage, and the binary counter 9 receives the clock signal. Three counts are performed during two cycles. The operation from time t ₅ to t ₉ is similar.

Furthermore, when the 1/2 frequency divider 3 is set to the set state in FIG.
There were times when the active edge of the clock input of the first stage coincided with the active edge of the original clock signal, and times when they did not match, but in the circuit configuration of the present invention shown in FIG. If the output is low level, the output of gate 13 becomes low level and gate 1
If a clock with the same active edge (same polarity) as the original clock is supplied from the output of 1 to the clock input of the second flip-flop, and the output of Q of the first flip-flop is at a high level, the original clock is supplied. With the arrival of the trailing edge of the input signal (the start of the low level period), the output of the gate 14 becomes low level and this state is maintained, and the output of the gate 13 is also held at low level, so that the flip-flop in the second stage from the output of the gate 11 A clock having the same active edge (same polarity) as the active edge of the original clock is supplied to the clock input of the clock. That is,
The active edge of the original clock signal is always constant and does not depend on the Q output state of the first stage flip-flop.

As is clear from the above description, the binary counter 9 performs 1x, 1.5x, and 2x counting operations by setting and resetting the 1/2 frequency divider 3 with a single active edge of a single clock input signal. Switching is done depending on the function. In the above embodiment, AND gates 10, 11, and 13 are used as matching gates, NAND gates are used as 15, and OR gates are used as 16, but other matching gates can be used by converting the logic.

Effects of the Invention As is clear from the above description, the present invention uses a 1/2 frequency divider with a set/reset function and a match gate to use a single clock signal, and a single active edge. 1 times the clock signal,
By performing 1.5x and 2x counting operations and easily switching the counting operations, an excellent effect can be obtained in that the output of the binary counter can be handled in the same way as a normal counter.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional binary counter.
2 and 3 are signal waveform diagrams of each part of the configuration shown in the first diagram, FIG. 4 is a configuration diagram of a binary counter in an embodiment of the present invention, and FIGS. 5 and 6 are diagrams of the configuration shown in the fourth diagram. It is a signal waveform diagram of each part. 1... Clock signal input terminal, 2... Inverter, 3... 1/2 frequency divider, 4 to 8... Flip-flop, 9... Binary counter, 10, 11,
13...AND gate, 14,15...NAND gate, 16...OR gate.

Claims (1)

[Claims] 1. A binary counter that has at least a first-stage flip-flop and a second-stage flip-flop (hereinafter referred to as FF), is configured by cascading a plurality of FFs, and counts a clock signal; a 1/2 frequency divider, which has a reset terminal, uses an inverted signal obtained by inverting the polarity of the clock signal as a clock input signal, and divides the frequency of the inverted signal by half; Reset at the output level and set at the clock signal.
RS・FF, and the second of the Q output of the first stage FF
When the output level of the 1/2 frequency divider reaches the first output level, the inhibition is released and the next clock signal is output as the first signal. The first stage FF counts clock signals and inhibits clock input when the Q output of the 1/2 frequency divider is at the second output level, and the Q output of the 1/2 frequency divider is the second output. The 1/2 frequency divider set includes the second stage FF which uses a signal whose level matches the clock signal as a second signal and performs a counting operation using both the first and second signals as clock inputs. and select one of the reset canceled state, set state, and reset state, and select 1x, 1.5x, or 2x
A binary counter characterized by being set to double counting operation.