JPH0964725A - Odd number frequency divider circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the structure of the odd number frequency divider circuit in which a duty cycle of a frequency division output is 1:1. SOLUTION: The circuit is provided with a counter 2 whose output Q2 connects to its reset input R and having outputs Q0-Q3 in 4 bit width, a D flip-flop 3 receiving an output of the output Q1 of the counter 2 at its data input D and receiving a clock signal at a clock input CLK via a NOT circuit 4, and an OR circuit 5 ORing an output signal outputted from the output Q of the D flip-flop 3 and a signal outputted from the output Q1 of the counter 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an odd frequency divider circuit that divides a clock by an odd number.

[0002]

2. Description of the Related Art An example of a conventional odd frequency divider circuit will be described with reference to FIGS. FIG. 4 is a circuit diagram of the odd frequency dividing circuit, and FIG. 5 is a timing chart showing the relationship between the clock and the frequency-divided signal. (A) is the clock and (b) is the frequency-divided signal. The odd frequency division circuit shown in FIG. 4 divides the clock by 5, and 1 is a 4-bit wide output Q0 to Q3.
Is a counter equipped with. CLK is the clock input of the counter 1 which inputs the divided clock, and R is the reset input. In the circuit shown in FIG. 4, the output of the output Q2 is the counter 1
Connected to the reset input R of.

As shown in FIG. 4, the clock to be divided is input to the clock input CLK of the counter 1, and the output Q1 of the counter 1 is used as the output of the divided signal.
By connecting the output Q2 of the above to the reset input R of the counter 1, a general dividing circuit by 5 can be realized.

The operation of the odd frequency divider circuit shown in FIG. 4 will be described. The output of the counter 1 is a type of counter that changes the output by catching the rising edge of the clock. As the clock is input to the clock input CLK, the outputs q0 to q3 output from the outputs Q0 to Q3 are (Q
0, q1, q2, q3) = (0, 0, 0, 0), (0, 0,
0, 1), (0, 0, 1, 0), (0, 0, 1, 1),
When the output q2 changes to (0, 1, 0, 0) and the output q2 becomes 1, the output of the counter 1 becomes (q
0, q1, q2, q3) = (0, 0, 0, 0). By repeating this operation, a signal obtained by dividing the clock by 5 is output from the output Q1 of the counter 1, as shown in FIG.

[0005]

However, the problem shown in FIG.
As shown in FIG. 5, the frequency-divided output of the frequency-dividing circuit has a problem that the duty cycle becomes 2: 3 and the duty cycle does not become 1: 1.

The present invention has been made in view of the above problems, and an object thereof is to provide a structure of an odd frequency dividing circuit in which a duty cycle of a frequency dividing output is 1: 1.

[0007]

In order to solve the above problems, an odd frequency dividing circuit according to claim 1 is an odd frequency dividing circuit that divides a clock by an odd number, and the rising edge or falling edge of the clock. The output of the circuit that performs frequency division using either of these is used as the input of the D flip-flop that operates with the inverted signal of the clock, and the logical sum operation of the output of the circuit and the output of the D flip-flop is performed. It is characterized by.

According to a second aspect of the present invention, there is provided an odd frequency dividing circuit which divides a clock by an odd number, the frequency dividing circuit utilizing either a rising edge or a falling edge of the clock. And an inverted signal of the clock for dividing the input of the second circuit, and an inverted signal of the clock for dividing the input of the second circuit. It is characterized by performing an OR operation of outputs.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of an odd frequency dividing circuit of the present invention will be described based on the circuit diagram of FIG. The odd frequency dividing circuit shown in FIG. 1 is a circuit for dividing a clock by 5, and 2 is a counter provided with outputs Q0 to Q3 having a 4-bit width. CLK
Is a clock input of the counter 2 for inputting a divided clock, and R is a reset input. In the circuit shown in FIG. 1, the output Q2 of the counter 2 is connected to the reset input R of the counter 2. Further, 3 is a D flip-flop for inputting the output of the output Q1 of the counter 2 to its data input D and inputting a clock to its clock input CLK via the NOT circuit 4, and 5 is an output Q of the D flip-flop 3. It is an OR circuit that performs an OR operation of the output signal output and the signal output from the output Q1 of the counter 2.

That is, the circuit shown in FIG. 1 branches the output signal output from the output Q1 of the counter 2 and operates one of them by the inverted signal of the clock (the output signal of the NOT circuit 4).
Input to the data input D of the flip-flop 3 and output the output signal from the output Q1 of the counter 2 to 1/2 of the clock.
A signal delayed by the cycle is generated, and the OR circuit 5 ORs the output signal output from the output Q1 of the counter 2 with the signal delayed by 1/2 cycle of the clock with respect to the output signal. It is a circuit that outputs the calculation result as a divided signal.

The operation of the circuit shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart showing the relationship of each signal. (A) is a clock, (b) is the output of the counter 2.
The output signal ψ1, (c) output from Q1 is the output signal ψ2, (d) output from the output Q of the D flip-flop 3.
Is the output signal ψ3 (divided signal) of the OR circuit 4. (B)
, The counter 2 operates in the same manner as the counter 1 of the circuit shown in FIG.
Is a divided signal with a duty cycle of 2: 3. On the other hand, the output signal ψ2 output from the output Q of the D flip-flop 3 detects the falling edge of the clock by the D flip-flop 3 and outputs the output signal ψ1 of the counter 2 input to its data input D 1 to its output Q. Since it is output from, the output signal .psi.1 of the counter 2 is delayed by a clock 1/2 cycle as shown in (c). Then, the output signal ψ1 of the counter 2 shown in FIG.
The clock is divided by 5 from the output of the OR circuit 5 by performing an OR operation with the output signal ψ2 output from the output Q of the D flip-flop 3 shown in (c),
It is possible to output a divided signal having a duty cycle of 1: 1.

Next, a different embodiment of the odd frequency dividing circuit of the present invention will be described with reference to the circuit diagram of FIG. The odd frequency division circuit shown in FIG. 3 is a circuit that divides a clock by five.
2 is a circuit including two peripheral circuits (frequency dividing circuits) of the counter 2 shown in FIG. The frequency dividing circuit 6a (first circuit) and the frequency dividing circuit 6b (second circuit) are the 4-bit wide output Q0-
This is a circuit in which the output Q2 of the counter 2 having Q3 is connected to the reset input R, and its clock input CLK is used as an input terminal, and its output Q1 is used as an output terminal.

In the odd frequency divider circuit shown in FIG. 3, the clock is input to the frequency divider circuit 6a, the inverted clock signal is input to the frequency divider circuit 6b via the NOT circuit 7, and the OR circuit 8 divides it. This is a circuit for performing an OR operation on the outputs of the frequency dividing circuit 6a and the frequency dividing circuit 6b and outputting the output of the OR circuit 8 as a frequency dividing signal. In the circuit shown in FIG. 1, the output of the counter 6 and the signal obtained by delaying the output of the counter 6 by 1/2 cycle of the clock are ORed to generate the divided signal.
The circuit shown in FIG.
A frequency divider circuit 6b that operates with a delay of / 2 cycle (a frequency divider circuit that operates with a clock of an equal cycle whose phase is 180 degrees different from the clock of the frequency divider circuit 6a) is provided, and the output of the counter 6a and
Since it is a circuit that performs an OR operation of the output of the counter 6b, the operation of the circuit shown in FIG. 3 is similar to the operation described based on the timing chart shown in FIG.

[0014]

According to the odd numbered frequency dividing circuit of the first or second aspect, it is possible to obtain a frequency divided output having a duty cycle of 1: 1.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an odd frequency divider circuit of the present invention.

FIG. 2 is a timing chart for explaining the operation of the odd frequency divider circuit shown in FIG.

FIG. 3 is a circuit diagram showing a different embodiment of the odd frequency dividing circuit of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional odd frequency divider circuit.

5 is a timing chart for explaining the operation of the odd frequency divider circuit shown in FIG.

[Explanation of symbols]

 3D flip-flop 6a frequency dividing circuit (first circuit) 6b frequency dividing circuit (second circuit)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Okita 1048, Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Works Co., Ltd.

Claims (2)

[Claims] 1. An odd frequency divider circuit for dividing a clock by an odd number, wherein the output of a circuit for performing frequency division using either the rising edge or the falling edge of the clock is an inverted signal of the clock. An odd-numbered frequency divider circuit, which is used as an input of a D flip-flop that operates in accordance with 1., and performs an OR operation of the output of the circuit and the output of the D flip-flop. 2. An odd frequency dividing circuit for dividing a clock by an odd number, the circuit performing frequency division by utilizing either the rising edge or the falling edge of the clock.
The input of the first circuit is used as the clock, and the input of the second circuit is used as an inverted signal of the clock, and outputs of the outputs of the first circuit and the second circuit are provided. An odd frequency divider circuit which performs a logical sum operation.