JPS6049490A - Presettable counter - Google Patents

Abstract

PURPOSE:To simplify the constitution of a preset circuit by providing set and reset terminals to each of cascaded delay FFs and giving higher priority to a setting action then a resetting action. CONSTITUTION:When an enable input 2 is applied, the FFs are reset all at once. At the same time, only the bits receiving high-level inputs are set among preset data 3-7. In this case, higher priority is given to the setting action than the resetting action for the FF with which both setting and resetting actions are performed simultaneously. The input 2 is transmitted assuredly to the set input S since there is an element delay equivalent to an AND gate compared with the transmission time to the reset input R. That is, the bit having a high level of preset data input is set, with the bit having a low level reset respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the simplification of a presettable counter that can be preset to any state.

In general, a presettable counter is a counter that performs a 1/N frequency division operation, and when a preset enable signal is given, each bit is set or reset according to preset data and preset to one of N states. It is possible. As a typical example of this, 4
Bit setting, delay 7 lip 7 with reset,
FIG. 6 shows a circuit diagram of a Johnson counter constructed using Rozzo and made brisector full. In order to configure a Johnson counter with a frequency division ratio from 1/10 to 1/2 in the circuit configuration shown in the figure, it is sufficient to apply each signal to the data input terminal 1 according to Table 1. The preset operation in this circuit is as follows: When the preset enable input 2 is given, the preset data input 5, 4, 5, 6.7 for each bit is performed.
This is done by setting or resetting each bit according to the state of . However, since this circuit has a large number of constituent elements, it has the drawback of hindering the improvement of the degree of integration, especially when it is integrated into an integrated circuit.

The present invention simplifies the preset circuit in order to alleviate such drawbacks, and will be described in detail below with reference to the drawings.

A specific example of the circuit of the present invention is shown in FIG. 1, and the configuration of the counter in the same figure is the same Johnson counter as in FIG.
The difference is that the delay 7 lip 70 lip used gives priority to the set function as shown in FIG. In the circuit of Fig. 1, if preset enable human power 2 is given, each 7
Lip 70 bits are reset uniformly, and at the same time only the bits of preset data 3, 4, 5, 6, and 7 to which a high level input is given are set.
7-rippu'Oy that sets and resets at the same time
As for the steps, each of the 7 lips and 70 tubes has set priority as shown in Figure 2, and in Figure 1, the preset enable human power 2 is propagated to the set human power S of 7 lips and 7 ships because it is transmitted to the reset human power R. Since there is an element delay equivalent to one AND gate than the propagation time of , it can be set reliably.

That is, the bits at which the preset data input is at a high level are set, and the bits at which the preset data input is at a low level are reset. Therefore, as is clear from the comparison between FIG. 1 and FIG. 3, the present invention can reduce the number of elements while obtaining exactly the same results.

On the other hand, in Figures 1 and 2, we explained an example in which all bits are uniformly reset using the set priority function, but if the delay 7 lip 70 bit in Figure 2 is changed to reset priority, the configuration in Figure 1 can also be used. It goes without saying that the structure is changed to one in which all bits are uniformly set, and the preset data input and AND gate are connected to the reset human power R.In addition, in the explanation of the circuit example shown in FIG. 1 above, , since each set manual force S has a propagation delay of one AND gate with respect to the reset manual force R, it is stated that the set can be reliably set even if the set and reset are performed at the same time, but in order to further increase the certainty, the preset The idea is to separate the enable signal into one for set and one for reset, and make the enable signal for set have a longer pulse width than the enable signal for reset, so that the set signal remains even after the reset signal ends. It will be done.

The present invention is applicable not only to the above-mentioned Johnson counter, but also to counters with other branching modes such as binary code counters, and also to counters using other 7-lip L7 flops (such as the JK7 70-lip, etc.). It can also be applied to circuits.Table 1 is a connection table for constructing a Johnson counter in FIGS. 1 and 3.

Table 1

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a presettable counter according to the present invention. FIG. 2 is a circuit diagram of a 70-tub delay with set function priority used in the present invention. FIG. 3 is a diagram showing an example of the configuration of a conventional presettable counter. 1...Data input terminal 2...Preset enable input terminal 3, 4, 5. (
S, 7...Preset data input terminal 8...Clock input terminal and above Applicant Suwa Seikosha Co., Ltd. Agent Patent attorney Tsutomu Mogami

Claims (2)

[Claims] (1) In a counter obtained by connecting a plurality of delay flip-70 flip-flops in series, each delay-7 flip-flop has a set terminal and a reset terminal, and the set operation takes priority over the reset operation. can be,
Each reset terminal is equally connected to the preset enable input terminal, and each set terminal independently functions as a set data input terminal, so that when the preset enable input is given, all bits are uniformly reset and the necessary A presettable counter that sets only certain bits. (2) ``A counter obtained by connecting multiple delay flip-70 flip-flops in series, each delay-7 flip-flop has a set terminal and a reset terminal, and the reset operation takes priority over the set operation. Each set terminal is equally connected to the preset enable input terminal, and each reset terminal independently functions as a reset data input terminal, so that when the preset enable input is given, all bits are uniformly set. A presettable counter that also resets only necessary bits.