JPS63163563A - Data processor - Google Patents

Data processor

Info

Publication number
JPS63163563A
JPS63163563A JP61314564A JP31456486A JPS63163563A JP S63163563 A JPS63163563 A JP S63163563A JP 61314564 A JP61314564 A JP 61314564A JP 31456486 A JP31456486 A JP 31456486A JP S63163563 A JPS63163563 A JP S63163563A
Authority
JP
Japan
Prior art keywords
processing unit
general
scientific
registers
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61314564A
Other languages
Japanese (ja)
Inventor
Toshikatsu Nagasawa
長澤 敏勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61314564A priority Critical patent/JPS63163563A/en
Publication of JPS63163563A publication Critical patent/JPS63163563A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053Vector processors

Abstract

PURPOSE:To improve the performance of a central processing unit by providing general registers and validation bits corresponding to these registers in the central processing unit and a scientific arithmetic processing unit. CONSTITUTION:A central processing unit 2 and a scientific arithmetic processing unit 3 are provided with plural general registers 10 and 12 used by machine language instructions and validation bits 11 and 13 corresponding to these registers. Validation bits corresponding to general registers used in the central processing unit 2 are turned on, and contents of used general-purpose registers GR(0)-GR(15) are transferred to general-purpose registers of the scientific arithmetic processing unit 3 and validation bits V(0)-V(15) corresponding to pertinent general-purpose registers in the central processing unit 2 are turned off. Validation bits U(0)-U(15) corresponding to general registers, to which contents of said registers are transferred, of the scientific arithmetic processing unit 3 are turned on, and results of scientific operation arithmetic processing based on contents of general-purpose registers XRG(0)-XRG(15) of the scientific arithmetic processing unit 3 are stored in general-purpose registers 12 of the scientific arithmetic processing unit 3. Thus, the processing is quickly performed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は科学演算処理装置(SIP)を備えるデータ処
理装置における汎用レジスタの制御の方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a system for controlling general-purpose registers in a data processing device equipped with a scientific processing unit (SIP).

(従来の技術) 従来、この種のデータ処理装置には汎用レジスタ(OR
)と呼ばれろレジスタが16個中央処理装置内に存在し
ており、科学yL算焙処理装置接続されても科学演算が
終了した後はその演算結果を汎用レジスタに格納するた
め科学演算処理装置から中央処理装置に演算結果データ
全転送していた。
(Prior Art) Conventionally, this type of data processing device has a general-purpose register (OR
) There are 16 registers in the central processing unit, and even if the scientific calculation processing unit is connected, after the scientific calculation is completed, the result of the calculation is stored in the general-purpose register, so the data is transferred from the scientific calculation processing unit. All calculation result data was transferred to the central processing unit.

上記汎用レジスタは、ソフトウェアの構造によりアドレ
ス計算、科学演算、分岐先アドレス等により用いられる
レジスタがそれぞれ異っている。
Among the general-purpose registers, registers used for address calculations, scientific operations, branch destination addresses, etc. differ depending on the software structure.

(発明が解決しようとする問題点〕 したがって、上記演算結果を中央処理装置に転送させな
いためには汎用レジスタの2重化が考えられるが、16
個の汎用レジスタのうちいずれの汎用レジスタを常駐さ
せてよいか不明であるという問題が生ずる。
(Problem to be solved by the invention) Therefore, in order to prevent the above calculation results from being transferred to the central processing unit, duplication of general-purpose registers can be considered.
A problem arises in that it is unclear which general-purpose register out of the total number of general-purpose registers can be made resident.

本発明の目的は科学演算結果を科学演算処理装置から中
央処理装置に転送する動作を省略することにより処理の
高速化を図ったデータ処理装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that can speed up processing by omitting the operation of transferring scientific calculation results from a scientific calculation processing device to a central processing unit.

(問題点を解決するための手段〕 前記目的を達成するために本発明によるデータ処理装置
は機械語命令を処理する中央処理装置と前記中央処理装
置の指示にしたがって科学演算を実行する科学演算処理
装置とによって構成されるデータ処理装置において、前
記中央処理ge置と科学演算処理装置それぞれに、機械
語命令で使用する複数個の汎用レジスタと前記各汎用レ
ジスメ対応に有効ビット全具備し、中央処理製電内の使
用されている汎用レジスタ対応の有効ビットをオンし、
前記使用されている汎用レジスタの内容を科学演算処理
装置の汎用レジスタに転送するとともに中央処理装置の
当該汎用レジスタ対応の有効ビットをオフし、科学演算
処理装置の転送された汎用レジスタ対応の有効ビットを
オンし、前記科学演算処理装置の汎用レジスタの内容に
基づき科学演算処理した結果を科学演算処理装置の汎用
レジスタに格納するように構成されている。
(Means for Solving the Problems) In order to achieve the above object, a data processing device according to the present invention includes a central processing unit that processes machine language instructions, and a scientific operation processor that executes scientific operations according to instructions from the central processing unit. In the data processing device, each of the central processing unit and the scientific processing unit is equipped with a plurality of general-purpose registers used in machine language instructions and all valid bits corresponding to each of the general-purpose registers, and Turn on the valid bit corresponding to the general-purpose register used in the electronics manufacturing,
The content of the general-purpose register being used is transferred to the general-purpose register of the scientific processing unit, and the valid bit corresponding to the general-purpose register of the central processing unit is turned off, and the valid bit of the scientific processing unit corresponding to the general-purpose register that has been transferred is turned off. is turned on, and the result of scientific calculation processing based on the contents of the general-purpose register of the scientific calculation processing device is stored in the general-purpose register of the scientific calculation processing device.

(実 施 例) 以下、図面を参照して本発明金さらに詳しく説明する。(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

第1図は本発明によるデータ処理装置の実施例を示すブ
ロック図である。
FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention.

図において、主記憶装置(MEM)1と、中央処理装置
(cpu)zはメモリバス100で結合されている。中
央処理装置2と科学演算処理袋@(8IP)3はデータ
バス101で結合されている。
In the figure, a main memory device (MEM) 1 and a central processing unit (CPU) z are connected by a memory bus 100. The central processing unit 2 and the scientific operation processing bag@(8IP) 3 are connected by a data bus 101.

中央処理装置2は汎用レジスタG几(0)〜GR(15
)までの16個のレジスタを具備している。
The central processing unit 2 has general-purpose registers G(0) to GR(15).
) is equipped with 16 registers.

このレジスタ10にそれぞれ対応して有効ビン)V(o
)〜V (15)まで設けである。
Valid bins) V(o
) to V (15).

一方、科学演算処理装置3にも中央処理装置2に対応の
汎用レジスタXGR(o) 〜XGJ15)までの16
個のレジスタ12Q設けてアク、これらについても中央
処理装置の場合と同様、汎用レジスタXGR(0)〜X
GR(15)に対応してそれぞれ有効ピッ) V (0
)〜V(xs)6設けである。
On the other hand, the scientific processing unit 3 also has 16 general-purpose registers XGR(o) to XGJ15) corresponding to the central processing unit 2.
As in the case of the central processing unit, these registers 12Q are provided with general-purpose registers XGR(0) to X
Corresponding to GR (15), each valid pitch) V (0
) to V(xs) are provided.

初期状態では中央処理装置2内の有効ビットv(0〕〜
V(1s)は丁ぺてオン状態とされ、科学演算処理装置
3の有効ビットV (O)〜v(15)はオフ状態とさ
れる。
In the initial state, the valid bits v(0) to
V(1s) is turned on, and the valid bits V(O) to v(15) of the scientific processing unit 3 are turned off.

次に汎用レジスタGR(3)と主記憶装[1のオペラン
ドデータの科学演算を行なって、その演算結果を汎用レ
ジスタGR(3)に書込む機械語命令を実行する場合に
ついて述べる。
Next, a case will be described in which a machine language instruction is executed to perform a scientific operation on the operand data of the general-purpose register GR(3) and the main memory [1, and write the result of the operation to the general-purpose register GR(3).

機械語命令が解釈されるとオペランドアドレスに従い、
主記憶装置lからオペランドデータを中央処理装置2内
に取込む。
When a machine language instruction is interpreted, according to the operand address,
Operand data is taken into the central processing unit 2 from the main storage device l.

中央処理装置2は科学演算の演算コードとオペランドデ
ータを科学演算処理装置3に転送する。
The central processing unit 2 transfers the scientific operation code and operand data to the scientific operation processing unit 3.

次に汎用レジスタ0R(3)の有効ビット■(3)をオ
フにして汎用レジスタGR(3)のデータをデータバス
101を通して送る。
Next, the valid bit (3) of the general-purpose register 0R (3) is turned off and the data of the general-purpose register GR (3) is sent through the data bus 101.

科学演算処理装置3は科学演算の演算コードとオペラン
ドデータと汎用レジスタGR(a)のデータが揃ったこ
とにより科学演算を開始する。
The scientific operation processing device 3 starts the scientific operation when the operation code of the scientific operation, the operand data, and the data in the general-purpose register GR(a) are completed.

科学演算処理装置3は科学演算の終了により演算結果を
科学演算装置3内の汎用レジスタXGR(3)に格納す
ると、同時に有効ビン)V(a)をオンにする。
Upon completion of the scientific operation, the scientific operation processing device 3 stores the operation result in the general-purpose register XGR(3) within the scientific operation device 3, and at the same time turns on the valid bin (V(a)).

(発明の効果) 本発明は以上説明したように中央処理装置と科学演算処
理装置にそれぞれ汎用レジスタおよび対応に有効ビット
を設けることにより、演算結果を汎用レジスタに格納す
る機械語命令などの場合、科学演算処理装置から中央処
理装置に演算結果を転送する必要がなくなるので、中央
処理装置の性能を向上させることができる。
(Effects of the Invention) As described above, the present invention provides general-purpose registers and corresponding valid bits in the central processing unit and the scientific processing unit, respectively, so that in the case of machine language instructions that store operation results in general-purpose registers, etc. Since there is no need to transfer calculation results from the scientific processing unit to the central processing unit, the performance of the central processing unit can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるデータ処理装置の実施例を示すブ
ロック図である。 1・・・主記憶装置   2・・・中央処理装置3・・
・科学演算処理装置 10.12−16個の汎用レジスタ 11.13−・汎用レジスタに対応した有効ビット 特許出願人  日本電気株式会社 代理人 弁理士 井 ノ  ロ   壽オIm
FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. 1... Main memory device 2... Central processing unit 3...
・Scientific processing unit 10.12-16 general-purpose registers 11.13-・Effective bits corresponding to general-purpose registers Patent applicant NEC Corporation Representative Patent attorney Hisao Inoro Im

Claims (1)

【特許請求の範囲】[Claims] 機械語命令を処理する中央処理装置と前記中央処理装置
の指示にしたがつて科学演算を実行する科学演算処理装
置とによつて構成されるデータ処理装置において、前記
中央処理装置と科学演算処理装置それぞれに、機械語命
令で使用する複数個の汎用レジスタと前記各汎用レジス
タ対応に有効ビットを具備し、中央処理装置内の使用さ
れている汎用レジスタ対応の有効ビットをオンし、前記
使用されている汎用レジスタの内容を科学演算処理装置
の汎用レジスタに転送するとともに中央処理装置の当該
汎用レジスタ対応の有効ビットをオフし、科学演算処理
装置の転送された汎用レジスタ対応の有効ビットをオン
し、前記科学演算処理装置の汎用レジスタの内容に基づ
き科学演算処理した結果を科学演算処理装置の汎用レジ
スタに格納することを特徴とするデータ処理装置。
A data processing device comprising a central processing unit that processes machine language instructions and a scientific calculation processing unit that executes scientific calculations according to instructions from the central processing unit, the central processing unit and the scientific calculation processing unit Each is equipped with a plurality of general-purpose registers used in machine language instructions and a valid bit corresponding to each of the general-purpose registers, and turns on the valid bit corresponding to the general-purpose register used in the central processing unit. transfers the contents of the general-purpose register to the general-purpose register of the scientific processing unit, turns off the valid bit corresponding to the general-purpose register of the central processing unit, turns on the valid bit of the scientific calculation processing unit corresponding to the transferred general-purpose register, A data processing device characterized in that a result of scientific calculation processing based on the contents of a general-purpose register of the scientific calculation processing device is stored in a general-purpose register of the scientific calculation processing device.
JP61314564A 1986-12-24 1986-12-24 Data processor Pending JPS63163563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61314564A JPS63163563A (en) 1986-12-24 1986-12-24 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61314564A JPS63163563A (en) 1986-12-24 1986-12-24 Data processor

Publications (1)

Publication Number Publication Date
JPS63163563A true JPS63163563A (en) 1988-07-07

Family

ID=18054798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61314564A Pending JPS63163563A (en) 1986-12-24 1986-12-24 Data processor

Country Status (1)

Country Link
JP (1) JPS63163563A (en)

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