JPH0588890A - Data processing method - Google Patents

Abstract

PURPOSE:To further decrease the number of program steps by parallel calcula tion. CONSTITUTION:This data processing method executes designated operations to an operand at the designated storage destination while containing a part to designate the kind of the operation and a part to designate the storage destination of the operand in one instruction word, the part to designate the storage destination of the operand is defined as 1st, 2nd, 3rd and 4th parts rd1, rs1, rd2 and rs2, the designated operations are executed to the operands at the two storage destinations designated by the first and second parts rd1 and rs1, and the designated operations are also executed to the operands at the two storage destinations designated by the third and fourth parts rd2 and rs2.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a data processing method. An instruction word used in a data processing device such as a computer is a part (op) that specifies a type of operation (processing or operation).
code: operation code) and a part (address part in the case of direct memory specification) for designating an operand (operand: number of operations) to be operated.

Depending on the number of address parts in a command word, it can be classified into a 1-address system, a 2-address system, or a 3-address system. The one-address method operation is performed between the accumulator and the operand designated by the address part (one), and the operation result is stored in the accumulator. It is often used in simple systems because the instruction words are short and easy to decipher. Two-address method There are two address parts in one instruction word, and two registers (or memory, hereinafter referred to as a register) are designated by these. The operation is performed on the operands in the two registers and the result is written back to one of the two registers. Three-address method The two-address method is expanded to have three addresses, and the operation is performed in the form of (A) + (B) → (C), for example. That is, the operation is performed on the operand of address A and the operand of address B, and the result is stored in address C. The function of one instruction becomes high,
While it can reduce the number of program steps, it has the disadvantage of lengthening the command word.

[0003]

2. Description of the Related Art FIG. 6 shows a conventional instruction word having a length of 32 bits. In this figure, opcode is an instruction code part, r
d, rs1 and rs2 are three address parts, and
pcode is assigned to 8 bits from bit 24 to bit 31, and rs1, rs2 and rd are bit 0 to bit 4, bit 14 to bit 18, respectively.
Alternatively, it is assigned to each 5 bits from bit 19 to bit 23. The 8 bits from bit 5 to bit 12 are unused unused bits (ig
nored). Further, as shown in FIG. 7, this instruction word may have bits 0 to 12 as the existing values.

[0004]

However, since such an instruction word format is a so-called three-address system having three address parts, for example, one instruction / one operation such as (rs1) + (rs2) → (rd). However, there is a limit when trying to further reduce the program steps.

Therefore, an object of the present invention is to further reduce the number of program steps by parallel operation.

[0006]

In order to achieve the above object, the present invention includes, in one instruction word, a part for designating a type of operation and a part for designating a storage destination of an operand,
A data processing method for executing a specified operation on an operand of a specified storage destination, wherein a part specifying a storage destination of the operand is four parts from a first part to a fourth part. And performs the operation specified for the two storage destination operands specified in the second part, and also for the two storage destination operands specified in the third and fourth parts. Characterized by performing a specified operation.

[0007]

In the present invention, four operands are designated at one time by one instruction word. For example, four operands are a,
If b, c, and d are added and the instruction types of the instruction words are added, a + b = b and c + d = d are calculated. That is, the parallel calculation of these two expressions becomes possible.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are diagrams showing an embodiment of a data processing device to which a data processing method according to the present invention is applied. The instruction word m used in this data processing device has, for example, a 32-bit length, and its format is as shown in FIG. 1 with an instruction code portion opcode for specifying the type of operation and an operand storage destination (register or memory). 4 parts to specify r
It includes d1, rs1, rd2, and rs2.

Opcode is from bit 24 to bit 31
Up to 8 bits, and rd1 is assigned to 5 bits from bit 19 to bit 23, r
s1 is assigned to 5 bits from bit 14 to bit 18. Furthermore, rd2 is bit 8 to bit 12
5 bits to rs2, and rs2 is allocated to 5 bits from bit 0 to bit 4.

The four parts rd1, rs1, rd2, rs
Four storage destinations are designated according to the contents of 2, and a total of four operands are extracted. Hereinafter, rd1, rs1,
When the subscript V with parentheses is added to rd2 and rs2, the contents of the part (for example, register specified value or memory address value) are shown, or when the subscript O with parentheses is added, the contents of the part are followed. It shall represent the fetched operand (operation number).

FIG. 2 is a block diagram of the main parts of the data processing apparatus. 10 is a register file, 11 is a first arithmetic unit, 12 is a multiplexer, and 13 is a second arithmetic unit. The register file 10 includes an instruction register that stores an instruction word in the above format, a large number of general-purpose registers, and the like, and the first arithmetic unit 11 has four operands rd1 _(O) and rs1 _(O) extracted from the register file 10. , Rd
One set of 2 _(O) and rs2 _(O) "rd2 _(O) , rs
2 _(O) ", the type of operation specified by opcode is executed. The multiplexer 12 is rd1 _(O)
And rs2 _(O) are selected, the second arithmetic unit 13
Is the output of the multiplexer 12 "rd1 _(O) / rs
2 _(O) "and" rs1 _(O) "are subjected to the type of operation specified by opcode.

FIG. 3 is a diagram common to the arithmetic units 11 and 13. The arithmetic operation by the ALU 14 and the arithmetic operation by the multiplier 15 are executed with respect to two operands, and the multiplexer is operated according to the type of operation (for example, addition or multiplication). To output the result of either operation. Here, when the type of operation is "multiplication" (mlt instruction), the following two operations are executed.

(Rs1_(V)) × (rd1_(V)) → (rd1_(V)) (Rs2_(V)) × (rd2_(V)) → (rd2_(V)) That is, (1) One operation is the content rs1 of rs1._(V)Specified by
Storage destination (for example, a predetermined file in the register file 10)
Operand rs1 extracted from register r0)
_(O)And the contents of rd1 rd1_(V)Storage destination specified in (example
For example, from the predetermined register r2) in the register file 10
The fetched operand rd1_(O)And for the multiplication
And write the result back to register r2.
It is a series of processes. (2) Also, another operation is the content rs2 of rs2.
_(V)The storage destination specified in (for example, register file 10
Operand r fetched from a predetermined register r0) in
s2_(O)And the contents of rd1 rd2_(V)Storage destination specified in
(For example, the predetermined register r4 in the register file 10)
Operand rd2 extracted from_(O)And against
And write the result back to register r4.
It is a series of processes.

FIG. 4 is a diagram showing some instruction steps including these two operations, and is an example in which four mlt instructions (multiplication instructions) are followed by add instructions (addition instructions). The mlt instruction written in the first line corresponds to the above two operations (1) and (2). The code written on the right side of the instruction represents the content of each instruction in a binary number.
For example, the opcode code [11101000] represents multiplication, the rd1 code [00010] represents the register number [r2], the rs1 code [00000] represents the register number [r0], and the rd2 code [0010].
0] represents the register number [r4], and [00000] of the rs2 code represents the register number [r0].

As described above, in this embodiment, the portion for specifying the storage destination of the operand of one instruction word m is rs
1, rd1, rs2, rd2, that is, the four parts from the first to the fourth, and the opcode for the two storage destination operands specified by the first part (rs1) and the second part (rd1) Performs the operation specified by the third part (rs2) and the fourth part (rd
The specified operation can be simultaneously executed in parallel for the two storage destination operands specified in 2). Therefore, the parallel operation can further reduce the number of program steps.

Note that one of the four parts (rs2) for designating the storage destination of the operand may be an existing value as shown in FIG.

[0017]

According to the present invention, the parts for designating the storage destination of the operand of one instruction word are the four parts from the first to the fourth, so that the parts are designated by the first part and the second part. The specified operation is performed on the operands of the specified two storage destinations, and the specified operation is also executed on the operands of the two storage destinations specified by the third and fourth parts. Therefore, the parallel operation can further reduce the number of program steps.

[Brief description of drawings]

FIG. 1 is an instruction format according to an embodiment.

FIG. 2 is a main part configuration diagram of a data processing device according to an embodiment.

FIG. 3 is a configuration diagram of an arithmetic unit according to an embodiment.

FIG. 4 is an instruction code diagram of an example.

FIG. 5 is another instruction format according to an embodiment.

FIG. 6 is an instruction format of a conventional example.

FIG. 7 is another instruction format of the conventional example.

[Explanation of symbols]

 m: instruction word opcode: instruction code part rd1, rs1, rd2, rs2: four parts

Claims (1)

[Claims] 1. Data for executing a specified operation on an operand of a specified storage destination, including a part for specifying a type of operation and a part for specifying a storage destination of an operand in one instruction word. In the processing method, a part for designating a storage destination of the operand is divided into first to fourth parts.
Up to four parts, the specified operation is executed for the two storage destination operands specified in the first part and the second part, and the specified parts are specified in the third part and the fourth part. A data processing method characterized in that a specified operation is executed also for two operands of storage destinations.