JPS63155719A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device of high quality with high yield by providing many fine contact holes to a whole impurity diffused layer provided at the center of a wafer, thereby suppressing a breakdown of the contact holes and a gate at the time of ion implantation. CONSTITUTION:In a wafer 11, a large N<+> or P<+> type region 13 is so formed on one chip region 12 of the center as to extend substantially to the whole. Fine contact holes 14 are so formed in an insulating film on the region 13 as to be introduced into the region 13 dispersively in the whole regions 13. An ion implantation to a normal chip region for forming an element therearound is conducted. Then, a chargeup of the energy at the time of the ion implantation is concentrated only at the region 12, and the chargeup is escaped by way of an earth due to the holder of an ion implantation device at the periphery of the wafer 11. Accordingly, a chargeup is avoided from the chip region for forming a normal element therearound, and a breakdown is not observed, thereby obtaining a semiconductor device of high quality with high yield.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and in particular, the phenomenon of device destruction due to charge-up that occurs when performing ion implantation with high energy and high dose. Concerning means to prevent.

(Prior Art) FIG. 3 is a cross-sectional view of a conventional semiconductor device during direct ion implantation, where l is a semiconductor substrate, and 2
is an N-type or P-type diffusion layer, 3 is an insulating film (BPSG, etc.)
, 4 is an ion implantation protection resist, 5 is a contact hole, and A is a contact ion implantation implantation (hereinafter abbreviated as contact ion implantation).
It is.

When this is converted into a planar pattern diagram, it becomes as shown in Fig. 4.

As mentioned above, contact ion implantation is performed using Renost 4.
is done as a protective layer.

(Problem to be Solved by the Invention) However, the finer the diameter of the contact hole 5 (for example, 1.2μ or less), the more a charge-up phenomenon occurs during ion implantation, as shown in FIG. As a result, contact hole 5 is destroyed.

FIG. 6 is a plan view of the case where the contact hole 5 is destroyed. In particular, as shown in FIG. 7, the implantation holder 6 of the ion implantation apparatus holds the wafer 7 only at the periphery of the wafer 7. In this case, since only the peripheral portion is grounded, the energy during ion implantation is absorbed into the central portion 8 of the wafer 7, as shown in FIG.
The destructive phenomena shown in FIGS. 3 and 4 occur.

This phenomenon occurs because ionized impurities are highly accelerated and implanted. In particular, the smaller the contact hole 5 shown in FIG. 3, the wider the N type or P type diffusion layer 2, the more
Furthermore, the closer the resist 4 is to the contact hole 5, the more likely it is to occur in a concentrated manner.

In addition, such a destructive phenomenon can be confirmed by inspection for contact holes, but for example, P-) of MO8IC
Destruction cannot be determined by inspection, so methods such as electron shower implantation, which prevents impurity ionization, are being considered, but no fundamental countermeasure has been found.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, which suppresses destructive phenomena such as contact holes and dirt during ion implantation as described above, and can obtain high-quality semiconductor devices with a high yield. .

(Means to Solve the Problem) In this invention, the steps of providing an impurity diffusion layer in the central part of the wafer and forming a large number of fine contact holes throughout the diffusion layer on the impurity diffusion layer are sequentially performed. The central portion of the wafer is then used as a sacrificial region, and then ion implantation is performed on the wafer.

(Function) The charge-up phenomenon of ion implantation/chision is
■The wider the impurity diffusion layer is in the center of the wafer, ■the smaller the contact hole, and ■the closer the resist is to the contact hole, the more likely it is to occur. This invention utilizes these characteristics in reverse, and performs ion implantation after configuring the central part of the wafer as described above to serve as a sacrificial area, and charge-up is concentrated only in the central part of the wafer. However, it is avoided from surrounding areas. Therefore, the destructive phenomenon associated with charge-up is concentrated only in the central part of the Ueno,
It will be avoided from surrounding areas.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a wafer 11 in one embodiment of the invention.

This wafer 11 has one chip area 12 in the center,
As shown in Figure 2, it is so large that it almost spreads over the entire area! Alternatively, a P+ region 13 is formed. In addition, on the N+ or P+ region 13, the area 1 is dispersed over the entire N+ or P+ region 13 on an unillustrated survival film.
3, a fine contact hole 14 (less than 1.2 microns) is formed using a resist mask (not shown) as a mask.

In one embodiment of the present invention, one chip region 12 at the center of the wafer 11 is configured as described above, and then ion implantation is performed into a regular chip region for forming elements on the periphery. Then, in the above wafer 11,
Large in one chip area 12 in the center! Alternatively, since the P+ region 13 is formed and a large number of fine contact holes 14 are formed above the P+ region 13, the tearing up due to the energy during ion trapping is concentrated only in one chip region 12 at the center. Since charge-up can escape from the periphery of the wafer 11 by being grounded by the holder of the ion implantation apparatus, the charge-up phenomenon can be avoided from the regular chip area for forming elements on the periphery.

By avoiding the charge-up phenomenon,
The destruction phenomenon is no longer observed in the chip area for regular element formation on the periphery, and the destruction phenomenon is concentrated in one chip area 2 at the center.

(Effects of the Invention) As explained above, according to the method of the present invention, the energy charge-up during ion implantation and the resulting destructive phenomenon can be concentrated only in the center of the wafer, and the periphery can be concentrated. Charge-up and destruction phenomena can be suppressed from this area. Therefore, high quality semiconductor devices can be obtained from the circumferential area at a high yield.

In addition, if heat treatment is performed after ion-injection,
A gettering effect can also be expected at the fractured area (crystal defect area) at the center of the wafer.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention, in which FIG. 1 is a plan view of a wafer, and FIG. 2 is a plan view of one chip area in the center of the wafer. FIG. 3 is a cross-sectional view of a conventional semiconductor device during contact ion implantation, FIG. 4 is a plan view of the same, FIG. FIG. 7 is a cross-sectional view showing the wafer holding state during ion implantation, and FIG. 8 is a plan view of the wafer showing the location where the destructive phenomenon occurs. DESCRIPTION OF SYMBOLS 11... Wafer, 12... Wafer) central chip area, 13... N+ or P+ area, 14... Contact hole. Figure 3 Y3 solidification plan view of the center of the wafer

Claims (1)

[Claims] A step of providing an impurity diffusion layer in the center of the wafer, and a step of providing a large number of fine contact holes throughout the entire diffusion layer on the impurity diffusion layer are sequentially performed to transform the center of the wafer into a sacrificial region. A method for manufacturing a semiconductor device, comprising: performing ion implantation on a wafer.