KR100261965B1 - Manufacturing method of triple well of semiconductor device - Google Patents

Manufacturing method of triple well of semiconductor device Download PDF

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KR100261965B1
KR100261965B1 KR1019970077390A KR19970077390A KR100261965B1 KR 100261965 B1 KR100261965 B1 KR 100261965B1 KR 1019970077390 A KR1019970077390 A KR 1019970077390A KR 19970077390 A KR19970077390 A KR 19970077390A KR 100261965 B1 KR100261965 B1 KR 100261965B1
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well
conductive
forming
conductive well
semiconductor device
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KR19990057339A (en
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이정훈
이영춘
김태우
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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Abstract

PURPOSE: A method for forming the triple well of a semiconductor device is provided to prevent the crystal defect from occurring in a wafer and to improve the control of the threshold voltage and the characteristic of punch-through in the device by forming a gettering film and the triple well simultaneously, wherein the gettering film is capable of controlling each well density by performing a mask process twice. CONSTITUTION: The first photoresist film pattern is formed on a semiconductor substrate(12) to expose the portion which will be a n-well(20). A buried p-well(14) is formed on the substrate(12) by a p-well implant process, and a p-well(16) is formed on the upper surface of the first photoresist film pattern. An n-well(20) is formed by using the first photoresist film pattern as a mask. After removing the first photoresist film pattern, the second photoresist film pattern is formed on the substrate(12) to expose the portion which will be a r-well(26) within the n-well(20). The r-well(26) is formed by using the second photoresist film pattern as a mask.

Description

반도체소자의 3중웰 형성방법Triple well formation method of semiconductor device

본 발명은 반도체소자의 3중웰 형성방법에 관한 것으로, 특히 두번의 마스크 공정으로 원하는 도핑 농도를 갖고 독립적으로 동작하는 3가지의 웰을 형성하는 동시에 게터링막(gettering layer)을 형성하여 접합 누설전류가 발생하는 것을 방지하고, 그에 따른 소자의 특성 및 생산성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a triple well forming method of a semiconductor device. In particular, two wells are used to form three wells having a desired doping concentration and operate independently, and a gettering layer is formed to form a junction leakage current. The present invention relates to a technique for preventing the occurrence of the corresponding component and improving the characteristics and productivity of the device.

일반적으로 DRAM 이하의 주변회로는 CMOS가 널리 사용되며, 이러한 CMOS 는 3중웰이 구비된 반도체기판에 형성되는데 3중웰은 종래의 2중웰 구조의 n-well 영역에 또 다른 p-well 영역이 형성된다.In general, CMOS is widely used for peripheral circuits below DRAM, and such CMOS is formed on a semiconductor substrate provided with triple wells. The triple well is formed with another p-well region in an n-well region of a conventional double well structure. .

이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 3중 웰 형성방법을 설명한다.Hereinafter, a triple well forming method of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 3중 웰 형성방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a triple well forming method of a semiconductor device according to the prior art.

먼저, 반도체기판(11) 상부에 소자분리 영역으로 예정되어 있는 부분에 소자분리막(15)을 형성한다.First, an element isolation film 15 is formed on a portion of the semiconductor substrate 11 that is intended as an element isolation region.

다음, n-well 마스크(17)를 이용하여 n-well 영역으로 예정된 부분에 임플란트 공정을 실시하여 n-well(13)을 형성한다. (도 1a참조)Next, an n-well 13 is formed by performing an implant process on a portion intended for the n-well region using the n-well mask 17. (See FIG. 1A)

그 다음, 상기 n-well(13) 이외의 영역을 노출시키는 동시에 n-well(13) 내의 일부분만 노출시키는 p-well 마스크(19)를 사용하여 임플란트 공정을 실시한다.Next, an implant process is performed using a p-well mask 19 which exposes a portion other than the n-well 13 and simultaneously exposes only a portion of the n-well 13.

이때, 상기 n-well(13) 내부에 r-well(23)이 형성되고, n-well(13) 이외의 영역에는 p-well(21)이 형성된다. (도 1b참조)At this time, an r-well 23 is formed inside the n-well 13, and a p-well 21 is formed in a region other than the n-well 13. (See FIG. 1B)

상기와 같이 종래기술에 따른 반도체소자의 3중웰 형성방법은, n-well을 형성한 다음에, p-well과 r-well을 동시에 형성하기 때문에 상기 r-well의 불순물 농도는 상기 p-well의 도즈와 n-well의 도즈에 의하여 결정되므로 상기 r-well의 불순물 농도를 독립적으로 조절할 수 없고, 낮은 온도에서 열공정을 실시하여 웨이퍼의 결정결함을 게터링(gettering)하기 위한 공정 디자인(process design)이 어려운 문제점이 있다.As described above, since the triple well forming method of the semiconductor device according to the related art forms n-wells and then simultaneously forms p-wells and r-wells, the impurity concentration of the r-wells is determined by the p-wells. As it is determined by the dose and the dose of the n-well, the impurity concentration of the r-well cannot be controlled independently, and the process design is used to getter the crystal defects of the wafer by performing a thermal process at a low temperature. This is a difficult problem.

본 발명은 상기한 종래기술의 문제점들을 해결하기 위하여, 2번의 마스크 공정으로 각각의 웰농도를 조절할 수 있는 3중웰을 형성하는 동시에 게터링막을 형성하여 웨이퍼에 결정결함이 발생하는 것을 방지하고, 각 소자의 문턱전압 조절이나 펀치쓰루 특성을 향상시키는 반도체소자의 3중웰 형성방법을 제공하는데 그 목적이 있다.The present invention to solve the above problems of the prior art, by forming a gettering film at the same time to form a triple well that can control each well concentration in two mask process to prevent the occurrence of crystal defects on the wafer, SUMMARY OF THE INVENTION An object of the present invention is to provide a triple well forming method of a semiconductor device which improves the threshold voltage and punch-through characteristics of the device.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a triple well forming method of a semiconductor device according to the prior art.

도 2a 및 도 2b 는 본 발명의 제1실시예에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도.2A and 2B are cross-sectional views illustrating a triple well forming method of a semiconductor device according to a first embodiment of the present invention.

도 2c 는 본 발명의 제2실시예에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도.2C is a cross-sectional view illustrating a method of forming a triple well of a semiconductor device according to a second embodiment of the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

11, 12 : 반도체기판 13, 20 : 필드산화막11, 12: semiconductor substrate 13, 20: field oxide film

14 : 베리드 p-well 15, 22 : 제2감광막14: buried p-well 15, 22: second photosensitive film

16, 21 : p-well 17, 18 : 제1감광막 패턴16, 21: p-well 17, 18: the first photosensitive film pattern

19, 24 : 제2감광막 패턴 23, 26 : r-well19, 24: second photosensitive film pattern 23, 26: r-well

28 : 제3감광막 패턴 30 : 베리드 r-well28: third photosensitive film pattern 30: buried r-well

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 3중웰 형성방법은,The triple well forming method of a semiconductor device according to the present invention for achieving the above object,

제1도전형의 반도체기판에 제2도전형웰으로 예정된 부분을 노출시키는 제1감광막 패턴을 형성하는 공정과,Forming a first photosensitive film pattern exposing a portion intended as a second conductive well on a first conductive semiconductor substrate;

상기 구조 전면에 제1도전형 임플란트 공정을 실시하여 베리드 제1도전형웰을 형성하는 동시에 상기 제1감광막 패턴 하부에 제1도전형웰을 형성하는 공정과,Forming a buried first conductive well by performing a first conductive implant on the entire surface of the structure and simultaneously forming a first conductive well under the first photoresist pattern;

상기 제1감광막 패턴을 제2도전형웰 마스크로 사용하여 상기 베리드 제1도전형웰 상부에 제2도전형웰을 형성하는 공정과,Forming a second conductive well on the buried first conductive well by using the first photoresist pattern as a second conductive well mask;

상기 제1감광막 패턴을 제거하는 공정과,Removing the first photoresist pattern;

상기 제2도전형웰의 일측에 제1도전형웰으로 예정된 부분을 노출시키는 제2감광막 패턴을 형성하는 공정과,Forming a second photoresist film pattern exposing a predetermined portion of the second conductive well on one side of the second conductive well;

상기 제2감광막 패턴을 제1도전형웰 마스크로 사용하여 제2도전형웰의 일측에 제1도전형웰을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a first conductive well on one side of the second conductive well by using the second photoresist pattern as the first conductive well mask.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 및 도 1b 는 본 발명의 제1실시예에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a triple well of a semiconductor device according to a first embodiment of the present invention.

먼저, 피형 반도체기판(12) 상부에 패드산화막(도시안됨), 질화막(도시안됨)제1감광막(도시안됨)을 순서대로 형성한 다음에, 소자분리 마스크를 이용하여 소자분리 영역으로 예정된 부분에 소자분리 절연막(22)을 형성하고, 상기 질화막 및 패드산화막을 제거한다.First, a pad oxide film (not shown) and a nitride film (not shown) and a first photoresist film (not shown) are formed in this order on an upper part of the semiconductor substrate 12, and then a device isolation mask is used to form a device isolation region. A device isolation insulating film 22 is formed, and the nitride film and the pad oxide film are removed.

다음, 상기 반도체기판(12) 상부에 n-well 영역으로 예정된 부분을 노출시키는 제1감광막 패턴(18)을 형성한다.Next, a first photoresist layer pattern 18 is formed on the semiconductor substrate 12 to expose a predetermined portion as an n-well region.

그 다음, 상기 제1감광막 패턴(18)을 p-well 마스크로 사용하여 높은 에너지로 p-well 임플란트 공정을 실시한다. 이때, 상기 제1감광막 패턴(18)에 의해 노출된 반도체기판(12)에는 베리드 p-well(14)이 형성되고, 상기 제1감광막 패턴(18) 하부의 반도체기판(12)에는 상기 p-well 임플란트 공정시 피형 불순물이 상기 제1감광막 패턴(18)을 관통하여 p-well(16)이 형성된다. 여기서, 상기 베리드 p-well(14)은 셀영역이 형성되는 r-well하부에서 발생되는 웨이퍼의 결정결함을 게터링하는 역할을 한다.Then, the first photoresist pattern 18 is used as a p-well mask to perform a p-well implant process with high energy. In this case, the buried p-well 14 is formed on the semiconductor substrate 12 exposed by the first photoresist pattern 18, and the p-well 14 is formed on the semiconductor substrate 12 under the first photoresist pattern 18. During the -well implant process, the p-well 16 is formed by penetrating impurities passing through the first photoresist pattern 18. Here, the buried p-well 14 serves to getter the crystal defect of the wafer generated under the r-well in which the cell region is formed.

그 후, 상기 제1감광막 패턴(18)을 n-well 마스크로 사용하여 보통 에너지로 n-well 임플란트 공정을 실시하여 n-well(20)을 형성한다. (도 2a참조)Thereafter, the first photoresist pattern 18 is used as an n-well mask to perform an n-well implant process using normal energy to form an n-well 20. (See Figure 2A)

다음, 상기 제1감광막 패턴(18)을 제거하고, 상기 반도체기판(12) 상부에 상기 n-well(20) 내부의 r-well로 예정된 부분을 노출시키는 제2감광막 패턴(24)을 형성한다.Next, the first photoresist layer pattern 18 is removed, and a second photoresist layer pattern 24 is formed on the semiconductor substrate 12 to expose a portion designated as an r-well inside the n-well 20. .

그 다음, 상기 제2감광막 패턴(24)을 r-well 마스크로 사용하여 r-well 임플란트 공정을 실시함으로써 r-well(26)을 형성한다. (도 2b참조)Next, the r-well 26 is formed by performing an r-well implant process using the second photoresist pattern 24 as an r-well mask. (See Figure 2b)

본 발명의 제2실시예에 따른 반도체소자의 3중웰 형성방법은 다음과 같다.A triple well forming method of a semiconductor device according to a second embodiment of the present invention is as follows.

상기 도 2a 까지의 공정을 실시하고, 상기 제1감광막 패턴(18)을 제거한다.The process to FIG. 2A is performed, and the first photosensitive film pattern 18 is removed.

그 다음, 상기 반도체기판(12) 상부에 상기 n-well(20) 내부의 r-well로 예정되어 있는 부분을 보호하는 제3감광막 패턴(28)을 형성한다.Next, a third photoresist pattern 28 is formed on the semiconductor substrate 12 to protect a portion of the n-well 20 that is supposed to be an r-well.

그리고, 상기 제3감광막 패턴(28)을 r-well 마스크로 사용하여 높은 에너지로 r-well 임플란트 공정을 실시하여 3중웰을 형성한다. 이때, 상기 제3감광막 패턴(28)에 의해 노출되어 있는 반도체기판(12) 하부에 베리드 r-well(30)이 형성되는 동시에 상기 제3감광막 패턴(28)의 하부에 r-well(26)을 형성한다. (도 2c참조)Then, the third photoresist pattern 28 is used as an r-well mask to form a triple well by performing an r-well implant process with high energy. In this case, the buried r-well 30 is formed under the semiconductor substrate 12 exposed by the third photoresist pattern 28, and the r-well 26 is formed under the third photoresist pattern 28. ). (See FIG. 2C)

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 3중웰 형성방법은, 두번의 마스크공정으로 3중웰을 형성하여 공정을 용이하게 하고, n-well, p-well 및 r-well 형성공정시 각각의 임플란트 공정 조건을 조절함으로써 소자의 문턱전압 및 펀치쓰루(punch through) 특성 조절을 용이하게 하여 트랜지스터의 조건 최적화가 가능하고, DRAM 소자의 경우 셀영역이 형성되는 r-well 하부에 베리드 p-well을 형성함으로써 웨이퍼의 결정결함을 게터링하여 접합 누설전류를 감소시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, the method of forming a triple well of a semiconductor device according to the present invention facilitates the process by forming a triple well by two mask processes, and in each of the n-well, p-well and r-well forming processes. By adjusting the implant process conditions, the threshold voltage and punch-through characteristics of the device can be easily adjusted to optimize the transistor conditions.In the case of DRAM devices, the buried p-well under the r-well where the cell region is formed By forming the semiconductor device, gettering of crystal defects in the wafer reduces the junction leakage current, thereby improving the characteristics and reliability of the semiconductor device.

Claims (6)

제1도전형의 반도체기판에 제2도전형웰으로 예정된 부분을 노출시키는 제1감광막 패턴을 형성하는 공정과,Forming a first photosensitive film pattern exposing a portion intended as a second conductive well on a first conductive semiconductor substrate; 상기 구조 전면에 제1도전형 임플란트 공정을 실시하여 베리드 제1도전형웰을 형성하는 동시에 상기 제1감광막 패턴 하부에 제1도전형웰을 형성하는 공정과,Forming a buried first conductive well by performing a first conductive implant on the entire surface of the structure and simultaneously forming a first conductive well under the first photoresist pattern; 상기 제1감광막 패턴을 제2도전형웰 마스크로 사용하여 상기 베리드 제1도전형웰 상부에 제2도전형웰을 형성하는 공정과,Forming a second conductive well on the buried first conductive well by using the first photoresist pattern as a second conductive well mask; 상기 제1감광막 패턴을 제거하는 공정과,Removing the first photoresist pattern; 상기 제2도전형웰의 일측에 제1도전형웰으로 예정된 부분을 노출시키는 제2감광막 패턴을 형성하는 공정과,Forming a second photoresist film pattern exposing a predetermined portion of the second conductive well on one side of the second conductive well; 상기 제2감광막 패턴을 제1도전형웰 마스크로 사용하여 제2도전형웰의 일측에 제1도전형웰을 형성하는 공정을 포함하는 반도체소자의 3중웰 형성방법.And forming a first conductive well on one side of the second conductive well using the second photoresist pattern as the first conductive well mask. 제 1 항에 있어서,The method of claim 1, 상기 제1도전형웰은 p-well 이고, 제2도전형웰은 n-well 인 것을 특징으로 하는 반도체소자의 3중웰 형성방법.Wherein the first conductive well is a p-well, and the second conductive well is an n-well. 제 1 항에 있어서,The method of claim 1, 상기 제2도전형웰의 일측에 형성된 제1도전형웰은 r-well 인 것을 특징으로 하는 반도체소자의 3중웰 형성방법.The first well formed on one side of the second conductive well is a triple well forming method of a semiconductor device, characterized in that the r-well. 제 1 항에 있어서,The method of claim 1, 상기 제2감광막 패턴은 상기 제2도전형웰의 일측에 제1도전형웰으로 예정된 부분을 보호하는 것을 특징으로 하는 반도체소자의 3중웰 형성방법.The second photoresist pattern is a triple well forming method of a semiconductor device, characterized in that to protect the portion of the second conductive well scheduled as a first conductive well on one side. 제 4 항에 있어서,The method of claim 4, wherein 상기 제2감광막 패턴을 제1도전형웰 마스크로 사용하여 임플란트 공정을 실시하여 베리드 제1도전형웰을 형성하는 동시에 상기 제2감광막 패턴의 하부에 제1도전형웰을 형성하는 것을 특징으로 하는 반도체소자의 3중웰 형성방법.A semiconductor device is formed using the second photoresist pattern as a first conductive well mask to form a buried first conductive well and a first conductive well under the second photoresist pattern. Triple well formation method. 제 5 항에 있어서,The method of claim 5, 상기 베리드 제1도전형웰은 셀영역이 형성되는 제2도전형웰 일측의 제1도전형웰 하부에 발생하는 웨이퍼의 결정결함을 게터링하는 것을 특징으로 하는 반도체소자의 3중웰 형성방법.The buried first conductive well is a method of forming a triple well of a semiconductor device, characterized in that the gettering of the crystal defects of the wafer occurring in the lower portion of the first conductive well on one side of the second conductive well in which the cell region is formed.
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