KR100354869B1 - Method for forming a isolation film - Google Patents
Method for forming a isolation film Download PDFInfo
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- KR100354869B1 KR100354869B1 KR1020000072899A KR20000072899A KR100354869B1 KR 100354869 B1 KR100354869 B1 KR 100354869B1 KR 1020000072899 A KR1020000072899 A KR 1020000072899A KR 20000072899 A KR20000072899 A KR 20000072899A KR 100354869 B1 KR100354869 B1 KR 100354869B1
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- active region
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- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000002955 isolation Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
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Abstract
본 발명은 소자분리막 형성 방법에 관한 것으로, 특히 래치-업(Latch-up) 특성을 저하시키기 위한 이온주입 공정을 틸트(Tilt) 이온주입 공정으로 진행하여 활성 영역의 반도체 기판 에지(Edge) 부위에만 산화막을 형성하므로, 활성 영역이 플로팅(Floating)되는 것을 방지하고 소자 동작시 발생되는 열의 방출을 용이하게 하며 또한 플로팅 바디(Body) 효과의 발생을 저하시키므로 소자의 수율 및 신뢰성을 향상시키는 특징이 있다.The present invention relates to a method of forming an isolation layer, and in particular, the ion implantation process for lowering latch-up characteristics is performed by a tilt ion implantation process, so that only the semiconductor substrate edge portion of the active region is formed. Since the oxide film is formed, the active region is prevented from being floated, it is easy to dissipate heat generated during operation of the device, and the generation of the floating body effect is reduced, thereby improving the yield and reliability of the device. .
Description
본 발명은 소자분리막 형성 방법에 관한 것으로, 특히 활성 영역의 반도체 기판 에지(Edge) 부위에만 산화막을 형성하여 소자의 수율 및 신뢰성을 향상시키는 소자분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film, and more particularly, to a method of forming a device isolation film in which an oxide film is formed only at an edge portion of a semiconductor substrate in an active region, thereby improving yield and reliability of the device.
반도체 소자는 매년 집적도의 증가 추세를 보이고 있으며, 이러한 집적도의 증가는 소자 각각의 구성 요소 면적 및 크기의 감소를 수반하게 되어 여러 가지 공정상의 제약을 맞게 되는데 그 중에서 소자 분리가 문제된다.Semiconductor devices show an increasing trend in integration every year, and the increase in integration is accompanied by a reduction in the component area and size of each device, which results in various process constraints, among which device separation is a problem.
종래의 소자분리막 형성 방법은 도 1a에서와 같이, 활성 영역과 소자분리 영역이 정의된 반도체 기판(11) 상에 소자분리 산화막(12)과 감광막(13)을 순차적으로 형성한 다음, 상기 감광막(13)을 상기 소자분리 영역 상측에만 남도록 선택적으로 노광 및 현상한다.In the conventional method of forming a device isolation film, as shown in FIG. 1A, a device isolation oxide film 12 and a photoresist film 13 are sequentially formed on a semiconductor substrate 11 on which an active region and a device isolation region are defined, and then the photoresist film ( 13) is selectively exposed and developed so as to remain only above the device isolation region.
도 1b에서와 같이, 상기 선택적으로 노광 및 현상된 감광막(13)을 마스크로 사용하여 상기 활성 영역의 소자분리 산화막(12)을 선택 식각한 후, 클리닝(Cleaning) 공정을 진행한다.As shown in FIG. 1B, the device isolation oxide film 12 in the active region is selectively etched using the selectively exposed and developed photosensitive film 13 as a mask, and then a cleaning process is performed.
도 1c에서와 같이, 상기 활성 영역의 반도체 기판(11)에 산소(O2) 분위기의 이온주입 공정(14)을 진행한다.As shown in FIG. 1C, an ion implantation process 14 in an oxygen (O 2 ) atmosphere is performed on the semiconductor substrate 11 in the active region.
여기서, 상기 산소(O2) 분위기의 이온주입 공정(14)은 래치-업 특성을 저하시키기 위한 공정이다.Here, the ion implantation step 14 in the oxygen (O 2 ) atmosphere is a step for reducing the latch-up characteristic.
그리고, 상기 이온주입 공정 진행 후, 상기 활성 영역의 반도체 기판(11) 상에 에피택셜(Epitaxial)층(15)을 성장시킨다.After the ion implantation process, an epitaxial layer 15 is grown on the semiconductor substrate 11 in the active region.
이어, 상기 감광막(13)을 제거한 다음, 전면에 폴리싱(Polishing) 공정을 진행한다.Subsequently, the photoresist layer 13 is removed, and then a polishing process is performed on the entire surface.
그 후, 상기 에피택셜층(15)을 포함한 전면에 스크린(Screen) 산화막(16)을 형성한다.Thereafter, a screen oxide film 16 is formed on the entire surface including the epitaxial layer 15.
여기서, 상기 스크린 산화막(16)을 형성하기 위한 열처리 공정 및 후속 공정에서 사용되는 열처리 공정에 의해 상기 이온주입 공정(14)으로 주입된 산소(O2)가 확산되어 상기 활성 영역의 반도체 기판(11) 전면에 산화막(17)을 형성한다.Here, the oxygen (O 2 ) injected into the ion implantation process 14 is diffused by a heat treatment process for forming the screen oxide film 16 and a heat treatment process used in a subsequent process, so that the semiconductor substrate 11 of the active region is diffused. An oxide film 17 is formed on the entire surface.
종래의 소자분리막 형성 방법은 래치-업 특성을 저하시키기 위한 이온주입 공정으로 활성 영역의 반도체 기판 전면에 산화막을 형성하므로, 상기 활성 영역이 산화막에 의해 반도체 기판과 격리되어 소자 동작시 발생되는 열이 빠져나가기가 어렵고 또한 플로팅 바디(Body) 효과가 증가하여 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.In the conventional method of forming a device isolation film, an oxide film is formed on the entire surface of a semiconductor substrate in an active region by an ion implantation process to reduce latch-up characteristics, so that the active region is isolated from the semiconductor substrate by an oxide film, and heat generated during operation of the device is removed. It is difficult to escape and the floating body effect is increased, resulting in a decrease in yield and reliability of the device.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 래치-업 특성을 저하시키기 위한 이온주입 공정을 틸트 이온주입 공정으로 진행하여 활성 영역의 반도체 기판 에지 부위에만 산화막을 형성하므로, 소자 동작시 발생되는 열의 방출을 용이하게 하고 또한 플로팅 바디 효과를 저하시키는 소자분리막 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, the ion implantation process to reduce the latch-up characteristics to the tilt ion implantation process to form an oxide film only on the edge portion of the semiconductor substrate of the active region, which is generated during operation It is an object of the present invention to provide a method for forming a device isolation film that facilitates the release of heat and also reduces the floating body effect.
도 1a내지 도 1c는 종래 기술에 따른 소자분리막 형성 방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of forming a device isolation film according to the prior art.
도 2a내지 도 2e는 본 발명의 실시 예에 따른 소자분리막 형성 방법을 나타낸 공정 단면도2A to 2E are cross-sectional views illustrating a method of forming a device isolation film according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11, 31 : 반도체 기판 12, 32 : 소자분리 산화막11, 31: semiconductor substrate 12, 32: device isolation oxide film
13, 33 : 감광막 15,35 : 에피택셜층13, 33: photosensitive film 15, 35: epitaxial layer
16, 36 : 스크린 산화막 17, 37 : 산화막16, 36: screen oxide film 17, 37: oxide film
본 발명의 소자분리막 형성 방법은 반도체 기판 상에 활성 영역을 정의하는 소자분리 산화막을 형성하는 단계, 상기 활성 영역의 반도체 기판에 틸트 이온주입 방법으로 산소(O2)를 주입하는 단계, 상기 활성 영역의 반도체 기판 상에 에피택셜층을 성장시키는 단계 및 전면을 열처리하여 상기 에피택셜층을 포함한 전면에 스크린 산화막을 형성함과 동시에 상기 주입된 산소(O2)가 확산되어 상기 활성 영역의반도체 기판 에지 부위에만 산화막이 형성되는 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming a device isolation film of the present invention includes forming a device isolation oxide film defining an active region on a semiconductor substrate, injecting oxygen (O 2 ) into the semiconductor substrate of the active region by a tilt ion implantation method, and in the active region. Growing an epitaxial layer on a semiconductor substrate and heat treating the entire surface to form a screen oxide film on the entire surface including the epitaxial layer, and simultaneously injecting the oxygen (O 2 ) into the semiconductor substrate edge of the active region. And an oxide film is formed only at the site.
상기와 같은 본 발명에 따른 소자분리막 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, preferred embodiments of the device isolation film forming method according to the present invention as described above in detail as follows.
도 2a내지 도 2e는 본 발명의 실시 예에 따른 소자분리막 형성 방법을 나타낸 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming an isolation layer in accordance with an embodiment of the present invention.
본 발명의 실시 예에 따른 소자분리막 형성 방법은 도 2a에서와 같이, 활성 영역과 소자분리 영역이 정의된 반도체 기판(31) 상에 소자분리 산화막(32)과 감광막(33)을 순차적으로 형성한 다음, 상기 감광막(33)을 상기 소자분리 영역 상측에만 남도록 선택적으로 노광 및 현상한다.In the method of forming a device isolation film according to the embodiment of the present invention, as shown in FIG. 2A, the device isolation oxide film 32 and the photoresist film 33 are sequentially formed on a semiconductor substrate 31 in which an active region and a device isolation region are defined. Next, the photoresist 33 is selectively exposed and developed to remain only above the device isolation region.
도 2b에서와 같이, 상기 선택적으로 노광 및 현상된 감광막(33)을 마스크로 사용하여 상기 활성 영역의 소자분리 산화막(32)을 선택 식각한 후, 클리닝 공정을 진행한다.As shown in FIG. 2B, the element isolation oxide layer 32 in the active region is selectively etched using the selectively exposed and developed photoresist layer 33 as a mask, and then a cleaning process is performed.
도 2c에서와 같이, 상기 활성 영역의 반도체 기판(31)에 산소(O2) 분위기의 틸트 이온주입 공정(34)을 진행한다.As shown in FIG. 2C, a tilt ion implantation process 34 in an oxygen (O 2 ) atmosphere is performed on the semiconductor substrate 31 in the active region.
여기서, 상기 산소(O2) 분위기의 틸트 이온주입 공정(34)은 래치-업 특성을 저하시키기 위한 공정이다.Here, the tilt ion implantation step 34 in the oxygen (O 2 ) atmosphere is a step for reducing the latch-up characteristic.
도 2d에서와 같이, 상기 틸트 이온주입 공정 진행 후, 상기 활성 영역의 반도체 기판(31) 상에 p형 불순물이 도핑된 에피택셜층(35)을 성장시킨다.As shown in FIG. 2D, the epitaxial layer 35 doped with p-type impurities is grown on the semiconductor substrate 31 in the active region after the tilt ion implantation process is performed.
도 2e에서와 같이, 상기 감광막(33)을 제거한 다음, 전면에 폴리싱 공정을 진행한다.As shown in FIG. 2E, the photoresist layer 33 is removed, and then a polishing process is performed on the entire surface.
그리고, 상기 에피택셜층(35)을 포함한 전면에 스크린 산화막(36)을 형성한다.The screen oxide layer 36 is formed on the entire surface including the epitaxial layer 35.
여기서, 상기 스크린 산화막(36)을 형성하기 위한 열처리 공정 및 후속 공정에서 사용되는 열처리 공정에 의해 상기 틸트 이온주입 공정(34)으로 주입된 산소(O2)가 확산되어 상기 활성 영역의 반도체 기판(31) 에지(Edge) 부위에만 산화막(37)을 형성한다.Here, the oxygen (O 2 ) injected into the tilt ion implantation process 34 is diffused by a heat treatment process for forming the screen oxide film 36 and a heat treatment process used in a subsequent process, so that the semiconductor substrate of the active region ( 31) The oxide film 37 is formed only at the edge part.
본 발명의 소자분리막 형성 방법은 래치-업 특성을 저하시키기 위한 이온주입 공정을 틸트 이온주입 공정으로 진행하여 활성 영역의 반도체 기판 에지 부위에만 산화막을 형성하므로, 활성 영역이 플로팅(Floating)되는 것을 방지하고 소자 동작시 발생되는 열의 방출을 용이하게 하고 또한, 플로팅 바디 효과의 발생을 저하시키므로 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the device isolation film forming method of the present invention, the ion implantation process for reducing the latch-up characteristic is performed by a tilt ion implantation process to form an oxide film only at the edge portion of the semiconductor substrate in the active region, thereby preventing the active region from floating. And it is easy to release the heat generated during the operation of the device, and also reduces the occurrence of the floating body effect has the effect of improving the yield and reliability of the device.
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