JPS63152090A - Dynamic ram - Google Patents

Abstract

PURPOSE:To accelerate an access time and to attain low power consumption, by providing a sense amplifier consisting of an amplifying MOSFET respectively for complementary data lines constituting a memory array, and a common sense amplifier connected selectively to a pair of complementary data lines in a group. CONSTITUTION:The unit circuit of the sense amplifier SA is provided corresponding to the complementary data line constituting the memory array M-ARY, and the unit circuit of the common sense amplifier CSA is provided at every group setting every four pairs of complementary data lines as one group. And a readout signal of the memory cell to be outputted is amplified at high speed by both a sense amplifier SA circuit corresponding to the complementary data line to which the memory cell is coupled, and a common sense amplifier CSA circuit connected selectively, and the storage information of another memory cell is refreshed only by the sense amplifier SA circuit provided corresponding to respective complementary data line. In such way, it is possible to perform a readout operation at high speed, and to lower the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic RAM (Random Access Memory), in which, for example, the memory array includes a capacitor for information storage and a MOS for address selection.
The present invention relates to a technique that is effective for use in a dynamic RAM, which is configured with an L-element type dynamic memory cell consisting of FETs, and in which a sense amplifier circuit is provided corresponding to each complementary data line.

[Conventional technology]

A dynamic RAM using a so-called one-element type dynamic memory cell is described, for example, in "Nikkei Electronics" published by Nikkei McGraw-Hill, June 3, 1985, pages 209 to 231.

[Problem that the invention seeks to solve]

In the dynamic RAM as described above, sense amplifier circuits are provided respectively corresponding to a plurality of complementary data lines forming a memory array. Further, a common source line for supplying operating current to a plurality of sense amplifier circuits arranged on the same memory mantle is laid out along these sense amplifier circuits. Sense amplifier circuits coupled to the same common source line are simultaneously brought into operation according to a sense amplifier operation timing signal supplied from a timing control circuit.

The sense amplifier circuit amplifies the minute Yo2t signal output from the dynamic memory cell.

The read signal amplified by the sense amplifier circuit is
It is selectively output via the complementary common data line, and the data of the corresponding memory cell is output as shown in 1. a Used to refresh emotions.

The access time in a read operation of a dynamic RAM is affected by the sensitivity and operating speed of these sense amplifier circuits. The sensitivity of this sense amplifier circuit is
It depends on the conductance of the amplification MOSFET that constitutes the sense amplifier circuit, and the operating speed of the sense amplifier circuit also depends on the rise of the operating current supplied via the conductance of the amplification MOSFET and the common source line.

As mentioned above, a sense amplifier circuit is provided for each complementary data line, and multiple sense amplifier circuits within the same memory mat are connected to a single sense amplifier circuit that is routed over a relatively long distance along the memory mat. According to the operating current supplied via the common source line, they are brought into operation simultaneously. In addition, these sense amplifier circuits are compatible with dynamic RAM
In addition to normal access, the dynamic RAM is activated during a refresh operation performed at a predetermined cycle, and the power consumption of the dynamic RAM is determined by the power consumption during the refresh operation. Therefore, by increasing the conductance of the amplifying MOS FET in the sense amplifier circuit and increasing its sensitivity, dynamic RAM
Although the operation speed of the dynamic RAM is increased, the power consumption of the dynamic RAM increases accordingly. on the other hand,
A distributed resistance exists in the common source line according to a distance from the driving MOSFET turned on by the timing signal as a starting point. Therefore, the operating speed of the sense amplifier circuit decreases as the distance from the driving MOSFET increases, and the access time as a dynamic RAM is uniformly determined by the operating speed of the sense amplifier circuit located farthest from the driving MOSFET. Ru. In the conventional dynamic RAM described above, the method of dividing the memory mantle and the size of the amplifying MOS FET in the sense amplifier circuit must be optimized depending on the desired access time, power consumption, and size of the semiconductor substrate. No.

An object of the present invention is to provide a dynamic RAM that further achieves faster access time and lower power consumption.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, an amplification MOS with relatively small conductance corresponds to the complementary data lines that constitute the memory array.
Each has a sense amplifier circuit consisting of an FET,
In addition, corresponding to the groups obtained by dividing the plurality of complementary data lines into each group by a predetermined number, the increase in conductance is considered to be relatively large.
A common sense amplifier circuit consisting of 1M05 FETs is provided which is selectively connected to a set of complementary data lines in a corresponding group according to a predetermined address signal.

[For production]

According to the above means, the read signal of the memory cell to be output is transmitted by both the sense amplifier circuit provided corresponding to the complementary data line to which the memory cell is coupled and the common sense amplifier circuit selectively connected. The dynamic type RAM is amplified at high speed, and the information stored in other memory cells is refreshed relatively slowly within the access period of the dynamic type RAM only by the sense amplifier circuit provided corresponding to each complementary data line. It is possible to speed up the read operation of RAM and reduce power consumption.

〔Example〕

Figure 2 shows a dynamic RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using a known CMO3 (complementary MOS) construction circuit manufacturing technology. In the diagrams below, a MOSFET with an arrow added to the channel (bank gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow added.

In the dynamic RAM of this embodiment, unit circuits of sense amplifiers SA are provided corresponding to the complementary data lines constituting the memory array M-ARY, and four sets of complementary data lines are defined as one group. Common sense amplifier C3A
unit circuits are provided. These common sense amplifiers C
The 3A unit circuit selects a memory cell to be selected or another memory cell whose column address of the lower two bits is the same as that of the memory cell, according to the lower two bit column address signals supplied as the X address signals AXO and AXI. is selectively connected to a set of complementary data lines in the group corresponding to the data lines. Therefore, the dynamic RAM0 column address decoder of this embodiment has a two-stage configuration together with the row address decoder, decodes the lower two bits of the column address signal, and decodes the common sense amplifier C3A.
and a selection signal yO− to the column address decoder CDCR.
A predecoder PDCR is provided for supplying y3. This predecoder PDCR decodes the lower 2 bits of the row address signal, forms word line selection timing signals φXO to φx3, and outputs the row address decoder R.
It also has the function of supplying to DCR.

Furthermore, the dynamic RAM of this embodiment employs an address multiplex system, and the X address signal AXO
-Axt and Y address signals AYO-AYi are supplied via the same external terminals AO-At. In addition, in the automatic refresh operation mode, a refresh address counter REFC for autonomously specifying a word line to be refreshed, and a refresh address counter R
Refresh address signal rx formed by EFC
oxrxi and externally supplied X address signal AXO
~AXi and select the row address buffer R.
Address multiplexer AMX for conveying to ADB
is provided.

In FIG. 2, although not particularly limited, the memory 7 ray M
-ARY is a two-intersection system, with m+1 sets of complementary data lines DO/H] to Dn-Dn arranged in the horizontal direction in the figure, and m11 word lines WO to Wm arranged in the vertical direction.
and (m+1)×(n+1) memory cells arranged at the intersections of these complementary data lines and word lines.

As will be described later, these memory cells are element type dynamic memory cells, and are each composed of an address selection MOSFETQm and an information storage capacitor Cs.

The drains of the address selection MOSFETs Qm of memory cells arranged in the same column of the memory array M-ARY are alternately coupled to the corresponding complementary data lines DO·σ1 to Dn-Dn with a predetermined regularity.

Complementary data lines DO/DO~Dn -Dn are coupled on one side to the unit circuit of the corresponding sense amplifier SA, and further connected to the switch MOSF of the common sense amplifier C3A.
It is coupled to its unit circuit via ET. Although not particularly limited, a unit circuit of the common sense amplifier C3A is provided for each group of four sets of complementary data lines, and connects the memory cell designated by the column address signal and the lower two It is selectively coupled to a complementary data line corresponding to another memory cell whose bit column address is the same as that of the memory cell. The gates of these switch MOS FET pairs are commonly connected,
Corresponding selection signal yO-y3 from predecoder PDCR
is supplied.

As described later, the sense amplifier SA has n + 1 (f
Consists of a lit degree circuit, common sense amplifier C
3A is composed of (n+1)/4 unit circuits.

The n+1 unit circuits of the sense amplifier SA are connected to each other via two sets of drive MOSFETs arranged in parallel.
The power supply voltage Vcc and ground potential of the circuit are supplied. Common source lines SP and SN are connected between these driving MOS FETs and the sense amplifier SA unit circuit, respectively.
is provided.

Similarly, (H+1)/of the common sense amplifier C3A
The power supply voltage Vcc of the circuit and the ground potential are supplied to the unit circuits No. 4 through two sets of drive MOSFETs arranged in parallel, respectively. Common source lines CP and CN are provided between these drive MOSFETs and the unit circuit of the common sense amplifier CSA, respectively. The two sets of driving MOSFETs of the sense amplifier SA and the common sense amplifier C5A are provided with a timing control circuit TC, which will be described later.
Timing signals φpal and φρa2 are supplied from. These timing signals φpal and φpa2 are
They are formed with a slight time difference. Thereby, each unit circuit of the sense amplifier SA and the common sense amplifier C3A performs a two-stage operation according to the timing signals φpal and φpa2.

The specific circuit configuration and operation outline of these sense amplifiers SA and common sense amplifier C3A will be explained in detail later.

On the other hand, the complementary data lines Do-DO-Dn-Dn connect to the corresponding switch MOS of the column switch C8W.
It is coupled to the complementary common Deke line CD-σ stone via a FET pair. The gates of each switch MOSFET pair of the column switch C3W are commonly connected, and the corresponding data line selection signal Y is output from the column address decoder CDCR.
O-Yn is supplied respectively.

As described above, in the dynamic RAM of this embodiment, although not particularly limited, the lower two bits of the column address signal are supplied as the X address signals AXO and AXI, and other column address signals except these lower two bits are supplied. , Y address signals AYO to AYi.

Among these, the column address signal of the lower two bits is sent to the predecoder PDC via the row address buffer RADB.
R, decoded as selection signals yO to y3, and then supplied to column address decoder CDCH.

In addition, other column address signals are processed by complementary internal address signal ayQ by column address buffer CADB.
xayi (Here, for example, an internal address signal ayo having the same phase as the external address signal AYO and an internal address signal ayQ having the opposite phase are collectively expressed as a complementary internal address signal ayO.

(the same applies hereinafter) and is supplied to the column address decoder CDCR.

Column address decoder CDCR receives complementary internal address signal a supplied from column address buffer CADB.
Decodes yQ to ayi to the predecoder PD
Selection signal yO−) supplied from CR! 3, the data line selection signals YO to Yn are formed and supplied to the column switch C3W. These data line selection signals YO-Yn are formed in synchronization with the data line selection timing signal φy supplied from the timing control circuit TC.

Column address buffer CADB receives Y address signals AYO to AYi supplied via address signal input terminals AO-Ai in synchronization with the falling of column address strobe signal CAS, and receives Y address signals AYO to AYi supplied via address signal input terminals AO to Ai in synchronization with the falling edge of column address strobe signal CAS. In addition, complementary internal address signals ayQ to ayi are taken in and held according to the address information, and are supplied to column address decoder CDCH.

The common complementary data line CD-CD to which the complementary data line specified by the column switch C8W is selectively connected is
It is coupled to the input terminal of main amplifier MA and to the output terminal of data input buffer DIB. The output terminal of main amplifier MA is further coupled to the input terminal of data output sofa DOB.

The main amplifier MA is activated by the high level of the timing signal φma supplied from the timing control circuit TC, and further amplifies the read data inputted from the selected memory cell via one of the complementary common data lines CD. , and transmits the data to the data output sofa DOB.

In the read operation mode of the dynamic RAM, the data output cover 7F DOB is connected to the timing control circuit TC.
The main amplifier MA is activated by the high level of the timing signal φr supplied from the main amplifier MA, and outputs the output signal of the main amplifier MA to the data input/output terminal D10. Dynamic type R
In the AM non-operation state or write operation mode, the output of the data output buffer DOB is placed in a high impedance state.

The data input buffer DIB is a dynamic RAM
In the write operation mode, the timing signal φW is brought into an operating state by the high level, and the hot data supplied from the data input/output terminal DIO is used as a complementary write signal and is supplied to the complementary common data line CD-. When the dynamic RAM is in a non-operating state or in a read operation mode, the output of the data input buffer DIR is in a high impedance state.

On the other hand, n arranged in the same row of memory array M-ARY
+1 memory cell address selection M○S F E
The gate of TQm is coupled to the corresponding word line WO-Wm. The word lines WO-Wm are coupled to a row address decoder RDCR, and one of them is selected and
It is specified.

As described above, the row address decoder has a two-stage configuration. Furthermore, in the dynamic RAM of this embodiment, the row address signal of the lower two bits is the X address signal AX2.
and AX3, and other row address signals excluding the lower two bits are supplied as X address signals AX4 to AXi.
Supplied as.

Of these, the lower two bits of the row address signal are sent from the row address buffer RADB to the complementary internal address signal Q-A.
X2 and ax3 are sent to the predecoder PDCR, and after being decoded there, the word line selection timing signals φxQ to φx3 are sent to the row address decoder RDCR.
transmitted to R. Further, other row address signals excluding the lower two bits are directly transmitted from the row address buffer RADB to the row address decoder RDCR as complementary internal address signals ax4 to axi.

As described above, the predecoder PDCR decodes the lower two bits of the column address signal and outputs the selection signal yO-y.
3 and a row address buffer RADB.
Complementary internal address signals ax2 and ax3 supplied from
and word line selection timing signals φxO~φ
x3 and supplies it to the row address decoder RDCR.

These word line selection timing signals φxO to φx3 are formed in synchronization with the timing signal φX supplied from the timing control circuit TC.
In order to prevent the voltage from decreasing due to the threshold voltage of OS FET, the voltage is set to be slightly higher than the power supply voltage Vcc.

The row address decoder RDCR decodes the complementary internal address signals x4 to axi excluding the lower two bits, and further combines them with the word line selection timing signals φxO to φx3 supplied from the predecoder PDCR to determine which signals are designated as row address signals. A word line selection signal .multidot.(WO=Wm) is formed to bring one word line into a selected state at a high level slightly higher than the power supply voltage Vcc.

By configuring the row address selection circuit in two stages as described above, it is possible to match the layout pitch (interval) of the unit circuits of the row address decoder RDCR with the layout pitch of the word lines, thereby improving the layout on the semiconductor substrate. can be made efficient.

The row address buffer RADB receives a row address signal supplied from the address multiplexer AMX,
While holding it, the complementary internal address signal
~axi is formed and supplied to the predecoder PDCR and row address decoder RDCH.

As mentioned above, in the dynamic RAM of this embodiment, the data stored in the memory cell is read out within a predetermined period, and
An automatic refresh mode for rewriting is provided, and a refresh address counter REFC is provided for specifying a word line to be refreshed in this automatic refresh mode. Address multiplexer AMX receives X address signals AXO-AXi supplied via external terminals AO-Ai and refresh address signals rxo~ supplied from refresh address counter REFC in accordance with internal control signal ref supplied from timing control circuit TC. iM is selected from rXi and transmitted to the row address buffer RADB. That is, in a normal memory access mode in which the internal control signal ver is at a low level, the X address signal AXO=AXi supplied from an external device via the external terminal AOxAi is selected, and the internal control signal ref is at a high level. In the automatic refresh mode, refresh address signals rxQ to rxi output from the refresh address counter REFC are selected. X address signal AXO=
Since AXi is supplied in synchronization with the fall of the row address strobe signal RAS supplied as a control signal from the outside, the row address buffer RADB takes in the row address signal using the row address strobe signal RAS by the timing control circuit TC. This is performed in accordance with a timing signal φar generated by detecting the falling edge of .

The refresh address counter REFC operates in the automatic refresh operation mode of the dynamic RAM, counts the timing signal φC supplied from the timing control circuit TC, and generates refresh address signals rxQ to rxi for specifying the word line to be refreshed. and supplies it to the address multiplexer AMX.

The timing control circuit TC forms the above-mentioned various timing signals and internal control signals based on the row address strobe signal πAS, column address strobe signal CAS, and write enable signal WE supplied as control signals from the outside, and supplies them to each circuit.

FIG. 1 shows a circuit diagram of an embodiment of the sense amplifier SA and common sense amplifier C5A of the dynamic RAM shown in FIG.

In FIG. 1, each memory cell MC constituting the memory array M-ARY has an information storage capacitor Cs and an address selection MOSFET, as exemplarily shown in the same figure.
Consisted of. As mentioned above, the gates of the address selection MOSFETs of the memory cells MC of n 1 ([1) arranged in the same row are
j4 W O= W Salel bond to m. In addition, an MOS for selecting addresses of memory cells MC arranged in the same column
The drains of FET are alternately coupled to corresponding complementary data lines Do-DO to Dn-Dn with a predetermined regularity.

As shown in FIG. 1, each complementary data line DO-D to Dn-Dn is coupled on one side to a corresponding unit circuit USA of the sense amplifier SA, and is further coupled to a corresponding switch M of the common sense amplifier C3A. O.S.F.E.T.
It is selectively connected to the corresponding group of unit circuits UC5A via pairs Q13 and Q14 to Q27 and Q28. The gates of these switch MOSFET pairs are commonly connected every four pairs, and receive a selection signal y from a predecoder PDCR.
O to y3 are supplied. This selection signal yo=y3 is formed during normal memory access of the dynamic RAM, and is not formed during the refresh operation mode. On the other hand, each complementary data line Do/DO~Dn-Dn is
On the other side, the corresponding switch MO5FET pair of column switch C3W Q29/Q30~Q43/Q44
is selectively connected to the complementary common data line CD-CD via.

As mentioned above, the switch MOSFET pairs of these column switches csW include a column address decoder CDC.
Corresponding data line selection signals YO to Yn are supplied from R.

The sense amplifier SA is n + 1 (unit circuit U of II
Composed by SA. As exemplarily shown in FIG.
Q7. Q8 and N-channel MOSFETQII, QI
2 CMOS latch circuits, whose output nodes correspond to complementary data lines Do-DO-Dn-D.
n, respectively. Although not particularly limited, these amplifiers M constituting the unit circuit USA of the sense amplifier SA
The OSFET refreshes the information stored in the memory cell MC coupled to the corresponding complementary data line over the entire period of the refresh operation mode of the dynamic RAM.

The conductance is designed to have a relatively small conductance. The sources of the P-channel type and N-channel type amplification MOSFETs constituting the sense amplifier SA are commonly connected to common source lines SP and SN, respectively. Although not particularly limited, these common source lines SP and SN can be connected to parallel P-channel MOSFETQ.
3. Q4 is coupled to the '21 source voltage Vcc through N-channel MOSFET Q47. Coupled to circuit ground voltage via Q48.

The common sense amplifier C3A includes (n+1)/4 unit circuits UC3A provided corresponding to four groups of complementary data lines.

These unit circuits and complementary data lines DO/DO~Dn-L
) between the above-mentioned switch MOSFET pair Q13.
Q14 to Q27 and Q2B are provided.

One of each switch MOS FET pair is coupled to the corresponding complementary data line, and the other is connected to the unit circuit UC3A of the common sense amplifier C3A corresponding to each group.
Commonly connected to the human output node of.

The unit circuit UC3A of the common sense amplifier C5A has the same configuration as the unit circuit USA of the sense amplifier SA, as exemplarily shown in FIG. That is, each unit circuit UC3A of the common sense amplifier C5A has a P channel/l
/MO5FETQ5. Q6 and N channel MOsFE
TQ9. It consists of a CMOS launch circuit consisting of QI O, the input/output nodes of which are coupled to the other of the four switch MOSFET pairs in the corresponding group, as described above. Although not particularly developed, these common sense amplifiers cs
The amplification MO5FET that constitutes the unit circuit UC3A of A is:
Designed to have relatively large conductance.

The sources of the P-channel type and N-channel type amplification MOSFETs constituting the common sense amplifier C3A are commonly connected to the common source lines CP and CN, respectively. These common sources 1lCP and CN can be connected to P-channel MOSFETs QI, Q2 in parallel form, but are not particularly limited.
are connected to the power supply voltage Vcc via parallel N-channel MOSFETs Q45. Coupled to circuit ground voltage via Q46.

Drive MOSFET Q1 provided between the common source lines CP and SP and the circuit power supply voltage Vcc
.

Q3 and Q2. A common sense amplifier C is connected to the gate of Q4.
3A and timing signals φpal and φpa'l for activating the sense amplifier SA and inverted signals by inverter circuits N1 and N2 are supplied, respectively. Further, drive MOSFET Q45. is provided between the common source lines CN and SN and the circuit ground potential. Q47 and Q
46. The gate of Q48 receives the timing signal φpa.
l and φpa2 are respectively supplied. These timing signals φpal.

φpa"l is formed with a predetermined time difference. As a result, the common sense amplifier C3A and the sense amplifier SA
The operation is performed in two stages.

That is, in the first stage where the timing signal φpal is supplied, the MOSFETs QI, Q3, Q45 . Q47 is turned on, and due to its current limiting action, the minute read signal applied from the memory cell to the corresponding complementary data line is amplified without undergoing any undesired bell fluctuations.

In addition, the common sense amplifier C3A and the sense amplifier S
After the potential difference between the complementary data lines is increased to some extent by the amplification operation of A, the timing signal φpa2 is supplied. This allows the MO with relatively large conductance to
5FETQ2. Q4 and Q46°Q48 are turned on. The amplification operation of common sense amplifier C8A and sense amplifier SA is performed by MOSFETQ2. Q4 and Q46. Q48
is turned on, and the level of the complementary data line rapidly changes to high or low level.

In this way, by performing the amplification operations of the common sense amplifier C5A and the sense amplifier SA in two stages, it is possible to read stored data at high speed while preventing undesired level changes in the complementary data lines. .

By the way, in the dynamic RAM of this embodiment, as described above, a unit circuit of the common sense amplifier C5A is provided for each group of four sets of complementary data lines. The unit circuit UCSA of these common sense amplifiers C3A is
They are selectively connected to a set of complementary data lines in a corresponding group in accordance with selection signals yO-y3 formed by bit column address signals. This complementary data line is a complementary data line specified by a column address signal, or a complementary data line whose lower two bits have the same column address as the specified complementary data line.

That is, in memory access of the dynamic RAM, the unit circuit USA of the corresponding sense amplifier SA and the unit circuit UCSA of the common sense amplifier C3A are simultaneously connected to the complementary data line specified by the column address signal.

As mentioned above, the amplifying MOSFETs constituting the unit circuit USA of the sense amplifier SA are designed to have relatively small conductance, and the common sense amplifier CSA
The amplification MOS F E that constitutes the unit circuit UC3A of
T is designed to have a relatively large conductance. Further, each unit circuit of the common sense amplifier C3A is supplied with its operating current via common source lines CP and CN that are separate from the sense amplifier SA.

As described above, in the dynamic RAM of this embodiment, the complementary data line DO forming the memory array M-ARY is
A unit circuit USA of sense amplifier SA is provided corresponding to -Do to Dn-Dn, and a unit circuit UC of common sense amplifier C3A is provided for each group of four sets of complementary data lines.
3A is provided. The unit circuits UCSA of these common sense amplifiers C5A are selectively coupled to a set of complementary data lines in the group according to the column address signal of the lower two bits, and the unit circuits UCSA of the sense amplifiers SA provided corresponding to the complementary data lines are selectively coupled to a set of complementary data lines in the group. Together with the unit circuit USA, it is put into an operating state.

Further, an operating current is supplied to the unit circuit of the sense amplifier SA and the unit circuit of the common sense amplifier CS A, which are simultaneously activated, through respective common source lines CP, CN and SP, SN. Therefore, the minute read signal output from the memory cell MC coupled to the complementary data line specified by the column address signal is
Since the signal is rapidly amplified by the unit circuits of the sense amplifier SA and the common sense amplifier C5A that are activated at the same time, the read operation of the dynamic RAM is accelerated. In addition, in the refresh operation mode of the dynamic RAM, the common sense amplifier CSA is not activated and is connected to the selected word line.
The memory 1"n information of the memory cell MC of il is relatively It is refreshed slowly. Therefore, power consumption in the dynamic RAM refresh operation mode is reduced.

As shown in the above embodiment, the present invention is a dynamic type memory in which the memory is composed of one-element CD dynamic memory cells and sense amplifier circuits are provided corresponding to complementary data lines constituting the memory array. R
By applying it to AM, the following effects can be obtained. That is, (1) a sense amplifier circuit consisting of an amplification MOSFET with relatively small conductance is provided corresponding to each complementary data line constituting the memory array, and the plurality of complementary data lines are divided into a predetermined number. A common sense amplifier circuit is provided corresponding to each group, which is composed of amplifying MOS FETs with relatively large conductance and is selectively coupled to a set of complementary data lines in the corresponding group according to a predetermined address signal. By doing so, the minute read signal output from the specified memory cell is
The sense amplifier circuit and the common sense amplifier that are activated at the same time have the advantage of being able to amplify at a relatively high speed.

(2) By supplying the operating current to the sense amplifier circuit and the common sense amplifier circuit through separate common source lines, it is possible to reduce the rise delay of the operating current due to the distributed resistance of the common source line. The effect is that it can be suppressed.

(3) The above (11) and (2) provide the effect of speeding up the read operation of the dynamic RAM.

(4) In the above (Section 11), the common sense amplifier circuit is not activated in the refresh operation mode, and the f and Q information of a plurality of memory cells coupled to a selected word line is transmitted with a relatively small conductance. % increase M O
Power consumption in the refresh L/TS operation mode can be reduced by refreshing the dynamic RAM relatively quickly over the entire refresh/no-sh access period using only the sense amplifier circuit consisting of SFF and T. This has the effect of reducing the power consumption of the dynamic RAM.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and may be modified in various ways without departing from the gist of the invention.) Not even. For example, in this embodiment, the unit circuit UC3A of the common sense amplifier CS A is provided for each group of four sets of complementary data lines. It is not limited by. Furthermore, the unit circuit of the sense amplifier SA and the common sense amplifier C3A is a P-channel MOSFET or an N-channel MOS FET.
It may be composed only of T. In the embodiment shown in FIG. 1, the conductance of the amplifying MOS FET constituting the unit circuit to the sense amplifier S is made relatively small, and the conductance of the amplifying MOS FET constituting the common sense amplifier C3A is
Although the conductance of FET is made relatively large,
Amplify both sense amplifier circuits with the same conductance M O
It may be configured by S FET. Furthermore, the second
The dynamic RAM shown in the figure has a special configuration and control signals that allow, for example, a memory array to be configured with multiple memory mantles, or to simultaneously write or read multiple bits. combination L etc.,
Twelve embodiments are possible.

The above description will mainly focus on the invention made by the inventors of the present application and the field of application that provided its background.
Although the description has been made for a case where the present invention is applicable to the above, the present invention is not limited thereto, and can be applied to various other dynamic RAMs and digital devices including such dynamic RAMs, for example. The present invention is widely applicable to at least a dynamic RAM whose memory array is constituted by dynamic memory cells and a sense amplifier circuit is provided corresponding to its complementary data line, and a semiconductor device including such a dynamic RAM. .

[Effects of the Invention] The effects obtained by the typical inventions disclosed in this application are as follows. A sense amplifier circuit consisting of a MOS FET with a relatively small conductance is provided, and an amplification circuit with a relatively large conductance is provided corresponding to each group obtained by dividing the plurality of complementary data lines into a predetermined number. By providing a common sense amplifier circuit consisting of MOS FETs and selectively connected to a set of complementary data lines in a corresponding group according to a predetermined address signal, it is possible to speed up the read operation of the dynamic RAM. , it is possible to reduce the power consumption of the dynamic RAM in the refresh operation mode.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
2 is a block diagram showing an example of a dynamic RAM including the sense amplifier circuit and common sense amplifier circuit of FIG. 1. FIG. . C3A...Common sense amplifier circuit, SA...Sense amplifier circuit, M-ARY...Memory array, C8W...
...Column switch. USA...Sense amplifier unit circuit, UC3A...Common sense amplifier unit circuit, MC...Memory cell, Cs
...Information storage capacitor, Qm" -Address selection MOSFET, Ql ~ Q8...P channel MO
SFET, Q9~Q48...N channel MOSFE
T, Nl, N2... Inverter circuit. PDCR...Predecoder, RDCR...Row address decoder, CDCR...Column address decoder, RADB...Row address buffer, AMX...
・Address multiplexer, CA D B ・Column address buffer, MA ・Main amplifier, DOt
3...Data output cover sofa, DIB...Data input cover sofa, TC...Evening/f timing control circuit, REFC
...Refresh counter. Representative Patent Attorney Katsuma Ogawa 18.1 Figure 2

Claims (1)

[Claims] 1. A memory array consisting of a plurality of word lines, a plurality of complementary data lines, and a plurality of memory cells arranged in a grid at the intersections of these word lines and complementary data lines, and the complementary data lines. multiple sense amplifier circuits provided corresponding to the
A plurality of common senses provided corresponding to groups formed by dividing the plurality of complementary data lines into a predetermined number each, and selectively connected to a set of complementary data lines in the corresponding group according to a predetermined address signal. A dynamic RAM characterized by being equipped with an amplifier circuit. 2. A common source for supplying operating current is provided between the plurality of sense amplifier circuits and the circuit power supply voltage and ground potential, and between the plurality of common sense amplifier circuits and the circuit power supply voltage and ground potential. 2. The dynamic RAM according to claim 1, wherein each line is provided. 3. Amplification MOSFET that constitutes the above sense amplifier circuit
has a relatively small conductance to the extent that information stored in the memory cell can be refreshed during the access period of the dynamic RAM, and the amplifying MOSFETs constituting the common sense amplifier circuit are selectively connected complementary MOSFETs. Dynamic type R according to claim 1, characterized in that it has a relatively large conductance so as to be able to amplify a read signal from a memory cell coupled to a data line at high speed.
A.M.