JPS63147742U - - Google Patents
Info
- Publication number
- JPS63147742U JPS63147742U JP3857787U JP3857787U JPS63147742U JP S63147742 U JPS63147742 U JP S63147742U JP 3857787 U JP3857787 U JP 3857787U JP 3857787 U JP3857787 U JP 3857787U JP S63147742 U JPS63147742 U JP S63147742U
- Authority
- JP
- Japan
- Prior art keywords
- microprogram
- register
- contents
- address
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013507 mapping Methods 0.000 claims description 3
- 238000004590 computer program Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第1図はこの考案の一実施例を示す図、第2図
は従来のマイクロプログラム制御装置を説明する
ための図である。
図において、1は記憶装置、2はメモリ入力レ
ジスタ、3はメモリ出力レジスタ、4は命令レジ
スタ、5は演算レジスタ、6は演算器、7は出力
回路、8はマツピング回路、9はカウンタ、10
はセレクタ、11はマイクロプログラムメモリ、
12はマイクロ命令レジスタ、13はスタツク、
14は試験制御回路である。なお、図中、同一符
号は同一又は相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram for explaining a conventional microprogram control device. In the figure, 1 is a storage device, 2 is a memory input register, 3 is a memory output register, 4 is an instruction register, 5 is a calculation register, 6 is a calculation unit, 7 is an output circuit, 8 is a mapping circuit, 9 is a counter, 10
is a selector, 11 is a microprogram memory,
12 is a microinstruction register, 13 is a stack,
14 is a test control circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ジスタと、このレジスタの内容により実行するマ
イクロプログラムのアドレスを強制的に分岐させ
るマツピング回路と、強制分岐先での処理終了後
強制分岐の前の処理に戻るために復帰アドレスを
保持するスタツクと、電子計算機のレジスタ及び
メモリの内容を電子計算機の出力回路を介して出
力するマイクロプログラムを記憶したマイクロプ
ログラムメモリとを有することを特徴とするマイ
クロプログラム制御装置。 A register that indicates the test mode of the computer program, a mapping circuit that forcibly branches the address of the microprogram to be executed based on the contents of this register, and a mapping circuit that forcibly branches the address of the microprogram to be executed based on the contents of this register, and returns to the process before the forced branch after completing processing at the forced branch destination. 1. A microprogram control device comprising: a stack that holds a return address; and a microprogram memory that stores a microprogram that outputs the contents of a register and memory of an electronic computer via an output circuit of the computer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3857787U JPS63147742U (en) | 1987-03-17 | 1987-03-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3857787U JPS63147742U (en) | 1987-03-17 | 1987-03-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63147742U true JPS63147742U (en) | 1988-09-29 |
Family
ID=30850951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3857787U Pending JPS63147742U (en) | 1987-03-17 | 1987-03-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63147742U (en) |
-
1987
- 1987-03-17 JP JP3857787U patent/JPS63147742U/ja active Pending
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