JPH0212800U - - Google Patents
Info
- Publication number
- JPH0212800U JPH0212800U JP8862088U JP8862088U JPH0212800U JP H0212800 U JPH0212800 U JP H0212800U JP 8862088 U JP8862088 U JP 8862088U JP 8862088 U JP8862088 U JP 8862088U JP H0212800 U JPH0212800 U JP H0212800U
- Authority
- JP
- Japan
- Prior art keywords
- address
- write
- read
- data
- address counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Advance Control (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図は第１図のメモリ回路１０のデータと
アドレスとの説明図、第３図はプツシユ動作を説
明する波形図、第４図はポツプ動作を説明する波
形図、第５図は従来装置の構成ブロツク図、第６
図は第５図のメモリ回路１０のデータとアドレス
との説明図である。
１０……メモリ回路、２０，７０……信号発生
回路、３０……書込みアドレスカウンタ、４０…
…読出しアドレスカウンタ、５０……アドレスセ
レクタ、６０……出力レジスタ。
1 is a configuration block diagram showing one embodiment of the present invention, FIG. 2 is an explanatory diagram of data and addresses of the memory circuit 10 of FIG. 1, FIG. 3 is a waveform diagram illustrating push operation, and FIG. The figure is a waveform diagram explaining the pop operation, Figure 5 is a block diagram of the conventional device, and Figure 6 is a waveform diagram explaining the pop operation.
The figure is an explanatory diagram of data and addresses of the memory circuit 10 of FIG. 5. 10...Memory circuit, 20, 70...Signal generation circuit, 30...Write address counter, 40...
...Read address counter, 50...Address selector, 60...Output register.
Claims (1)
ドレスを記憶する書込みアドレスカウンタと、 当該メモリ回路に対する読出し動作におけるア
ドレスを記憶する読出しアドレスカウンタと、 前記書込みアドレスカウンタと読出しアドレス
カウンタのアドレス信号を切替えて前記メモリ回
路に送るアドレスセレクタと、 プツシユ信号若しくはポツプ信号を入力して後
入れ先出し記憶による制御信号を送る信号発生回
路と、 よりなるスタツク回路において、 前記メモリ回路のデータ出力端に設けられた出
力レジスタと、 この出力レジスタの制御を前記信号発生回路と
同期して以下の制御をする制御手段を設け、 前記書込みアドレスカウンタの内容をラストデ
ータの一つ後のアドレスとし、前記読出しアドレ
スカウンタの内容をラストデータの一つ前のアド
レスとしたことを特徴とするスタツク回路。 プツシユ信号が入力されたときは、メモリ回
路の書込みアドレスカウンタに示されたアドレス
に入力されたデータを書込むと共に、出力レジス
タにも当該入力データを書込むこと。 ポツプ信号が入力されたときは、出力レジス
タの内容を直ちにデータとして読出し、メモリ回
路の読出しアドレスカウンタに示されたアドレス
のデータを読出し、当該ポツプサイクルの終了近
傍でこの読出されたデータを出力レジスタに書込
むこと。[Claims for Utility Model Registration] A memory circuit, a write address counter that stores an address in a write operation to the memory circuit, a read address counter that stores an address in a read operation to the memory circuit, and the write address counter and the read address counter. A stack circuit comprising: an address selector that switches an address signal of an address counter and sends it to the memory circuit; and a signal generation circuit that inputs a push signal or a pop signal and sends a control signal based on last-in, first-out storage; An output register provided at the data output terminal, and a control means for synchronizing the control of this output register with the signal generation circuit to perform the following control, the contents of the write address counter are set to the address immediately after the last data. A stack circuit characterized in that the content of the read address counter is the address immediately before the last data. When the push signal is input, write the input data to the address indicated by the write address counter of the memory circuit, and also write the input data to the output register. When a pop signal is input, the contents of the output register are immediately read as data, the data at the address indicated in the read address counter of the memory circuit is read, and the read data is transferred to the output register near the end of the pop cycle. To write.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8862088U JPH079280Y2 (en) | 1988-07-04 | 1988-07-04 | Stack circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8862088U JPH079280Y2 (en) | 1988-07-04 | 1988-07-04 | Stack circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0212800U true JPH0212800U (en) | 1990-01-26 |
| JPH079280Y2 JPH079280Y2 (en) | 1995-03-06 |
Family
ID=31313180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8862088U Expired - Lifetime JPH079280Y2 (en) | 1988-07-04 | 1988-07-04 | Stack circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079280Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009176177A (en) * | 2008-01-28 | 2009-08-06 | Meidensha Corp | Programmable controller |
-
1988
- 1988-07-04 JP JP8862088U patent/JPH079280Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009176177A (en) * | 2008-01-28 | 2009-08-06 | Meidensha Corp | Programmable controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079280Y2 (en) | 1995-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0212800U (en) | ||
| JPS5832476U (en) | microprocessor analyzer | |
| JPH0191959U (en) | ||
| JPH0218149U (en) | ||
| JPS5881654U (en) | arithmetic processing unit | |
| JPS5894026U (en) | small electronic calculator | |
| JPS6087050U (en) | data transfer control device | |
| JPS59144960U (en) | button telephone device | |
| JPS5911355U (en) | electronic cash register | |
| JPS59178734U (en) | text processing device | |
| JPH0322472U (en) | ||
| JPH022751U (en) | ||
| JPS6130107U (en) | Flowchart programmable controller | |
| JPH0334102U (en) | ||
| JPS63147741U (en) | ||
| JPH0313504U (en) | ||
| JPS6056653U (en) | Folding position display device for paper folding machine | |
| JPS6181700U (en) | ||
| JPH0452252U (en) | ||
| JPS6095650U (en) | Stack overflow detection circuit | |
| JPS59160347U (en) | audio output device | |
| JPS60180061U (en) | audio program calculator | |
| JPH01116844U (en) | ||
| JPS5865090U (en) | Character generation circuit | |
| JPS6010334U (en) | Erroneous operation prevention confirmation circuit |