JPS6314475A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6314475A JPS6314475A JP15825686A JP15825686A JPS6314475A JP S6314475 A JPS6314475 A JP S6314475A JP 15825686 A JP15825686 A JP 15825686A JP 15825686 A JP15825686 A JP 15825686A JP S6314475 A JPS6314475 A JP S6314475A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- polycrystalline silicon
- emitter
- photolithography
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000000206 photolithography Methods 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000004411 aluminium Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に高周波特性
のきめ手となる微細化及び高破壊耐量の為のエミヅタバ
ラスト抵抗を簡単に製造する事のできる高周波トランジ
スタの製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for easily manufacturing an emitter ballast resistor for miniaturization and high breakdown resistance, which are the key to high frequency characteristics. This invention relates to a method for manufacturing high-frequency transistors that can be manufactured.
従来、この種の高周波トランジスタは、エミヴタ形成・
エミ・フタバラスト抵抗・コンタクトホールの開口はそ
れぞれ別々のフォトリングラフィ工程を用いて行ってい
た為に、微細化はフォトリンクラフィの梢既によって決
まり一定の限界があった。Conventionally, this type of high-frequency transistor has an emitter formation and
Since openings for the emitter, ballast resistor, and contact hole were made using separate photolithography processes, there was a certain limit to miniaturization, which was determined by the size of the photolithography process.
上述した従来技術の製造方法では微細化を行う為には、
フォ) IJンクラフィの精度を上ける昼餐がbる。一
定のフォトリンクラフィの条件下で微細化を行う手法と
してセルフアライメント技術があるが、高耐圧高周波ト
ランジスタ構造では適用できないか又、適用でき又も非
常に多くの工程増となってしまうという欠点がある。In the conventional manufacturing method described above, in order to achieve miniaturization,
4) There is a lunch that improves the accuracy of IJ Nkrafi. Self-alignment technology is a method for miniaturization under certain photolinkage conditions, but it either cannot be applied to high-voltage, high-frequency transistor structures, or, even if it can be applied, it has the drawback of requiring a large number of additional steps. be.
本発明の半導体装置の製造方法は、
高濃度にドープされた多結晶シリコンを用いて不純物を
拡散する半導体装置の製造方法であって、半導体表面上
に形成された二酸化シリコンに第1の開口部を形成する
工程と、この開口をシリコン・ナイトライド膜で覆った
後その一部をエツチングする工程と、その上に多結晶ク
リコンを堆積させイオン注入により不純物を高濃度にド
ープさせその後1部を除去した後に熱処理をしてクヤロ
ージャンクシlンを形成する工程と、ジャンクションを
形成した後に酸素雰囲気中で熱処理する工程と、
多結晶シリコン及び半導体基板とコンタクトを取るため
のエツチング工程と、その上からAt配線を行う工程と
を含む事を特徴とする。A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which impurities are diffused using heavily doped polycrystalline silicon, the method comprising: forming a first opening in silicon dioxide formed on a semiconductor surface; , a step of covering this opening with a silicon nitride film and then etching a part of it, depositing polycrystalline silicon on top of it, doping it with impurities at a high concentration by ion implantation, and then etching a part of it. A process of heat-treating after removal to form a Kuyaro junction film, a process of heat-treating in an oxygen atmosphere after forming a junction, an etching process to make contact with polycrystalline silicon and a semiconductor substrate, and The method is characterized by including a step of performing At wiring from above.
次に本発明を工程フローにより説明する。 Next, the present invention will be explained using a process flow.
第1図は本発明の一実施例の製造工程断面図でめる。半
導体基板3にペース領域2を形成した後に二酸化シリコ
ン膜lを形成する(第1図(a))。FIG. 1 is a cross-sectional view of the manufacturing process of an embodiment of the present invention. After forming the space region 2 on the semiconductor substrate 3, a silicon dioxide film 1 is formed (FIG. 1(a)).
ペース仙域上の二酸化クリコン膜lを部分的にフォトリ
ングラフィを用いて開口4を形成する(第1図(b))
。An opening 4 is formed partially in the cricon dioxide film l on the pace sacrum using photolithography (Fig. 1(b)).
.
全面にシリコン・ナテライド膜5をつけ(第1図(C1
)、その1部をフォトリングラフィを用いてエツチング
する。A silicon nateride film 5 is applied to the entire surface (Fig. 1 (C1
), a part of which is etched using photolithography.
その後全面に多結晶クリコンロを成長させイオン注入、
またはガス拡散を用いて不純物を高濃度にドープさせる
(第1図(d))。After that, polycrystalline crystals are grown on the entire surface and ions are implanted.
Alternatively, impurities are doped at a high concentration using gas diffusion (FIG. 1(d)).
多結晶シリコンをフォトリングラフィを用いてエツチン
グしく第1図(e) ) 、その後に熱処理を行い多結
晶シリコンを通して不純物を拡散し、エミッタ領域7を
形成する(第1図(e))。The polycrystalline silicon is etched using photolithography (FIG. 1(e)), and then heat treatment is performed to diffuse impurities through the polycrystalline silicon to form an emitter region 7 (FIG. 1(e)).
続いて不純物拡散時より低い温度で酸化させ多結晶シリ
コン6の表面を二酸化シリコン8に変化させる(第1図
(f))。Subsequently, the polycrystalline silicon 6 is oxidized at a lower temperature than during impurity diffusion to change the surface of the polycrystalline silicon 6 to silicon dioxide 8 (FIG. 1(f)).
次に酸化石れた多結晶シリコンをマスクにしてシリコン
ナテライド膜5をホットリン酸の様なりエトエッチによ
り除去しコンタクトホール9を開口する(第1図(g)
)。Next, using the oxidized polycrystalline silicon as a mask, the silicon nateride film 5 is removed by etching with hot phosphoric acid to open a contact hole 9 (see Fig. 1(g)).
).
その後、フォトリソグラフィを用いてエミッタコンタク
トホールを多結晶シリコン上に開口したアトアルミニウ
ム10でペース、エミッタ領域を形成する(第1図(h
))。Thereafter, an emitter region is formed using atto aluminum 10 with an emitter contact hole opened on the polycrystalline silicon using photolithography (see Fig. 1 (h).
)).
第2図は第1図に示す製造方法によって作られた高耐圧
高周波パワートランジスタを示し、第2図(alはその
上面図、同図(blはその側面図、同図(C1はその断
面図である。Figure 2 shows a high-voltage, high-frequency power transistor manufactured by the manufacturing method shown in Figure 1. It is.
以上説明した様に本発明は、多結晶シリコン。 As explained above, the present invention relates to polycrystalline silicon.
シリコンナテライド膜、二酸化7リコン膜をそれぞれの
特徴を生かして組み合わせる事によシ、セルフアライメ
ントによる微細化及びエミッタバラスト抵抗の形成を簡
単な工程にて行う事がでさる効果かりる。具体的には、
従来のフォトリングラフイレベルの2倍以上の微細化を
行うことができるOBy combining the silicon nateride film and the 7-licon dioxide film by taking advantage of their respective characteristics, miniaturization through self-alignment and formation of the emitter ballast resistor can be achieved in a simple process. in particular,
O allows for miniaturization that is more than twice the level of conventional photophosphorography.
第1図1a)〜(h)は本発明の一実施例の工程断面図
、第2因(al〜(C1は第1図の製造方法を用いて作
られた高耐圧高周波パワートランジスタの上面図、側面
図および断面図である。
l・・・・・・二酸化シリコン膜、2・・・・・・ベー
ス軸域、3・・・・・・半導体基板、4・・・用開口、
5・・・・・・シリコンナテライド膜、6・・・・・・
多結晶シリコン、7・・・・・・エミνり領域、s・川
・・二酸化シリコン、9・・川・コンタクトホール、1
0・旧・・アルミニニーム、21・・・・・・エミッタ
At[極、22.23・・・m:酸化シリコン膜、24
・・・・・・多結晶シリコン(エミッタバラスト抵抗)
、25・・・・・・エミッタ領域、26・・・・・・ペ
ース1jl、27・・・・・・ペースAt[極。
タ タつレタクTホーノル第1図1a to 1h are process cross-sectional views of one embodiment of the present invention, and the second factor (al to (C1) is a top view of a high-voltage, high-frequency power transistor manufactured using the manufacturing method shown in , a side view and a cross-sectional view. 1... Silicon dioxide film, 2... Base axis region, 3... Semiconductor substrate, 4... Opening for...
5... Silicon nateride film, 6...
Polycrystalline silicon, 7... emitter region, s, river, silicon dioxide, 9... river, contact hole, 1
0. Old... Aluminum, 21... Emitter At [pole, 22.23... m: Silicon oxide film, 24
・・・・・・Polycrystalline silicon (emitter ballast resistor)
, 25...Emitter region, 26...Pace 1jl, 27...Pace At [pole. Figure 1
Claims (1)
拡散する半導体装置の製造方法であって、半導体表面上
に形成された二酸化シリコンに第1の開口部を形成する
工程と、上記開口をシリコン・ナイトライド膜で覆つた
後その一部をエッチングする工程と、その上に多結晶シ
リコンを堆積させイオン注入により不純物を高濃度にド
ープさせその後1部を除去した後に熱処理をしてシャロ
ージャンクシヨンを形成する工程と、ジャンクションを
形成した後に酸素雰囲気中で熱処理をする工程と、多結
晶シリコン及び半導体基板とコンタクトを取る為のエツ
チング工程と、その上からAl配線を行う工程とを含む
事を特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which impurities are diffused using heavily doped polycrystalline silicon, the method comprising: forming a first opening in silicon dioxide formed on a semiconductor surface;・A process of covering with a nitride film and then etching a part of it, depositing polycrystalline silicon on top of it, doping it with impurities at a high concentration by ion implantation, and then removing a part and then heat-treating it to form a shallow junction. A process of forming a junction, a process of heat treatment in an oxygen atmosphere after forming a junction, an etching process to make contact with polycrystalline silicon and a semiconductor substrate, and a process of forming an Al wiring from above. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15825686A JPS6314475A (en) | 1986-07-04 | 1986-07-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15825686A JPS6314475A (en) | 1986-07-04 | 1986-07-04 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6314475A true JPS6314475A (en) | 1988-01-21 |
Family
ID=15667650
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15825686A Pending JPS6314475A (en) | 1986-07-04 | 1986-07-04 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6314475A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5688358A (en) * | 1979-12-21 | 1981-07-17 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS56152265A (en) * | 1980-04-25 | 1981-11-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1986
- 1986-07-04 JP JP15825686A patent/JPS6314475A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5688358A (en) * | 1979-12-21 | 1981-07-17 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS56152265A (en) * | 1980-04-25 | 1981-11-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
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