JPS6314475A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable high-frequency power transistors having high dielectric strength to be constructed finely with self-alignment and provided with an emitter ballast resistance through simple processes, by utilizing polycrystalline silicon, a silicon nitride film and a silicon dioxide film in combination. CONSTITUTION:After a base region 2 is provided in a semiconductor substrate 3, a silicon dioxide film 1 is formed on the substrate. The silicon dioxide film 1 is partially etched by the photolithography to form apertures 4. A silicon nitride film 5 is formed to cover all over the substrate and is etched by the photolithography. Then, polycrystalline silicon 6 is grown thereon and is doped. The polycrystalline silicon 6 is then etched and heat treated to provide emitter regions 7. Subsequently, the surface of the polycrystalline silicon 6 is converted into silicon dioxide 8, which is used as a mask for forming contact holes 9 in the silicon nitride film 5. Emitter contact holes are formed on the polycrystalline silicon by the photolithography. Finally, base and emitter electrodes are formed of aluminium.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for easily manufacturing an emitter ballast resistor for miniaturization and high breakdown resistance, which are the key to high frequency characteristics. This invention relates to a method for manufacturing high-frequency transistors that can be manufactured.

[Conventional technology]

Conventionally, this type of high-frequency transistor has an emitter formation and
Since openings for the emitter, ballast resistor, and contact hole were made using separate photolithography processes, there was a certain limit to miniaturization, which was determined by the size of the photolithography process.

[Problem that the invention seeks to solve]

In the conventional manufacturing method described above, in order to achieve miniaturization,
4) There is a lunch that improves the accuracy of IJ Nkrafi. Self-alignment technology is a method for miniaturization under certain photolinkage conditions, but it either cannot be applied to high-voltage, high-frequency transistor structures, or, even if it can be applied, it has the drawback of requiring a large number of additional steps. be.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which impurities are diffused using heavily doped polycrystalline silicon, the method comprising: forming a first opening in silicon dioxide formed on a semiconductor surface; , a step of covering this opening with a silicon nitride film and then etching a part of it, depositing polycrystalline silicon on top of it, doping it with impurities at a high concentration by ion implantation, and then etching a part of it. A process of heat-treating after removal to form a Kuyaro junction film, a process of heat-treating in an oxygen atmosphere after forming a junction, an etching process to make contact with polycrystalline silicon and a semiconductor substrate, and The method is characterized by including a step of performing At wiring from above.

〔Example〕

Next, the present invention will be explained using a process flow.

FIG. 1 is a cross-sectional view of the manufacturing process of an embodiment of the present invention. After forming the space region 2 on the semiconductor substrate 3, a silicon dioxide film 1 is formed (FIG. 1(a)).

An opening 4 is formed partially in the cricon dioxide film l on the pace sacrum using photolithography (Fig. 1(b)).
.

A silicon nateride film 5 is applied to the entire surface (Fig. 1 (C1
), a part of which is etched using photolithography.

After that, polycrystalline crystals are grown on the entire surface and ions are implanted.
Alternatively, impurities are doped at a high concentration using gas diffusion (FIG. 1(d)).

The polycrystalline silicon is etched using photolithography (FIG. 1(e)), and then heat treatment is performed to diffuse impurities through the polycrystalline silicon to form an emitter region 7 (FIG. 1(e)).

Subsequently, the polycrystalline silicon 6 is oxidized at a lower temperature than during impurity diffusion to change the surface of the polycrystalline silicon 6 to silicon dioxide 8 (FIG. 1(f)).

Next, using the oxidized polycrystalline silicon as a mask, the silicon nateride film 5 is removed by etching with hot phosphoric acid to open a contact hole 9 (see Fig. 1(g)).
).

Thereafter, an emitter region is formed using atto aluminum 10 with an emitter contact hole opened on the polycrystalline silicon using photolithography (see Fig. 1 (h).
)).

Figure 2 shows a high-voltage, high-frequency power transistor manufactured by the manufacturing method shown in Figure 1. It is.

〔Effect of the invention〕

As explained above, the present invention relates to polycrystalline silicon.

By combining the silicon nateride film and the 7-licon dioxide film by taking advantage of their respective characteristics, miniaturization through self-alignment and formation of the emitter ballast resistor can be achieved in a simple process. in particular,
O allows for miniaturization that is more than twice the level of conventional photophosphorography.

[Brief explanation of drawings]

1a to 1h are process cross-sectional views of one embodiment of the present invention, and the second factor (al to (C1) is a top view of a high-voltage, high-frequency power transistor manufactured using the manufacturing method shown in , a side view and a cross-sectional view. 1... Silicon dioxide film, 2... Base axis region, 3... Semiconductor substrate, 4... Opening for...
5... Silicon nateride film, 6...
Polycrystalline silicon, 7... emitter region, s, river, silicon dioxide, 9... river, contact hole, 1
0. Old... Aluminum, 21... Emitter At [pole, 22.23... m: Silicon oxide film, 24
・・・・・・Polycrystalline silicon (emitter ballast resistor)
, 25...Emitter region, 26...Pace 1jl, 27...Pace At [pole. Figure 1

Claims (1)

[Claims] A method for manufacturing a semiconductor device in which impurities are diffused using heavily doped polycrystalline silicon, the method comprising: forming a first opening in silicon dioxide formed on a semiconductor surface;・A process of covering with a nitride film and then etching a part of it, depositing polycrystalline silicon on top of it, doping it with impurities at a high concentration by ion implantation, and then removing a part and then heat-treating it to form a shallow junction. A process of forming a junction, a process of heat treatment in an oxygen atmosphere after forming a junction, an etching process to make contact with polycrystalline silicon and a semiconductor substrate, and a process of forming an Al wiring from above. A method for manufacturing a featured semiconductor device.