JPS63132457A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS63132457A
JPS63132457A JP27856286A JP27856286A JPS63132457A JP S63132457 A JPS63132457 A JP S63132457A JP 27856286 A JP27856286 A JP 27856286A JP 27856286 A JP27856286 A JP 27856286A JP S63132457 A JPS63132457 A JP S63132457A
Authority
JP
Japan
Prior art keywords
layer
conductive layer
insulating layer
conductive
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27856286A
Other languages
Japanese (ja)
Inventor
Hiroyuki Akiba
秋葉 裕之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP27856286A priority Critical patent/JPS63132457A/en
Publication of JPS63132457A publication Critical patent/JPS63132457A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To increase the insulating property between layers of a multilayer interconnection, by oxidizing a part of a first conductive layer after the first conductive layer is formed on a substrate on which elements are formed, and by forming a second insulating layer and a second conductive layer thereon. CONSTITUTION:On a silicon substrate 1 on which a semiconductor element is formed, a metal layer 3 of aluminum is formed via a silicon oxide film 2. A first insulating film 4 is formed by oxidizing a part of the surface of the layer 3. Resist is spread on the whole surface of the layer 4, and the layer 3 is eliminated by photolithography leaving a pattern of the first conductive layer. After the resist is eliminated, a second insulating layer 7 is deposited on the substrate 1 via the film 2 containing the pattern 3. After the layer 7 is made flat, an insulating layer 9 between conductive layers is formed, and a contact hole 10 is made. Then a second conductive layer 11 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層配線を有する半導体装置の製造方法に係
り特に第1導電層と8g2導電、′1iとの間の良好な
層間絶縁層の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having multilayer wiring, and in particular to a method for manufacturing a semiconductor device having a multilayer wiring, and particularly to a method for forming a good interlayer insulating layer between a first conductive layer and an 8g2 conductive layer '1i. Regarding the manufacturing method.

〔従来の技術〕[Conventional technology]

微細技術の進歩に伴って多層配線を有する半導体装li
tが要求されているが、導電層間の絶縁性が問題となっ
ている。
With the progress of fine technology, semiconductor devices with multilayer wiring
t is required, but the insulation between conductive layers is a problem.

従来、導電層間を絶縁するために、第1導電を脅の上に
絶縁層を堆積させ、平担化の処理をした後、第2導心層
を形成する方法がある。すなわち、半導体素子が形成さ
れた半導体基板上にシリコンまたは鋼等を含むアルミ合
金の導電層を形成し、所望の配線パターンに従って第1
導電層を形成する。
Conventionally, in order to insulate between conductive layers, there is a method of depositing an insulating layer on a first conductive layer, flattening the layer, and then forming a second conductive layer. That is, a conductive layer of aluminum alloy containing silicon or steel is formed on a semiconductor substrate on which a semiconductor element is formed, and a first conductive layer is formed according to a desired wiring pattern.
Form a conductive layer.

次におよそ300’Oの低温プラズマ(至)法によりシ
リコン酸化物またはシリコン窒化膜等の絶縁膜を堆積さ
せる。その後堆積した絶縁膜とエツチングレイトがほぼ
等しい材料からなるレジストを塗布してパターンを形成
した後、RIEにより異方向性エツチングをして絶縁膜
表面を平担化する。この絶縁膜上に再度低温プラズマロ
法により絶縁膜を堆積させて導電層間の絶縁層を形成す
る。この上に第2Nj目のアルミ合金の導電ノーを形成
している。
Next, an insulating film such as silicon oxide or silicon nitride film is deposited by a low temperature plasma method at approximately 300'O. Thereafter, a resist made of a material having approximately the same etching rate as the deposited insulating film is applied to form a pattern, and then anisotropic etching is performed by RIE to flatten the surface of the insulating film. An insulating film is again deposited on this insulating film by low-temperature plasma deposition to form an insulating layer between the conductive layers. On top of this, a second Nj-th conductive layer of aluminum alloy is formed.

この様な従来の製造方法においては、導電層に用いる材
料のアルミニウムが、絶縁層堆積の際に加えられる熱に
より再結晶化して第1導電層の表面にヒロックと呼ばれ
る突起が生じていた。プラズマCVDのデポジション温
度は低温に設定されてはいるが、およそ200”C以上
では突起が形成されて第1導電層および第2導電層間で
ショートを起こし、導電層間の絶縁を破壊させていた。
In such conventional manufacturing methods, aluminum, which is a material used for the conductive layer, is recrystallized by the heat applied during the deposition of the insulating layer, resulting in protrusions called hillocks on the surface of the first conductive layer. Although the deposition temperature of plasma CVD is set at a low temperature, at temperatures above approximately 200"C, protrusions are formed, causing a short circuit between the first conductive layer and the second conductive layer, and destroying the insulation between the conductive layers. .

また、ヒロック発生の状態は素子が粗に配置されるとこ
ろに比べ密に配置されるメモリ部、ロジック部等では絶
縁膜が薄くされるため特にヒロック発生の問題が顕著に
なっている。
Furthermore, the problem of hillock occurrence is particularly pronounced in memory areas, logic areas, etc., where the elements are arranged more densely than in areas where the elements are arranged sparsely, because the insulating film is thinner.

また、本発明の層間絶縁層構造に関連する技術として特
公昭58−2451号の「多層配線構造体の製造方法」
で知られるような第1導電層を含む基板表面にアルミキ
レート化合物を含む溶液を塗布し、加熱処理してアルミ
ナ膜を形成する技術がある。しかしながらこの技術は導
電層表面に溶液を塗布する点、それを加熱処理する点が
本発明とは違った思想であり、更に加熱処理をする工程
はヒロックの発生を防止することはできず、本発明とは
目的・効果の点でも異なる技術である。
Further, as a technology related to the interlayer insulating layer structure of the present invention, ``Method for manufacturing multilayer wiring structure'' published in Japanese Patent Publication No. 58-2451
There is a technique known in the art in which a solution containing an aluminum chelate compound is applied to the surface of a substrate including a first conductive layer, and then heat-treated to form an alumina film. However, this technique differs from the present invention in that it applies a solution to the surface of the conductive layer and heat-treats it, and the process of heat-treating cannot prevent the occurrence of hillocks. Inventions are technologies that differ in purpose and effect.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の多層配線を有する半導体装置においては第1導電
層を形成した後、低温プラズマCVD法によシ、絶縁層
を堆積しているため、絶縁層にピンホールが形成された
シ、この(至)の熱により配線表面に突起が形成されて
いた。また2層以上の多層配線を形成する工程中、2層
目導電層からの金属不純物が拡散されていた。このよう
な突起や金属不純物拡散は、導電層間の絶縁性を破壊し
、半導体装置の信頼性を大きく低下させている。
In conventional semiconductor devices with multilayer wiring, after forming the first conductive layer, an insulating layer is deposited by low-temperature plasma CVD, so pinholes are formed in the insulating layer. ) had formed protrusions on the wiring surface. Further, during the process of forming a multilayer wiring having two or more layers, metal impurities from the second conductive layer were diffused. Such protrusions and metal impurity diffusion destroy the insulation between conductive layers, greatly reducing the reliability of semiconductor devices.

本発明は、4電層上の突起の形成、及び導電層における
金属不純物の拡散やピンホールの発生〜止し、4電層間
に安定な絶縁層を形成することを目的とする。
The object of the present invention is to prevent the formation of protrusions on the tetraelectric layer, the diffusion of metal impurities and the generation of pinholes in the conductive layer, and to form a stable insulating layer between the tetraelectric layers.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、半導体素子が形成された半導体基板上に第1
導電層を形成し、この4it層の少なくとも一部表面を
低温で酸化させて第1導電層表面に第1絶縁層を形成す
る。続いて第2絶縁層を形成した後、その上に第2配線
層を形成して多層配線を有する半導体装置を製造するも
のである。
According to the present invention, a first
A conductive layer is formed, and at least a portion of the surface of the 4it layer is oxidized at a low temperature to form a first insulating layer on the surface of the first conductive layer. Subsequently, after forming a second insulating layer, a second wiring layer is formed thereon to manufacture a semiconductor device having multilayer wiring.

〔作 用〕[For production]

本発明は上述したように、@1導電層の少なくとも一部
表面を低温で直接に酸化させて第1絶縁層を形成してお
シ、従来の第1導電層の上にプラズマCVD法で絶縁層
を堆積させる前に、導電層表面を第1絶縁層で保護して
いる。
As described above, the present invention forms a first insulating layer by directly oxidizing at least a portion of the surface of the @1 conductive layer at a low temperature, and insulates the first insulating layer by plasma CVD on the conventional first conductive layer. Before depositing the layers, the surface of the conductive layer is protected with a first insulating layer.

〔実施例〕〔Example〕

本発明の一冥施例を第1図を用いて説明する。 An embodiment of the present invention will be described with reference to FIG.

半導体素子が形成されたシリコン基板1上に素子領域と
導電層領域とを分離するためのシリコン酸化膜5i02
2を介して、シリコン、鋼等を含むアルールが形成され
ており、半導体素子のコンタクト部と第1導電層とを導
通させている。次に陽極酸化法により第1図すに示すよ
うにアルミ金属層3の一部表面を酸化して2000X以
下の膜厚のアルミ酸化物kl 203からなる第1絶縁
層4を形成する。
A silicon oxide film 5i02 for separating an element region and a conductive layer region on a silicon substrate 1 on which a semiconductor element is formed.
An allure containing silicon, steel, or the like is formed via 2, and conducts the contact portion of the semiconductor element and the first conductive layer. Next, as shown in FIG. 1, a part of the surface of the aluminum metal layer 3 is oxidized by an anodic oxidation method to form a first insulating layer 4 made of aluminum oxide Kl 203 having a thickness of 2000X or less.

陽極酸化の条件としては硫酸系、シュウ酸系、硫酸シュ
ウ酸混合液系等の電解液中においておよそ100〜20
0Vの電圧を付加し、室温で行なう。この陽極酸化はア
ルミ合金の金属層3表面に突起が1し成されない温度で
行ない、望ましくは200°C以下で行なうと良い。
The conditions for anodic oxidation are approximately 100 to 20
A voltage of 0V is applied and the test is carried out at room temperature. This anodic oxidation is carried out at a temperature at which no protrusions are formed on the surface of the aluminum alloy metal layer 3, preferably at 200°C or lower.

次にAl2O3の第1絶縁層4上にレジスト5を全面に
塗布し、第14電層の配線パターンに従って写真蝕刻工
程を行ない、第1図Cに示すように第1導電層6部分を
残してアルミ金属層3を除去する。続いて、レジスト5
を除去した後、第1導電層6を含む5to2膜2を介し
た半導体基板1の上に低温プラズマ曳法でシリコン酸化
物5102 sシリコン窒化物Si3N4等の第2絶縁
層7を堆積させる(第1図d)、、次に堆積した第2絶
縁1g!7とエツチングレイトがほぼ等しい材質からな
るレジスト8を選択して第2絶縁層7の上に塗布する(
第1図e)。続いてRIE (異方向性エツチング)法
を用いて笥1図fに示したようにエツチングを行ない第
2絶縁層7の表面を平担化する。次に再度低温プラズマ
圓法で第2絶縁層と同じ絶縁物を堆積させて導電層間絶
縁層9を形成する。続いて第1導を層と第2導電層との
導通のためのコンタクトホール10を開孔した後、シリ
コン、銅等を含むアルミニウム合金からなる第2導電層
11を形成する(第1図g)。更に多層にする場合は第
24醒層11の表面を第1.Jt層表面と同様に処理し
て、以上説明した工程を繰り返兄す。
Next, a resist 5 is applied to the entire surface of the first insulating layer 4 of Al2O3, and a photolithographic process is performed according to the wiring pattern of the 14th conductive layer, leaving only a portion of the first conductive layer 6 as shown in FIG. 1C. Remove the aluminum metal layer 3. Next, resist 5
After removing the first conductive layer 6, a second insulating layer 7 of silicon oxide 5102s silicon nitride Si3N4, etc. is deposited on the semiconductor substrate 1 via the 5to2 film 2 including the first conductive layer 6 by low-temperature plasma deposition. 1 d), then deposited second insulation 1g! A resist 8 made of a material having approximately the same etching rate as 7 is selected and coated on the second insulating layer 7 (
Figure 1 e). Subsequently, the surface of the second insulating layer 7 is planarized by etching using the RIE (Anisotropic Etching) method as shown in FIG. 1F. Next, the same insulator as the second insulating layer is deposited again using the low-temperature plasma method to form the conductive interlayer insulating layer 9. Subsequently, after forming a contact hole 10 for electrical connection between the first conductive layer and the second conductive layer, a second conductive layer 11 made of an aluminum alloy containing silicon, copper, etc. is formed (see Fig. 1g). ). If the layer is further multi-layered, the surface of the 24th layer 11 is made into the first layer. The surface of the Jt layer is treated in the same manner as the surface, and the process described above is repeated.

以上説明したような方法で製造した半導体装置は、第1
4電層を形成した後、この第1導電層の1よ 表面を突起が形成されない温度、好ましく200’0以
下で直接酸化して、酸化金属の絶縁膜を形成しているた
め、その後従来通りのプラズマ(至)法で、絶縁層を堆
積させても、導電層表面の突起物の発生を防止すること
ができる。この絶縁層は導電層自体を一部酸化させたも
のであり、配線との密着性は良好である。また導電層の
表面に形成された酸化金属の絶縁膜は緻密であるためそ
の上に画法で堆積される絶縁層に生じるピンホール等か
ら金属配線を保護できる。更に上層の導電層から導電層
間絶縁層へ金属不純物の拡散による絶縁破壊を下層導電
層を酸化した絶縁層で防止することができる。
The semiconductor device manufactured by the method explained above has the first
After forming the four conductive layers, the surface of the first conductive layer is directly oxidized at a temperature at which no protrusions are formed, preferably at 200'0 or less, to form an insulating film of metal oxide, and then oxidized as before. Even if the insulating layer is deposited using the plasma method described above, it is possible to prevent the formation of protrusions on the surface of the conductive layer. This insulating layer is a conductive layer itself partially oxidized, and has good adhesion to wiring. Furthermore, since the metal oxide insulating film formed on the surface of the conductive layer is dense, it is possible to protect the metal wiring from pinholes and the like that occur in the insulating layer deposited thereon by a drawing method. Furthermore, dielectric breakdown due to diffusion of metal impurities from the upper conductive layer to the conductive interlayer insulating layer can be prevented by the insulating layer obtained by oxidizing the lower conductive layer.

このように本発明の製造方法は第1導電層の表面全一部
酸化させる工程が加わる他は従来の装置を用いて製造で
きる。工程数は従来方法より一工程増えるが、陽極酸化
法を用いれば容易に酸化することができ、また突起物の
発生を防止できる効果は大きい。
As described above, the manufacturing method of the present invention can be manufactured using conventional equipment except for the step of oxidizing the entire surface of the first conductive layer. Although the number of steps is one more than the conventional method, the anodic oxidation method allows easy oxidation and is highly effective in preventing the formation of protrusions.

本実施例では第1導電層表面を酸化する方法として陽極
酸化法をあげているが、この方法に限定されることはな
い。この場合、zoa”c以下で行なうことが好ましい
が、突起物が形成てれない方法で酸化を行なう方法であ
れば良い。
In this embodiment, an anodic oxidation method is used as a method for oxidizing the surface of the first conductive layer, but the method is not limited to this method. In this case, it is preferable to carry out the oxidation at zoa''c or less, but any method that does not cause the formation of protrusions may be used.

例えば、配線パターンに従った第1導電層を形成した後
、酸化プラズマ雰囲気中に置き、第1導電層表面を酸化
する方法がある。この方法は、陽極+1化方法より工程
が難しくなるが、同様な効果は得ることができる。また
第2図に示すように配線パターンの第1導1を層の全表
面を酸化できるので横方向にも酸化膜を形成でき、導電
層の保護が十分に行々うことができる。
For example, there is a method of forming a first conductive layer according to a wiring pattern and then placing it in an oxidizing plasma atmosphere to oxidize the surface of the first conductive layer. Although this method requires more difficult steps than the anode+1 method, similar effects can be obtained. Further, as shown in FIG. 2, since the entire surface of the first conductor 1 of the wiring pattern can be oxidized, an oxide film can also be formed in the lateral direction, and the conductive layer can be sufficiently protected.

また1本発明の導電層に使用する金属はアルミ合金に限
定されることはなく楕々の金属を用いることができる。
Further, the metal used for the conductive layer of the present invention is not limited to aluminum alloy, and any metal can be used.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、絶縁層堆積の際に加えられる熱による
突起の発生が防止できるので導電層間の上縁性が良好で
M頴性の高い半導体装置と製造することができる。
According to the present invention, since the generation of protrusions due to heat applied during the deposition of the insulating layer can be prevented, it is possible to manufacture a semiconductor device with good upper edge properties between conductive layers and high M-type properties.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示し、第2図は他の実施例
を示す。 1・・・半導体基板、2・・・5L02層、3・・・第
1導it層、 4・・・酸化金属層、9・・・4電層間
絶縁層、  11・・・第2配線層。 (a) ([)) (C) (d) 第1図
FIG. 1 shows one embodiment of the invention, and FIG. 2 shows another embodiment. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... 5L02 layer, 3... First conductive IT layer, 4... Metal oxide layer, 9... 4 Interlayer insulation layer, 11... Second wiring layer . (a) ([)) (C) (d) Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)半導体素子が形成された半導体基板上に第1導電
層を形成する工程と、前記第1導電層の少なくとも一部
表面を酸化して第1絶縁層を形成する工程と、前記第1
絶縁層の上に第2絶縁層を形成する工程と、前記第2絶
縁層の上に第2導電層を形成する工程とを有することを
特徴とする半導体装置の製造方法。
(1) a step of forming a first conductive layer on a semiconductor substrate on which a semiconductor element is formed; a step of oxidizing at least a portion of the surface of the first conductive layer to form a first insulating layer;
A method for manufacturing a semiconductor device, comprising the steps of: forming a second insulating layer on the insulating layer; and forming a second conductive layer on the second insulating layer.
(2)前記第1絶縁層を形成する工程は、陽極酸化法を
用いて前記第1導電層の少なくとも一部表面を酸化する
ことを特徴とする特許請求の範囲第1項記載の半導体装
置の製造方法。
(2) The semiconductor device according to claim 1, wherein the step of forming the first insulating layer oxidizes at least a portion of the surface of the first conductive layer using an anodic oxidation method. Production method.
JP27856286A 1986-11-25 1986-11-25 Manufacture of semiconductor device Pending JPS63132457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27856286A JPS63132457A (en) 1986-11-25 1986-11-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27856286A JPS63132457A (en) 1986-11-25 1986-11-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63132457A true JPS63132457A (en) 1988-06-04

Family

ID=17598992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27856286A Pending JPS63132457A (en) 1986-11-25 1986-11-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63132457A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5610788A (en) * 1979-07-06 1981-02-03 Nakamura Kenkyusho:Kk Automatic inspection unit providing automatic shielding from light harmful to image pickup

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5610788A (en) * 1979-07-06 1981-02-03 Nakamura Kenkyusho:Kk Automatic inspection unit providing automatic shielding from light harmful to image pickup

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