JPS6312950U - - Google Patents
Info
- Publication number
- JPS6312950U JPS6312950U JP10619986U JP10619986U JPS6312950U JP S6312950 U JPS6312950 U JP S6312950U JP 10619986 U JP10619986 U JP 10619986U JP 10619986 U JP10619986 U JP 10619986U JP S6312950 U JPS6312950 U JP S6312950U
- Authority
- JP
- Japan
- Prior art keywords
- duplicated
- signal
- signals
- bus
- control lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000005856 abnormality Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Small-Scale Networks (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
第１図は本考案に係る装置の一例を示す構成ブ
ロツク図、第２図及び第３図は動作の一部を説明
するための波形図である。
Ｂ１，Ｂ２……制御ライン、ＤＲ１，ＤＲ２…
…制御ラインドライブ回路、ＲＥ……レシーバ回
路、ＥＤ……エラー検出回路。
FIG. 1 is a configuration block diagram showing an example of the device according to the present invention, and FIGS. 2 and 3 are waveform diagrams for explaining a part of the operation. B1, B2...control line, DR1, DR2...
...Control line drive circuit, RE...Receiver circuit, ED...Error detection circuit.
Claims (1)
並列非同期バスにおいて、制御ラインを２重化す
るとともに、この制御ラインに結合する各制御装
置内に、前記２重化した制御ラインの両方に同じ
信号を送出する制御ラインドライブ回路と、２重
化した制御ラインの両方の信号を入力し両信号が
バス上でアクテイブとなる場合のみ信号がアクテ
イブであると判断し他の場合はインアクテイブと
判断するレシーバ回路と、２重化した制御ライン
の両信号の不一致を検出しバス異常信号を出力す
るエラー検出回路とを設けたことを特徴とする冗
長化並列伝送装置。 In a multi-drop parallel asynchronous bus using an open collector, control lines are duplicated and the same signal is sent to both of the duplicated control lines in each control device connected to this control line. a line drive circuit, and a receiver circuit that inputs signals from both the duplicated control lines and determines that the signal is active only when both signals are active on the bus, and otherwise determines that the signal is inactive; A redundant parallel transmission device comprising: an error detection circuit that detects a mismatch between both signals of a duplicated control line and outputs a bus abnormality signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10619986U JPS6312950U (en) | 1986-07-10 | 1986-07-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10619986U JPS6312950U (en) | 1986-07-10 | 1986-07-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6312950U true JPS6312950U (en) | 1988-01-28 |
Family
ID=30981334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10619986U Pending JPS6312950U (en) | 1986-07-10 | 1986-07-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6312950U (en) |
-
1986
- 1986-07-10 JP JP10619986U patent/JPS6312950U/ja active Pending